A high-brightness LED chip and a method for manufacturing the same

Abstract

The application discloses a high-brightness LED chip and a preparation method thereof, and relates to the technical field of light-emitting semiconductors. The high-brightness LED chip comprises a P-type GaN layer, an ITO metal composite structure and an Ag reflecting layer. The ITO layer is deposited on the P-type GaN layer, and then the ITO layer is etched by using a wet etching method or a dry etching method to form a plurality of pit structures on the ITO layer. Then, the ITO metal composite structure is formed by depositing full metal particles in the pit structures. The ITO metal composite structure comprises the ITO layer and a plurality of metal blocks embedded in the ITO layer. Finally, the Ag mirror reflecting layer is deposited on the ITO metal composite structure. The ITO metal composite structure is formed by embedding the metal blocks in the ITO layer. The current can be fully expanded horizontally in the structure, and finally dispersedly enters the P-type GaN layer, so that the local current concentration in the chip is avoided, the working voltage of the chip is reduced, and high brightness is obtained.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of light-emitting semiconductor technology, in particular to a high-brightness LED chip and a preparation method thereof. BACKGROUND

[0002] Figure 1 A structural schematic diagram of a prior art high-power flip-chip LED chip is shown, including a substrate 1, an N-type GaN layer 2, an MQW quantum well layer 3, a P-type GaN layer 4, a first opening 410, a second opening 420, a sidewall protection layer 5, a transparent conductive layer 6, an Ag mirror reflection layer 7, an Ag mirror protection layer 8, a primary passivation layer 9, an N-type hole 10, an N-type current conductive layer 11, a P-type current conductive layer 12, a secondary passivation layer 13, an N-type electrode pad 14, and a P-type electrode pad 15.

[0003] Currently, ITO is mainly used as a transparent conductive layer in a high-power flip-chip LED chip, and ITO is an N-type oxide semiconductor material, indium tin oxide. In order to obtain high brightness, the thickness of the ITO layer in the high-power flip-chip LED chip is generally thin. Figure 2 A current path schematic diagram in the prior art high-power flip-chip LED chip is shown. The current flows in the direction of the arrow. When the current reaches the ITO layer from the Ag mirror reflection layer, if the conductivity of the ITO layer is poor, the current is likely to directly penetrate the ITO layer vertically into the P-type GaN layer without expanding horizontally to the entire ITO layer, resulting in local current concentration in the chip, a high working voltage, and reduced luminous brightness, which seriously restricts the development and application of flip-chip LED chips in high power and high current. SUMMARY

[0004] The present application aims to overcome the shortcomings of the prior art, and provides a high-brightness LED chip and a preparation method thereof. A metal block is embedded in the ITO layer to form an ITO metal composite structure, the current horizontal expansion capability is improved, the large current is horizontally expanded to the entire ITO layer, and then vertically enters the P-type GaN layer at each region of the ITO layer, thereby avoiding current concentration, reducing the working voltage of the chip, and obtaining high brightness.

[0005] The present application provides a high-brightness LED chip, which comprises a P-type GaN layer, an ITO metal composite structure arranged on the P-type GaN layer, and an Ag reflection layer arranged on the ITO metal composite structure, wherein the ITO metal composite structure comprises an ITO layer and a plurality of metal blocks embedded in the ITO layer.

[0006] Specifically, the ITO metal composite structure comprises an ITO cover layer and one or more ITO metal composite layers, the ITO cover layer is arranged on the one or more ITO metal composite layers, each ITO metal composite layer in the one or more ITO metal composite layers comprises an ITO layer and a plurality of metal blocks, and the plurality of metal blocks are arrayed and inlaid in the ITO layer.

[0007] Specifically, when the one or more ITO metal composite layers are two or more ITO metal composite layers, the plurality of metal blocks in adjacent ITO metal composite layers are staggered in the longitudinal direction and the projections of the plurality of metal blocks in the longitudinal direction do not overlap; and / or the thickness of the ITO cover layer and the thickness of the ITO metal composite layer satisfy the quarter wavelength reflection law.

[0008] Specifically, the thickness of the ITO layer is H, the thickness of the metal block is h, and the relationship between the H and the h is that:

[0009] and / or the relationship between the H and the h is that H = h.

[0010] Specifically, the metal block is a reverse circular cone or a reverse circular truncated cone structure, the width of the metal block is 10-20 um, and / or the ratio of the total area of the upper surfaces of the plurality of metal blocks to the area of the ITO layer in each ITO metal composite layer is 1:2-2:3.

[0011] The application further provides a preparation method of the high-brightness LED chip.

[0012] The ITO layer is deposited on the P-type GaN layer, the ITO layer is etched by using a wet etching method or a dry etching method to form a plurality of pit structures on the ITO layer, the pit structures are filled with metal particles to form an ITO metal composite structure, the ITO metal composite structure comprises an ITO layer and a plurality of metal blocks inlaid in the ITO layer, and an Ag mirror reflection layer is deposited on the ITO metal composite structure.

[0013] Specifically, when the ITO metal composite structure comprises one or more ITO metal composite layers, the ITO layer is etched by using a wet etching method or a dry etching method to form a plurality of pit structures on the ITO layer, and the pit structures are filled with metal particles to form an ITO metal composite structure, which comprises:

[0014] The first ITO layer is etched by using a wet etching method or a dry etching method to form a plurality of arrayed pit structures on the first ITO layer, and the first ITO layer is arranged on the P-type GaN layer.

[0015] Depositing metal particles in the pit structure of the first ITO layer to form a first ITO metal composite layer, the first ITO metal composite layer comprising the first ITO layer and a plurality of metal blocks inlaid in the first ITO layer;

[0016] Depositing a second ITO layer on the first ITO metal composite layer;

[0017] Etching the second ITO layer by wet etching or dry etching to form a plurality of array-arranged pit structures on the second ITO layer; the pit structures in the first ITO layer and the pit structures in the second ITO layer are arranged in longitudinal interlacing manner and the projections in the longitudinal direction do not coincide with each other;

[0018] Depositing metal particles in the pit structure of the second ITO layer to form a second ITO metal composite layer, the second ITO metal composite layer comprising the second ITO layer and a plurality of metal blocks inlaid in the second ITO layer;

[0019] According to the total number of the ITO layers remaining, forming a plurality of ITO metal composite layers by the method of preparing the second ITO metal composite layer;

[0020] Depositing an ITO cover layer on the topmost ITO metal composite layer, the ITO cover layer and the plurality of ITO metal composite layers forming an ITO metal composite structure.

[0021] Specifically, etching the ITO layer to form the plurality of pit structures at a rate of 1 / 2-2 / 3 of the area of the ITO layer; and / or depositing the metal particles in the plurality of pit structures at a rate of 1 / 2-2 / 3 of the area of the ITO layer. Specifically, etching the ITO layer to form the plurality of pit structures at a rate of 1 / 2-2 / 3 of the area of the ITO layer; and / or depositing the metal particles in the plurality of pit structures at a rate of 1 / 2-2 / 3 of the area of the ITO layer.

[0022] Specifically, etching the ITO layer to form the plurality of pit structures at a rate of 1 / 2-2 / 3 of the area of the ITO layer; and / or depositing the metal particles in the plurality of pit structures at a rate of 1 / 2-2 / 3 of the area of the ITO layer.

[0023] Specifically, when etching the first ITO layer to form the pit structures, etching from the upper surface of the first ITO layer to a depth of 1 / 2-2 / 3 of the first ITO layer to form the pit structures; when etching any non-first ITO layer in the plurality of ITO metal composite layers to form the pit structures, etching from the upper surface of the non-first ITO layer to the lower surface of the non-first ITO layer to form the pit structures.

[0024] The high-brightness LED chip provided by the application has the following advantages:

[0025] ​The ITO metal composite structure is inlaid with several metal blocks, which enhances the conductivity of the LED chip, so that the current is dispersed in the ITO metal composite structure first, fully expands laterally, and then enters the P-type GaN layer vertically in the regions where the structure contacts the P-type GaN layer, thereby avoiding local current concentration in the chip and reducing the working voltage of the chip to obtain high brightness.

[0026] The thickness of the ITO cover layer and the thickness of the ITO metal composite layer both meet the thickness requirement of the quarter wavelength (the wavelength refers to the wavelength of light in the material) reflection law, which can enhance the light reflection effect.

[0027] In addition, in the preparation method of the high-brightness LED chip, when the first ITO layer is etched to form the recess structure, that is, when the recess structure is etched in the ITO layer directly contacting the P-type GaN layer, the recess structure is formed by etching from the upper surface of the layer to 1 / 2-2 / 3 of the depth of the layer, generally 10-100 nm, which is the easiest to control for the process, and can avoid the metal blocks formed by depositing metal particles from directly contacting the P-type GaN layer, avoid the current from the contact between the metal blocks and the P-type GaN layer to concentrate into the P-type GaN layer, and also avoid damaging the P-type GaN layer during etching of the ITO layer;

[0028] When the recess structure is etched in any non-first ITO layer of the several ITO metal composite layers, the recess structure is formed by etching from the upper surface of the non-first ITO layer to the lower surface of the non-first ITO layer, and the metal blocks formed by depositing metal particles in such a recess structure can contact the ITO metal composite layers of the upper and lower adjacent layers, and after the several ITO metal composite layers are stacked, the current can be well conducted downward while being expanded laterally;

[0029] The ITO layer is etched using wet etching or dry etching, both of which can fix the etching rate and accurately control the etching depth by etching time;

[0030] Secondly, the total area of the several recess structures in the ITO layer accounts for 1 / 2-2 / 3 of the area of the ITO layer, and the specific proportion can be determined according to the actual effect of reducing the voltage and improving the brightness, and the recess structure is a 10-20um inverted cone or inverted table structure, which is arranged in an array in the ITO layer, facilitating etching processing, and the metal blocks formed by depositing metal particles are inverted cone or inverted table shape, which can be uniformly dispersed in the ITO layer, so that the actual effect of reducing the voltage and improving the brightness is optimized; and the area of a single recess structure can be further reduced, the number of recess structures is increased, and the density of the metal blocks formed by deposition is increased, and the effect is better;

[0031] The recess structures in the two adjacent ITO layers are staggered in the longitudinal direction and the projections in the longitudinal direction do not coincide, so that the deposited metal blocks are prevented from connecting to form vertical channels, thereby avoiding vertical current flow.

[0032] The ITO metal composite structure film prepared by the method is dense, has low void rate and good photoelectric performance. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 is a structural schematic diagram of an existing high-power flip LED chip;

[0034] Figure 2 is a schematic diagram of a current path in the existing high-power flip LED chip;

[0035] Figure 3 is a structural schematic diagram of a high-brightness LED chip in an embodiment of the present application;

[0036] Figure 4 is a schematic diagram of an ITO metal composite structure of a high-brightness LED chip in an embodiment of the present application;

[0037] Figure 5 is a schematic diagram of a current path in a high-brightness LED chip in an embodiment of the present application;

[0038] Figure 6 is a first flow schematic diagram of a preparation method of a high-brightness LED chip in an embodiment of the present application;

[0039] Figure 7 is a second flow schematic diagram of a preparation method of a high-brightness LED chip in an embodiment of the present application.

[0040] In the drawings, 1 is a substrate; 2 is an N-type GaN layer; 3 is an MQW quantum well layer; 4 is a P-type GaN layer; 410 is a first opening; 420 is a second opening; 5 is a side wall protection layer; 6 is a transparent conductive layer; 600 is an ITO metal composite structure; 610 is an ITO metal composite layer; 611 is a first ITO metal composite layer; 612 is a second ITO metal composite layer; 620 is an ITO cover layer; 601 is an ITO layer; 602 is a metal block; 7 is an Ag mirror reflection layer; 8 is an Ag mirror protection layer; 9 is a primary passivation layer; 10 is an N-type hole; 11 is an N-type current conductive layer; 12 is a P-type current conductive layer; 13 is a secondary passivation layer; 14 is an N-type electrode pad; and 15 is a P-type electrode pad. DETAILED DESCRIPTION

[0041] Clearly, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts fall within the protection scope of the present application.

[0042] Figure 3 The structure diagram of the high-brightness LED chip in the embodiment of the present application is shown, which comprises a substrate 1, an epitaxial layer stack arranged on the substrate 1; the epitaxial layer stack comprises an N-type GaN layer 2, an MQW quantum well layer 3 and a P-type GaN layer 4 arranged in sequence; a first opening 410 in a stepped shape is arranged along the edge position of the epitaxial layer stack, and a second opening 420 in an inverted trapezoidal shape is arranged close to the central region of the epitaxial layer stack; an ITO metal composite structure 600, an Ag mirror reflection layer 7 and an Ag mirror protection layer 8 are arranged in sequence on the P-type GaN layer 4; a sidewall protection layer 5 is arranged along the surface of the first opening 410 and the second opening 420; a primary passivation layer 9 is arranged along the surface of the sidewall protection layer 5 and the Ag mirror protection layer 8; an N-type hole 10 is arranged in the region close to the bottom of the second opening 420; a current conducting layer is arranged on the primary passivation layer 9, comprising an N-type current conducting layer 11 filling the second opening 420 and a P-type current conducting layer 12 contacting the Ag mirror protection layer 8 through the hole in the primary passivation layer 9; an N-type electrode pad 14 is arranged on the N-type current conducting layer 11, and a P-type electrode pad 15 is arranged on the P-type current conducting layer 12; a secondary passivation layer 13 is arranged along the surface of the primary passivation layer 9 at the edge, and the secondary passivation layer 13 is also arranged between the N-type region and the P-type region.

[0043] Figure 4 The structure diagram of the ITO metal composite structure of the high-brightness LED chip in the embodiment of the present application is shown, which comprises an ITO layer 601 and a plurality of metal blocks 602 inlaid in the ITO layer 601; the ITO metal composite structure 600 comprises an ITO cover layer 620 and one or more ITO metal composite layers 610, and the ITO cover layer 620 is arranged on the one or more ITO metal composite layers 610; each ITO metal composite layer 610 in the one or more ITO metal composite layers 610 comprises an ITO layer 601 and a plurality of metal blocks 602 inlaid in the ITO layer 601 in an array. When the one or more ITO metal composite layers 610 are two or more ITO metal composite layers 610, the plurality of metal blocks 602 in the adjacent ITO metal composite layers 610 are arranged in a staggered manner in the longitudinal direction and the projections in the longitudinal direction do not coincide.

[0044] When the one or more ITO metal composite layers 610 are two or more ITO metal composite layers 610, the number of ITO metal composite layers 610 is 2-8, preferably, the number of ITO metal composite layers 610 is 4-6; the more the number of layers, the more the content of metal blocks 602 in the ITO metal composite layers 610, the stronger the conductivity, and the lower the voltage; however, when light passes through the multiple ITO metal composite layers 610, light refraction and light absorption inevitably occur, resulting in light loss, affecting the light reflection ratio, and reducing the brightness of the LED chip; the fewer the number of layers, the less the content of metal blocks 602 in the ITO metal composite layers 610, the weaker the conductivity, and the higher the voltage; however, when light passes through the multiple ITO metal composite layers 610, the loss ratio caused by light refraction and light absorption is low, the light reflection ratio is high, and the brightness of the LED chip is high; when the number of ITO metal composite layers 610 is 4-6, the voltage and brightness reach a balance, and the effect is best, the voltage is reduced by 0.05-0.10 V, and the brightness is increased by 5%-10%.

[0045] Figure 5 The current path in the high-brightness LED chip in the embodiment of the application is shown, and the current flows in the direction of the arrow. When the current flows from the Ag mirror reflection layer 7 to the ITO metal composite structure 600, the conductivity is enhanced due to the embedding of the metal blocks 602 in the ITO metal composite structure 600, so that the current can fully expand in the structure, and the current is dispersed in the ITO metal composite structure 600 in the radial direction and then enters the P-type GaN layer 4 in the longitudinal direction at each region where the structure contacts the P-type GaN layer 4, thereby avoiding local current concentration in the chip and reducing the working voltage of the chip to obtain high brightness.

[0046] The thickness of the ITO cover layer 620 and the thickness of the ITO metal composite layer 610 satisfy the quarter-wavelength (the wavelength refers to the wavelength of light in the material) reflection law, which can enhance the light reflection effect.

[0047] The thickness of the ITO layer 601 is H, and the thickness of the metal block 602 is h, and the relationship between the H and the h is:

[0048] The relationship between the H and the h is H=h.

[0049] In the ITO metal composite layer 610 directly contacting the P-type GaN layer 4, the thickness of the metal block 602 is 1 / 2-2 / 3 of the thickness of the ITO layer 601, at this time, the upper surface of the metal block 602 coincides with the upper surface of the ITO layer 601, so that the metal block 602 can not directly contact the P-type GaN layer 4, and the current can diffuse to each region of the ITO layer 601 and then enter the P-type GaN layer 4.

[0050] In the ITO metal composite layer 610 stacked on the ITO metal composite layer 610, the thickness of the metal block 602 is equal to the thickness of the ITO layer 601. The metal block 602 can contact the ITO metal composite layers 610 above and below. When several ITO metal composite layers 610 are stacked together, the current can be extended laterally and conducted downwards well.

[0051] The metal block 602 is composed of one of Ag, Al, or Cr, which have good electrical conductivity. The metal block 602 has an inverted conical or frustum-shaped structure and a width of 10-20 μm, which can be more densely arrayed and embedded in the ITO layer 601 to obtain better conductivity. The ratio of the total area of ​​the upper surface of several metal blocks 602 in each ITO metal composite layer 610 to the area of ​​the ITO layer 601 ranges from 1:2 to 2:3, which can be adjusted according to the actual effect of reducing voltage and increasing brightness to obtain the best effect.

[0052] Figure 6 This diagram illustrates the first process of a high-brightness LED chip fabrication method according to an embodiment of the present invention.

[0053] The method for fabricating this high-brightness LED chip includes the following steps:

[0054] S1. Deposit an ITO layer 601 on the p-type GaN layer 4;

[0055] A low-power deposition process is required to deposit the ITO layer 601 on the P-type GaN layer 4 to reduce damage to the P-type GaN layer 4. Specifically, on the P-type GaN layer 4, a low-power deposition process is used to deposit the ITO layer 601. The deposition rate of the ITO layer 601 is related to the degree of damage to the p-type GaN layer 4 and the quality of the ITO layer 601. It is a relatively small deposition rate range. Depositing the ITO layer 601 at this rate causes less damage to the P-type GaN layer 4, and the interface resistance and voltage between the deposited ITO layer 601 and the P-type GaN layer 4 are low. At the same time, the ITO layer 601 deposited at this rate has good compactness. In addition, using a small deposition rate is also beneficial for accurately controlling the deposition thickness of the ITO layer 601.

[0056] S2. The ITO layer 601 is etched using a wet or dry method to form several pit structures on the ITO layer 601.

[0057] The ITO layer 601 is etched using either wet etching or dry etching. Both methods can fix the etching rate and precisely control the etching depth by the etching time. The pit structure is arranged in an array on the ITO layer 601, which facilitates precise processing and ensures that the pit structure is evenly distributed.

[0058] The recess structure is formed by etching the upper surface of the ITO layer 601 in direct contact with the P-type GaN layer 4 to a depth of 1 / 2-2 / 3 of the ITO layer, typically 10-100 nm, which is the most easily controlled in the process and can avoid the metal block 602 formed by the deposited metal particles from being in direct contact with the P-type GaN layer 4, and can avoid the current from being concentrated into the P-type GaN layer 4 from the contact between the metal block 602 and the P-type GaN layer 4, and can also avoid damage to the P-type GaN layer 4 during etching of the ITO layer 601.

[0059] A small etching rate will result in a long process time, and a large etching rate will result in an inaccurate control of the etching depth during etching of the ITO layer 601, and specifically, an etching rate of 10-100 nm / min is more appropriate.

[0060] Secondly, 1 / 2-2 / 3 of the area of the ITO layer is etched to form a plurality of arrayed recess structures, so that the total area of the metal block 602 formed by the subsequent deposition is large enough, and the plurality of metal blocks 602 are arrayed in the ITO layer, which can make the current spreading effect the strongest; the recess structure is etched into a rounded cone or rounded table structure with a notch width of 10-20 um, which is the most easily realized in the actual process, and also facilitates the subsequent deposition of metal particles to densely and tightly fill the recess structure, avoiding the generation of gaps; once a gap is generated, the gap area will heat and expand when the LED chip is used at high temperature and large current, and then it will explode, resulting in abnormal failure of the LED chip.

[0061] Moreover, etching the recess structure into a rounded cone or rounded table structure with a notch width of 10-20 um facilitates the reduction of the area of a single recess structure, the increase of the number of recess structures, and the more dense array of the recess structures, so that more dense metal blocks 602 are formed by subsequent deposition, and better conductivity is obtained.

[0062] S3, depositing metal particles in the recess structure to form an ITO metal composite structure 600; the ITO metal composite structure 600 includes an ITO layer 601 and a plurality of metal blocks 602 inlaid in the ITO layer 601; the film layer of the ITO metal composite structure 600 is dense, has a low void rate, and has good photoelectric performance;

[0063] The metal particle deposition can use a PVD physical vapor deposition process such as magnetron sputtering, EBM electron beam evaporation or Thermal thermal evaporation process, preferably, the metal particles are deposited by using a magnetron sputtering process, and the deposition rate can be accurately controlled by power and gas flow, and the metal particle deposition rate is controlled at 10-100 nm / min. ​If the deposition rate is too low, the equipment hardware / software and process parameters cannot be controlled; if the deposition rate is too high, gaps are likely to appear when the metal particles are deposited and stacked, resulting in incomplete filling of the metal particles, forming voids between particles, which increases the voltage and reduces the brightness.

[0064] S4. Deposit an Ag mirror reflective layer 7 on the ITO metal composite structure 600;

[0065] The thickness of the Ag mirror reflective layer 7 can be set to be thicker, for Used for reflecting light. The Ag mirror reflective layer 7 generally includes an Ag monoproton layer and a primary protective layer; the thickness of the Ag monoproton layer affects its reflectivity, and is generally set to [value missing]. In this region, the Ag monolayer has the highest reflectivity; the primary protective sublayer is made of one or more organic combinations of metals such as TiW, Ti, Ni, or Pt, and is generally set as follows: If the layer is too thin, it will not provide sufficient protection for the Ag monoproton layer, causing the Ag monoproton layer to precipitate and be oxidized, resulting in low conductivity and low reflectivity of the Ag monoproton layer; if it is too thick, it will lead to low process efficiency and high process cost.

[0066] Figure 7 The diagram illustrates a second process flow of a high-brightness LED chip fabrication method according to an embodiment of the present invention. When the ITO metal composite structure 600 includes several ITO metal composite layers 610, the fabrication method of the high-brightness LED chip includes the following steps:

[0067] S21. Deposit the first ITO layer on the P-type GaN layer 4;

[0068] by The first ITO layer was deposited at a rate of [missing information], followed by [missing information]. Depositing any non-first ITO layer at a certain rate can make different ITO layers 601 bond tightly together, forming a single unit, reducing interface resistance, enhancing conductivity between different ITO layers 601, and also reducing light refraction loss at the interface between different ITO layers 601.

[0069] S22. The first ITO layer is etched using a wet or dry method to form a plurality of arrayed pit structures on the first ITO layer, wherein the first ITO layer is located on the p-type GaN layer 4; the pit structures are formed by etching the first ITO layer, that is, the pit structures are formed by etching in the ITO layer 601 that is in direct contact with the p-type GaN layer 4, and the pit structures are formed by etching from the upper surface of the layer down to 1 / 2 to 2 / 3 of the depth of the layer.

[0070] S23, depositing metal particles in the pit structure of the first ITO layer to form a first ITO metal composite layer 611, the first ITO metal composite layer 611 comprising the first ITO layer and a plurality of metal blocks embedded in the first ITO layer;

[0071] S24, depositing a second ITO layer on the first ITO metal composite layer;

[0072] S25, etching the second ITO layer by wet etching or dry etching to form a plurality of array-arranged pit structures on the second ITO layer; the pit structures in the first ITO layer and the pit structures in the second ITO layer are arranged in a staggered manner in the longitudinal direction and the projections in the longitudinal direction do not overlap, so as to avoid the metal blocks 602 formed by the deposited metal particles to be connected to form vertical channels, thereby avoiding the vertical current flow.

[0073] Moreover, when etching the pit structure in any non-first ITO layer (the non-first ITO layer refers to any ITO layer arranged on the first ITO layer) of the plurality of ITO metal composite layers 610, the pit structure is formed by etching through from the upper surface of the non-first ITO layer to the lower surface of the non-first ITO layer, and the metal blocks 602 formed by the metal particles deposited in the pit structure can be in contact with the ITO metal composite layers 610 of the upper and lower adjacent layers, and after the plurality of ITO metal composite layers 610 are stacked, the current can be expanded in the lateral direction and also be well conducted downward.

[0074] S26, depositing metal particles in the pit structure of the second ITO layer to form a second ITO metal composite layer 612, the second ITO metal composite layer 612 comprising the second ITO layer and a plurality of metal blocks embedded in the second ITO layer;

[0075] S27, forming a plurality of ITO metal composite layers 610 according to the preparation method of the second ITO metal composite layer 612 according to the remaining total number of the ITO layers 601;

[0076] S28, depositing an ITO cover layer 620 on the topmost ITO metal composite layer 610, and the ITO cover layer 620 and the plurality of ITO metal composite layers 610 form an ITO metal composite structure 600;

[0077] S29, depositing an Ag mirror reflection layer 7 on the ITO metal composite structure 600.

[0078] By controlling the area, depth, arrangement manner, etc. of the pit structure, the metal blocks 602 formed by deposition are uniformly and staggeredly embedded in the ITO metal composite structure 600 (as shown in FIG. 6B), and in the high-brightness LED chip using the ITO metal composite structure 600, the current is expanded in the lateral direction and also well conducted downward. Figure 4 Figure 5 ​As shown, the current flows from the Ag mirror layer 7 to the ITO metal composite structure 600, and the current is enhanced by the metal blocks 602 embedded in the ITO metal composite structure 600, so that the current can fully spread laterally in the structure, and then spread radially in the ITO metal composite structure 600 and longitudinally into the P-type GaN layer 4 in the regions where the structure contacts the P-type GaN layer 4, thereby avoiding local current concentration in the chip and reducing the working voltage of the chip to obtain high brightness. The conductivity is generally quantified by resistivity, and the ITO metal composite structure 600 reduces the resistivity by 30% to 50%, which is reflected in the LED chip as a voltage reduction of 0.05 to 0.1 V, and the brightness is increased by 5% to 10%.

[0079] The high-brightness LED chip and the preparation method thereof provided by the embodiments of the present application are described in detail above, and the principles and implementation manners of the present application are described by using specific examples in this paper. The above description of the embodiments is only used to help understand the method of the present application and its core idea. Meanwhile, for those skilled in the art, the specific implementation manners and application ranges can be changed according to the idea of the present application. In summary, the content of the specification should not be understood as a limitation of the present application.

Claims

1. A high-brightness LED chip, characterized by, It includes a p-type GaN layer, an ITO metal composite structure disposed on the p-type GaN layer, and an Ag reflective layer disposed on the ITO metal composite structure, wherein: The ITO metal composite structure includes an ITO layer and several metal blocks, wherein the several metal blocks are embedded in the ITO layer; The ITO metal composite structure includes an ITO cap layer and one or more ITO metal composite layers, wherein the ITO cap layer is disposed on the one or more ITO metal composite layers; each of the one or more ITO metal composite layers includes an ITO layer and a plurality of metal blocks, wherein the plurality of metal blocks are arrayed and embedded in the ITO layer; When the ITO metal composite layer consists of two or more ITO metal composite layers, several metal blocks in adjacent ITO metal composite layers are arranged alternately in the longitudinal direction and their projections in the longitudinal direction do not overlap; and / or The thickness of the ITO capping layer and the thickness of the ITO metal composite layer satisfy the quarter-wavelength reflection law.

2. The high-brightness LED chip of claim 1, wherein, The thickness of the ITO layer is H, and the thickness of the metal block is h. The relationship between H and h is as follows: And / or the relationship between H and h is: H = h.

3. The high-brightness LED chip of claim 1, wherein, The metal block has an inverted conical or frustum-shaped structure; the width of the metal block is 10–20 μm; and / or The ratio of the total area of ​​the upper surface of the plurality of metal blocks in each ITO metal composite layer to the area of ​​the ITO layer ranges from 1:2 to 2:

3.

4. A method of fabricating a high-brightness LED chip, comprising: Includes the following steps: Deposit an ITO layer on a p-type GaN layer; The ITO layer is etched using a wet or dry method to form several pit structures on the ITO layer. Metal particles are deposited in the pit structures to form an ITO metal composite structure. The ITO metal composite structure includes an ITO layer and several metal blocks embedded in the ITO layer. An Ag mirror reflective layer is deposited on the ITO metal composite structure; When the ITO metal composite structure comprises several ITO metal composite layers, the step of etching the ITO layers using wet or dry methods to form several pit structures on the ITO layers, and depositing metal particles in the pit structures to form the ITO metal composite structure, includes: The first ITO layer is etched using a wet or dry method to form a plurality of arrayed pit structures on the first ITO layer, wherein the first ITO layer is located on a P-type GaN layer. A first ITO metal composite layer is formed by depositing metal particles in the pit structure of the first ITO layer. The first ITO metal composite layer includes the first ITO layer and a number of metal blocks embedded in the first ITO layer. A second ITO layer is deposited on the first ITO metal composite layer; The second ITO layer is etched using a wet or dry method to form several arrayed pit structures on the second ITO layer; the pit structures in the first ITO layer and the pit structures in the second ITO layer are staggered in the longitudinal direction, and their projections in the longitudinal direction do not overlap. A second ITO metal composite layer is formed by depositing metal particles in the pit structure of the second ITO layer. The second ITO metal composite layer includes a second ITO layer and a number of metal blocks embedded in the second ITO layer. Based on the remaining total number of ITO layers, several ITO metal composite layers are formed according to the method for preparing a second ITO metal composite layer; An ITO capping layer is deposited on the topmost ITO metal composite layer, and the ITO capping layer and the plurality of ITO metal composite layers form an ITO metal composite structure.

5. The method for preparing a high-brightness LED chip as described in claim 4, characterized in that, The ITO layer is etched at a rate of 10–20 Å / s to form the plurality of pit structures; and / or The metal particles are deposited in the plurality of pit structures at a rate of 1 to 5 Å / s.

6. The method for preparing a high-brightness LED chip as described in claim 4, characterized in that, The ITO layer is etched to form a plurality of arrayed pit structures covering 1 / 2 to 2 / 3 of its area; and / or The pit structure is etched into an inverted cone or frustum shape with a notch width of 10-20 μm.

7. The method for preparing a high-brightness LED chip as described in claim 4, characterized in that, When etching the first ITO layer to form the pit structure, the pit structure is formed by etching from the upper surface of the first ITO layer downwards to 1 / 2 to 2 / 3 of the depth of the first ITO layer. When the pit structure is formed by etching any non-first ITO layer in a plurality of ITO metal composite layers, the pit structure is formed by etching from the upper surface of the non-first ITO layer to the lower surface of the non-first ITO layer.

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