A method for improving the signal transmission integrity of PCB holes

Abstract

The present invention relates to a method for improving the signal transmission integrity of PCB holes. The method is to separately fabricate the L1 to Lm layers, the intermediate layer, and the L(n-1) to Ln layers first, and then fabricate the above-mentioned completed L1 to Ln layers together. Both m and n are even numbers greater than 6, and m < n. Among them, in the fabrication of the L1 to Ln layers, the copper deposition and panel electroplating are first completed sequentially in two processes. The holes are metallized through copper deposition, and the electroplated layer is thickened by flash plating on the metallized holes through panel electroplating. After etching and stripping the film, the flash-plated copper of the intermediate layer and the L(n-1) to Ln layers corresponding to the back-drilled hole positions is etched away through flash etching, ensuring the integrity of the back-drilled holes and other position holes of the L1 to Lm layers, retaining the Ring of the Lm layer, and making the back-drilled holes have no copper after the Lm layer, achieving zero stub. The method for improving the signal transmission integrity of PCB holes in the present invention effectively solves the problem that the stub generated by the back-drilling method in the prior art affects the signal transmission integrity of the back-drilled holes, and improves the product quality.

Description

Technical Field

[0001] The present invention relates to the technical field of PCB board production and processing, and specifically provides a method for improving the signal transmission integrity of PCB holes. Background Art

[0002] With the increasing requirements of products, in order to ensure the integrity of the model, the design requirements for products are getting higher and higher. Often, to meet the signal requirements, the customer's design requires that the Ring of the inner layer connection position of the plug hole be reserved, the copper on the hole wall at the protruding position be etched off, and the inner layer Ring be exposed for welding. Taking a multilayer board as an example, to ensure the signal, the conventional manufacturing method is: inner layer pattern → lamination → outer layer drilling → copper electroplating on the board → outer layer pattern → pattern electroplating → back drilling (drilling to the target layer by drilling) → outer layer etching → outer layer AOI → subsequent processes. Among them, the lamination process is to laminate the board with the inner layer circuit pattern into a multilayer board, the copper electroplating on the board process is to flash electroplate the board with 6 - 8μm, the pattern electroplating process is to electroplate to the copper thickness required by the customer. After pattern electroplating, the back drilling method is used to drill to the target layer, and then the circuit pattern is made. By alkaline etching, the Stub after back drilling can be reduced, and the signal loss can be reduced. The existing methods all use the back drilling method to drill to the target layer. This method cannot meet the integrity of the Ring, or there is stub residue in the inner layer hole, and zero stub cannot be achieved, resulting in signal loss and unable to meet customer requirements. Summary of the Invention

[0003] The present invention provides a method for improving the signal transmission integrity of PCB holes. Using this method for PCB board production can effectively reduce production costs, improve product quality, meet the zero Stub required by customers, ensure the integrity of the signal transmission of the back drilled hole, and at the same time meet the production of the Ring required by customers to meet the customer's welding needs.

[0004] To achieve the above object, it is realized through the following technical solutions.

[0005] A method for improving the signal transmission integrity of PCB holes, the method is to first separately produce layers L1 to Lm, the intermediate layer, and layers L(n - 1) to Ln, and then produce the above-mentioned L1 to Ln layers together, where m and n are both even numbers greater than 6, m is the number of target layers, n is the number of the last layer, and m < n. Among them,

[0006] In the production of L1 to Ln layers, copper plating and board electroplating are first separated and completed in two processes in sequence. Copper plating is used to metallize the holes, and the board electroplating is used to thicken the electroplating layer. After etching and film stripping, the flash-plated copper in the intermediate layer corresponding to the back-drilled hole position and the L(n-1) to Ln layers is etched away by flash etching to ensure the integrity of the back-drilled holes and holes in other positions in the L1 to Lm layers, so that the ring of the Lm layer is retained and there is no copper in the back-drilled hole after Lm, achieving zero stub.

[0007] In the above technical solution, a pressed board is formed by pressing all core boards at once in the prior art, and the core board is first divided into several parts, namely, L1 layer to Lm target layer, middle layer, and L(n-1) to Ln layer, which are manufactured separately. In the manufacturing of L1 layer to Lm target layer, back-drilled holes are drilled, and then the sub-boards manufactured in the three steps are stacked and pressed together to form an overall pressed board. In the manufacturing of the overall pressed board, copper metallization holes are first used, and the electroplating layer is thickened by electro-flash plating. Then, in the subsequent flash etching process, the board is electro-flash plated to the flash plating layer below the target layer and etched away. Compared with the traditional back drilling method, this method can achieve zero stub in back drilling, effectively ensure the integrity of the back drilling hole signal transmission, and at the same time meet the customer's needs for ring production to meet welding requirements.

[0008] Furthermore, the method for improving the signal transmission integrity of a PCB hole comprises the following steps:

[0009] S1: The production of L1 to Lm layers, including the front process → first inner layer pattern → lamination → drilling → copper plate electroplating → second inner layer pattern → post-process. The first inner layer pattern is used to produce other inner layer patterns except Lm, and the second inner layer pattern is used to produce the inner layer pattern of the Lm layer. Drilling is done to drill holes at the locations where the back drilling holes of the L1 to Lm layers need to be connected;

[0010] S2: Production of layers L(m+1) to L(n-2), including cutting → inner layer patterning → grooving → post-processing, where the grooving is performed at the back-drilling positions corresponding to the L1 to Lm layers, hollowing out the core plates of the L(m+1) to L(n-2) layers;

[0011] S3: Production of L(n-1) to Ln layers, including cutting → inner layer patterning → post-processing;

[0012] S4: Production of L1 to Ln layers, front process → PP window opening → pressing → outer layer drilling → forming gong groove → copper plating → board electroplating → outer layer pattern → pattern electroplating → outer layer etching → film stripping → flash etching → back process, among which copper plating and board electroplating are divided into two processes. Copper plating is used to metallize the drilled holes in the previous steps, and board electroplating performs flash plating on the metallized holes to thicken the electroplating layer; flash etching is set after outer layer etching and film stripping, and is used to etch away the flash-plated thickened copper on the back-drilled holes of the L(m+1) to Ln layers, ensuring the integrity of the back-drilled holes and holes in other positions of the L1 to Lm layers, meeting the requirements of ring retention. At this time, there is no copper in the L(m+1) to Ln layers, achieving zero stub.

[0013] Furthermore, in step S1, the copper plate is used to plate the via holes drilled in the drilling step to the copper thickness required by the customer.

[0014] Furthermore, in step S4, the previous process includes the selection of a PP layer, and the PP layer adopts non-glue PP; the PP windowing will be performed at the position corresponding to the back drilling hole of the L1 to Lm layers.

[0015] Furthermore, the size of the PP window is 2 mil larger than the design hole required by the customer.

[0016] Furthermore, in step S4, the outer layer drilling is used to drill through holes from the L1 to Ln layers.

[0017] Furthermore, in step S4, the forming gong groove adopts a depth-controlled gong method to gong out the back-drilled holes from the L(m+1) to Ln layers, so that the back-drilled holes from the L1 to Ln layers are conductive.

[0018] Furthermore, in step S4, graphic electroplating is used to plate the locations where copper needs to be thickened to the copper thickness required by the customer using a secondary copper process. In this step, the back-drilled hole locations corresponding to the L1 to Lm layers are covered with dry film, and the dry film is stripped after the outer layer is etched.

[0019] Furthermore, in step S4, the plate is electroplated with a 2-3 μm copper layer on the metallized holes.

[0020] Furthermore, in step S4, flash etching is performed using a carrier etching method to etch away 2-3 μm of flash-plated copper on the back-drilled holes from the L(m+1) to Ln layers.

[0021] Compared with the prior art, the method of improving the signal transmission integrity of PCB holes in the present invention has the following beneficial effects:

[0022] The method for improving the signal transmission integrity of PCB holes of the present invention forms a pressed board by pressing all core boards at once in the prior art. The method is divided into several parts, namely, first dividing the core board into the L1 layer to the Lm target layer, the middle layer, and the L(n-1) to Ln layer, and manufacturing them separately. In the manufacturing of the L1 layer to the Lm target layer, back-drilled holes are drilled, and then the sub-boards manufactured in the three steps are stacked and pressed together to form an overall pressed board. In the manufacturing of the overall pressed board, copper metallization holes are first used, and the electroplating layer is thickened by electro-flash plating. Then, in the subsequent flash etching process, the board is electro-flash plated to the flash plating layer below the target layer and etched away. Compared with the traditional back drilling method, the back drilling can achieve zero stub, effectively ensuring the integrity of the back drilling hole signal transmission, and at the same time, it can also meet the ring production required by customers to meet welding requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 Create product stackup diagrams for existing technologies;

[0024] Figure 2 Schematic diagram of the product stacking structure of Example 1 of the method for improving the signal transmission integrity of a PCB hole according to the present invention;

[0025] Figure 3 Schematic diagram of the product stacking structure of Example 2 of the method for improving the signal transmission integrity of a PCB hole according to the present invention;

[0026] Figure 4 Schematic diagram of the product stacking structure of Example 3 of the method for improving the signal transmission integrity of PCB holes of the present invention. DETAILED DESCRIPTION

[0027] The method for improving the signal transmission integrity of a PCB hole according to the present invention will be described in further detail below with reference to specific embodiments and accompanying drawings.

[0028] Example 1

[0029] Reference Figure 2 A non-limiting embodiment of the present invention is a method for improving the signal transmission integrity of a PCB hole. The method described in this embodiment is performed using an 8-layer board as an example. Specifically, the method is to first separately manufacture layers L1 to L4, layers L5 to L6, and layers L7 to L8, and then combine the manufactured layers L1 to L8 together, wherein:

[0030] In the production of L1 to L8 layers, copper plating and electroplating are first separated and completed in two separate processes. Copper plating is used to metallize the holes, and electroplating is used to thicken the electroplating layer. After etching and film stripping, the flash-plated copper on the L5 to L8 layers corresponding to the position of back-drilled hole 2 is etched away by flash etching, ensuring the integrity of back-drilled hole 2 and holes in other positions on the L1 to L4 layers, retaining the ring 1 of the L4 layer, and ensuring that there is no copper after the back-drilled hole 2 on the L4 layer, achieving zero stub.

[0031] Reference Figure 2 In a non-limiting embodiment of the present invention, the method for improving the signal transmission integrity of a PCB hole comprises the following steps:

[0032] S1: The production of L1 to L4 layers includes the front process → the first inner layer pattern → lamination → drilling → copper plate electroplating → the second inner layer pattern → the back process, wherein the first inner layer pattern is used to produce the inner layer patterns of the L2 and L3 layers, and the second inner layer pattern is used to produce the inner layer pattern of the L4 layer. The holes at the positions where the back drilling holes 2 of the L1 to L4 layers need to be connected are drilled; in this step, the inner layer pattern is produced twice, once before lamination and once after lamination, that is, the L4 layer is separated and carried out after lamination, which can effectively ensure that the Ring 1 of the L4 layer, i.e. the target layer, is retained to meet customer welding requirements;

[0033] S2: The production of L5 to L6 layers, including cutting → inner layer patterning → grooving → post-processing. Among them, the grooving plate grooving the L5 to L6 core board at the position corresponding to the back drilling 2 of the L1 to L4 layers; the L5 to L6 layer grooving provides a tolerance value for the subsequent depth control groove cover after the motherboard is pressed together, to prevent insufficient reserved thickness and grooving to the target inner layer Ring 1, ensuring the integrity of the target layer Ring 1;

[0034] S3: Production of L7 to L8 layers, including cutting → inner layer patterning → post-processing; L7 to L8 layers only undergo inner layer patterning without lamination, effectively preventing problems such as uneven slot positions caused by grooves during subsequent motherboard pressing, thus ensuring quality for subsequent motherboard pressing;

[0035] S4: Production of L1 to L8 layers, front process → PP window opening → pressing → outer layer drilling → forming gong groove → copper plating → board electroplating → outer layer pattern → pattern electroplating → outer layer etching → film stripping → flash etching → back process, wherein copper plating and board electroplating are divided into two processes, copper plating is used to metallize the drilled holes in the previous step, and board electroplating performs flash plating on the metallized holes to thicken the electroplated layer. In this embodiment, board electroplating flash-plates a 2-3μm copper layer on the metallized holes; flash etching is arranged after outer layer etching and film stripping, and is used to etch away the flash-plated thickened copper on the back-drilled holes 2 of the L5 to L8 layers. In this embodiment, flash etching adopts a carrier etching method to etch away the flash-plated 2-3μm copper on the back-drilled holes 2 of the L5 to L8 layers, ensuring the integrity of the back-drilled holes 2 and other holes in the L1 to L4 layers, and meeting the retention of Ring 1. At this time, L5 to L8 layers are copper-free, achieving zero stub, ensuring the integrity of the signal transmission of the back-drilled holes 2, and improving product quality.

[0036] Reference Figure 2 In a non-limiting embodiment of the present invention, in step S1, the copper plate is electroplated to the copper thickness required by the customer on the via holes drilled in the drilling step, so that the copper thickness on the L1 to L4 layers, that is, the back-drilled hole 2 from L1 to the target layer, meets the requirements, ensuring product quality.

[0037] Reference Figure 2 In a non-limiting embodiment of the present invention, in step S4, the preceding process includes selecting a PP layer 4 using non-adhesive PP. PP windowing is performed at locations corresponding to the back-drilled holes 2 in layers L1 through L4. The use of non-adhesive PP ensures uniform and stable bonding between the PP and each sub-panel 3 during subsequent motherboard lamination. The PP windowing provides a foundation and guarantee for subsequent outer layer drilling, thereby improving product manufacturing efficiency. In this embodiment, the PP windowing is 2 mil larger than the customer's required hole design, ensuring that the hole size at the PP windowing after subsequent motherboard lamination meets the customer's requirements.

[0038] Reference Figure 2 In a non-limiting embodiment of the present invention, in step S4, the outer layer drilling is used to drill through holes in the L1 to L8 layers to make each layer conductive and ensure product quality.

[0039] Reference Figure 2 In a non-limiting embodiment of the present invention, in step S4, the forming gong groove adopts a depth-controlled gong method to gong out the back-drilled holes 2 of the L5 to L8 layers, so that the back-drilled holes 2 of the L1 to L8 layers are conductive.

[0040] Reference Figure 2 In a non-limiting embodiment of the present invention, in step S4, pattern electroplating is used to plate the locations where copper thickening is required to the copper thickness required by the customer using a secondary copper process. In this step, the back-drilled hole 2 locations corresponding to the L1 to L4 layers are covered with a dry film, and the dry film is stripped after the outer layer is etched.

[0041] Reference Figure 2 The method for improving the signal transmission integrity of PCB holes of the present invention forms a pressed board by pressing all core boards at once in the prior art, and first divides the core board into several parts, namely, L1 layer to L4 target layer, L5 to L6 layer, and L7 to L8 layer, and manufactures them separately. In the manufacture of L1 layer to L4 target layer, back-drilled holes 2 are drilled, and then the sub-boards 3 manufactured in the three steps are stacked and pressed together to form an overall pressed motherboard. In the manufacture of the overall pressed motherboard, copper metallization holes are first used, and the electroplating layer is thickened by electro-flash plating. Then, in the subsequent flash etching process, the board is electro-flash plated to below the target layer and the flash plating layer is etched away. Compared with the traditional back drilling method, the back drilling can achieve zero stub, effectively ensure the integrity of the signal transmission of the back drilling hole 2, and at the same time, it can also meet the production of the Ring 1 required by customers to meet the welding requirements.

[0042] Example 2

[0043] Reference Figure 3 A non-limiting embodiment of the present invention is a method for improving the signal transmission integrity of a PCB hole. The method described in this embodiment is performed using a 12-layer board as an example. Specifically, the method is to first separately manufacture layers L1 to L6, layers L7 to L10, and layers L11 to L12, and then combine the above-made layers L1 to L12. Specifically, the method includes the following steps:

[0044] S1: The production of L1 to L6 layers includes the front process → the first inner layer pattern → lamination → drilling → copper plate electroplating → the second inner layer pattern → the back process, wherein the first inner layer pattern is used to produce the inner layer pattern of L2 to L5 layers, and the second inner layer pattern is used to produce the inner layer pattern of L6 layer. The holes at the positions where the back drilling holes 2 of L1 to L6 layers need to be connected are drilled; in this step, the inner layer pattern is produced twice, once before lamination and once after lamination, that is, the L6 layer is separated and carried out after lamination, which can effectively ensure that the Ring 1 of the L6 layer, i.e. the target layer, is retained to meet customer welding requirements;

[0045] S2: The production of L7 to L10 layers includes cutting → inner layer patterning → grooving → post-processing. Among them, the grooving plate is used at the position of back drilling 2 corresponding to the L1 to L6 layers to grooving the L7 to L10 core boards. This provides a tolerance value for the subsequent depth control groove cover after the motherboard is pressed together, preventing insufficient reserved thickness and grooving to the target inner layer Ring 1, ensuring the integrity of the target layer Ring 1;

[0046] S3: Production of L11 to L12 layers, including cutting → inner layer patterning → post-processing; L11 to L12 layers only undergo inner layer patterning without lamination, effectively preventing problems such as uneven trough position during subsequent motherboard pressing due to grooves, thus ensuring quality for subsequent motherboard pressing;

[0047] S4: Production of L1 to L12 layers, front process → PP window opening → pressing → outer layer drilling → forming gong groove → copper plating → board electroplating → outer layer pattern → pattern electroplating → outer layer etching → film stripping → flash etching → back process, wherein copper plating and board electroplating are divided into two processes, copper plating is used to metallize the drilled holes in the previous step, and board electroplating performs flash plating on the metallized holes to thicken the electroplated layer. In this embodiment, board electroplating flash-plates a 2-3μm copper layer on the metallized holes; flash etching is arranged after outer layer etching and film stripping, and is used to etch away the flash-plated thickened copper on the back-drilled holes 2 of the L7 to L12 layers. In this embodiment, flash etching adopts a carrier etching method to etch away the flash-plated 2-3μm copper on the back-drilled holes 2 of the L7 to L12 layers, ensuring the integrity of the back-drilled holes 2 and other holes in the L1 to L6 layers, and meeting the retention of Ring 1. At this time, the L7 to L12 layers are copper-free, achieving zero stub, ensuring the integrity of the signal transmission of the back-drilled holes 2, and improving product quality.

[0048] Reference Figure 3 In a non-limiting embodiment of the present invention, in step S1, the copper plate is electroplated to the copper thickness required by the customer on the via holes drilled in the drilling step, so that the copper thickness on the L1 to L6 layers, that is, the back-drilled hole 2 from L1 to the target layer, meets the requirements, ensuring product quality.

[0049] Reference Figure 3 In a non-limiting embodiment of the present invention, in step S4, the preceding process includes selecting a PP layer 4 using non-adhesive PP. PP windows are created at locations corresponding to the back-drilled holes 2 in layers L1 through L6. The use of non-adhesive PP ensures uniform and stable bonding between the PP and each sub-panel 3 during subsequent motherboard lamination. The PP windows provide a foundation and guarantee for subsequent outer layer drilling, thereby improving product manufacturing efficiency. In this embodiment, the PP window size is 2 mil larger than the customer's required design hole, ensuring that the hole size at the PP window after subsequent motherboard lamination meets the customer's requirements.

[0050] Reference Figure 3 In a non-limiting embodiment of the present invention, in step S4, the outer layer drilling is used to drill through holes in the L1 to L12 layers to make each layer conductive and ensure product quality.

[0051] Reference Figure 3 In a non-limiting embodiment of the present invention, in step S4, the forming gong groove adopts a depth-controlled gong method to gong out the back-drilled holes 2 of the L7 to L12 layers, so that the back-drilled holes 2 of the L1 to L12 layers are conductive.

[0052] Reference Figure 3In a non-limiting embodiment of the present invention, in step S4, pattern electroplating is used to plate the locations where copper thickening is required to the copper thickness required by the customer using a secondary copper process. In this step, the back-drilled hole 2 positions corresponding to the L1 to L6 layers are covered with a dry film, and the dry film is stripped after the outer layer is etched.

[0053] Reference Figure 3 The method for improving the signal transmission integrity of PCB holes of the present invention forms a pressed board by pressing all core boards at once in the prior art. The method is divided into several parts, namely, first dividing the core board into L1 layer to L6 target layer, L7 to L10 layer, and L11 to L12 layer, and manufacturing them separately. In the manufacturing of L1 layer to L6 target layer, back-drilled holes 2 are drilled, and then the sub-boards 3 manufactured in the three steps are stacked and pressed together to form an overall pressed motherboard. In the manufacturing of the overall pressed motherboard, copper metallization holes are first used, and the electroplating layer is thickened by electro-flash plating. Then, in the subsequent flash etching process, the board is electro-flash plated to below the target layer and the flash plating layer is etched away. Compared with the traditional back drilling method, the back drilling can achieve zero stub, effectively ensuring the integrity of the signal transmission of the back drilling hole 2, and at the same time, it can also meet the production of the Ring 1 required by customers to meet the welding requirements.

[0054] Example 3

[0055] Reference Figure 4 A non-limiting embodiment of the present invention is a method for improving the signal transmission integrity of a PCB hole. The method described in this embodiment is performed using a 16-layer board as an example. Specifically, the method is to first separately manufacture layers L1 to L8, layers L9 to L14, and layers L15 to L16, and then combine the above-made layers L1 to L16. Specifically, the method includes the following steps:

[0056] S1: The production of L1 to L8 layers includes the front process → the first inner layer pattern → lamination → drilling → copper plate electroplating → the second inner layer pattern → the back process, wherein the first inner layer pattern is used to produce the inner layer pattern of L2 to L7 layers, and the second inner layer pattern is used to produce the inner layer pattern of L8 layer. The holes at the positions where the back drilling holes 2 of L1 to L8 layers need to be connected are drilled; in this step, the inner layer pattern is produced twice, once before lamination and once after lamination, that is, the L8 layer is separated and carried out after lamination, which can effectively ensure that the Ring 1 of the L8 layer, i.e. the target layer, is retained to meet customer welding requirements;

[0057] S2: The production of L9 to L14 layers includes cutting → inner layer patterning → grooving → post-processing. Among them, the grooving plate is used at the back drilling hole 2 position corresponding to the L1 to L8 layers to grooving the L9 to L14 core boards. This provides a tolerance value for the subsequent depth control groove cover after the motherboard is pressed together, preventing the reserved thickness from being insufficient and grooving to the target inner layer Ring 1 to ensure the integrity of the target layer Ring 1;

[0058] S3: Production of L15 to L16 layers, including cutting → inner layer patterning → post-processing; L15 to L16 layers only undergo inner layer patterning without lamination, effectively preventing problems such as uneven slot positions caused by grooves during subsequent motherboard pressing, thus ensuring quality for subsequent motherboard pressing;

[0059] S4: Production of L1 to L16 layers, front process → PP window opening → pressing → outer layer drilling → forming gong groove → copper plating → board electroplating → outer layer pattern → pattern electroplating → outer layer etching → film stripping → flash etching → back process, wherein copper plating and board electroplating are divided into two processes, copper plating is used to metallize the drilled holes in the previous step, and board electroplating performs flash plating on the metallized holes to thicken the electroplated layer. In this embodiment, board electroplating flash-plates a 2-3μm copper layer on the metallized holes; flash etching is arranged after outer layer etching and film stripping, and is used to etch away the flash-plated thickened copper on the back-drilled holes 2 of the L9 to L16 layers. In this embodiment, flash etching adopts a carrier etching method to etch away the flash-plated 2-3μm copper on the back-drilled holes 2 of the L9 to L16 layers, ensuring the integrity of the back-drilled holes 2 and other holes in the L1 to L8 layers, and meeting the retention of Ring 1. At this time, L9 to L16 layers are copper-free, achieving zero stub, ensuring the integrity of the signal transmission of the back-drilled holes 2, and improving product quality.

[0060] Reference Figure 4 In a non-limiting embodiment of the present invention, in step S1, the copper plate is electroplated to the copper thickness required by the customer on the via holes drilled in the drilling step, so that the copper thickness on the L1 to L8 layers, that is, the back-drilled hole 2 from L1 to the target layer, meets the requirements, ensuring product quality.

[0061] Reference Figure 4 In a non-limiting embodiment of the present invention, in step S4, the preceding process includes selecting a PP layer 4 using non-adhesive PP. PP windows are created at locations corresponding to the back-drilled holes 2 in layers L1 through L8. The use of non-adhesive PP ensures uniform and stable bonding between the PP and each sub-panel 3 during subsequent motherboard lamination. The PP windows provide a foundation and guarantee for subsequent outer layer drilling, thereby improving product manufacturing efficiency. In this embodiment, the PP window size is 2 mil larger than the customer's required design hole, ensuring that the hole size at the PP window after subsequent motherboard lamination meets the customer's requirements.

[0062] Reference Figure 4 In a non-limiting embodiment of the present invention, in step S4, the outer layer drilling is used to drill through holes in the L1 to L16 layers to make each layer conductive and ensure product quality.

[0063] Reference Figure 4 In a non-limiting embodiment of the present invention, in step S4, the forming gong groove adopts a depth-controlled gong method to gong out the back-drilled holes 2 of the L9 to L16 layers, so that the back-drilled holes 2 of the L1 to L16 layers are conductive.

[0064] Reference Figure 4 In a non-limiting embodiment of the present invention, in step S4, pattern electroplating is used to plate the locations where copper thickening is required to the copper thickness required by the customer using a secondary copper process. In this step, the back-drilled hole 2 positions corresponding to the L1 to L8 layers are covered with a dry film, and the dry film is stripped after the outer layer is etched.

[0065] Reference Figure 4 The method for improving the signal transmission integrity of PCB holes of the present invention forms a pressed board by pressing all core boards at once in the prior art, and first divides the core board into several parts, namely, L1 layer to L8 target layer, L9 to L14 layer, and L15 to L16 layer, and manufactures them separately. In the manufacture of L1 layer to L8 target layer, back-drilled holes 2 are drilled, and then the sub-boards 3 manufactured in the three steps are stacked and pressed together to form an overall pressed motherboard. In the manufacture of the overall pressed motherboard, copper metallization holes are first used, and the electroplating layer is thickened by electro-flash plating. Then, in the subsequent flash etching process, the board is electro-flash plated to below the target layer and the flash plating layer is etched away. Compared with the traditional back drilling method, the back drilling can achieve zero stub, effectively ensure the integrity of the signal transmission of the back drilling hole 2, and at the same time, meet the production of the Ring 1 required by customers to meet the welding requirements.

[0066] The above embodiments are merely specific embodiments of the present invention, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make various modifications and improvements without departing from the scope of the present invention, and such obvious alternatives are all within the scope of protection of the present invention.

Claims

1. A method for improving the signal transmission integrity of a PCB hole, characterized by: The method is to separately fabricate layers L1 to Lm, the intermediate layer, and layers L(n - 1) to Ln first, and then fabricate the above - completed layers L1 to Ln together. Both m and n are even numbers greater than 6, and m < n. Among them, In the fabrication of layers L1 to Ln, first, the copper deposition and panel electroplating are separately completed in two processes. Metalized holes are formed through copper deposition, and the electroplated layer is thickened by flash plating on the metalized holes through panel electroplating. After etching and stripping the film, the flash - plated copper on the intermediate layer and layers L(n - 1) to Ln corresponding to the back - drilled hole positions is etched away through flash etching, ensuring the integrity of the back - drilled holes and other holes in layers L1 to Lm, retaining the Ring of layer Lm, and making the back - drilled holes have no copper after layer Lm, achieving zero stub. The method includes the following steps: S1: Fabrication of layers L1 to Lm, including pre - process → first inner - layer pattern → lamination → drilling → copper deposition on panel → second inner - layer pattern → post - process. Among them, the first inner - layer pattern is used to fabricate the inner - layer patterns of other layers except Lm, the second inner - layer pattern is used to fabricate the inner - layer pattern of layer Lm, and drilling drills the holes at the positions where the back - drilled holes in layers L1 to Lm need to be connected. S2: Fabrication of layers L(m + 1) to L(n - 2), including material opening → inner - layer pattern → routing the board → post - process. Among them, when routing the board, at the positions corresponding to the back - drilled holes in layers L1 to Lm, the core boards of layers L(m + 1) to L(n - 2) are routed out. S3: Fabrication of layers L(n - 1) to Ln, including material opening → inner - layer pattern → post - process. S4: Fabrication of layers L1 to Ln, pre - process → PP window opening → lamination → outer - layer drilling → forming and routing grooves → copper deposition → panel electroplating → outer - layer pattern → pattern electroplating → outer - layer etching → stripping the film → flash etching → post - process. Among them, copper deposition and panel electroplating are divided into two processes. Copper deposition is used to metallize the drilled holes in the previous steps, and panel electroplating flash - plates and thickens the electroplated layer on the metallized holes. Flash etching is set after outer - layer etching and stripping the film, and is used to etch away the flash - plated and thickened copper on the back - drilled holes of layers L(m + 1) to Ln, ensuring the integrity of the back - drilled holes and other holes in layers L1 to Lm, meeting the requirement of retaining the Ring. At this time, layers L(m + 1) to Ln have no copper, achieving zero stub.

2. The method for improving the signal transmission integrity of a PCB hole according to claim 1, characterized in that: In step S1, copper deposition on panel electroplates the via holes drilled in the drilling step to the copper thickness required by the customer.

3. The method for improving PCB hole signal transmission integrity according to claim 1, characterized in that: In step S4, the pre - process includes the selection of the PP layer, and the PP layer uses non - bleeding PP; PP window opening performs PP window opening at the positions corresponding to the back - drilled holes in layers L1 to Lm.

4. The method for improving the signal transmission integrity of a PCB hole according to claim 3, characterized in that: The size of the PP window opening is 2 mil larger than the hole size designed by the customer's requirement.

5. The method for improving the signal transmission integrity of a PCB hole according to claim 1, characterized in that: In step S4, outer - layer drilling is used to drill the through - holes in layers L1 to Ln.

6. The method for improving signal transmission integrity of a PCB hole according to claim 1, characterized in that: In step S4, the forming and routing grooves adopt a controlled - depth routing method to route out the back - drilled holes in layers L(m + 1) to Ln, making the back - drilled holes in layers L1 to Ln conductive.

7. The method for improving signal transmission integrity of a PCB hole according to claim 1, characterized in that: In step S4, pattern electroplating is used to add copper to the positions that need to be thickened to the copper thickness required by the customer using the secondary copper process. In this step, the positions corresponding to the back - drilled holes in layers L1 to Lm are covered with dry film, and the dry film is stripped after outer - layer etching.

8. The method for improving the signal transmission integrity of a PCB hole according to any one of claims 1 to 7, characterized in that: In step S4, panel electroplating flash - plates a 2 - 3 μm copper layer on the metallized holes.

9. The method for improving the signal transmission integrity of a PCB hole according to any one of claims 1 to 7, characterized in that: In step S4, flash etching is performed using a carrier etching method to etch away the flash-plated copper of 2-3 μm on the back-drilled holes from the L(m+1) to Ln layers.

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