A multi-spi flash redundancy boot firmware method

Abstract

The application provides a multi-spi flash redundancy booting firmware method, and specifically as follows: an SPI bus on an MCU is connected in parallel with multiple SPI FLASHes, and then a GPIO pin of the MCU is used as CS0 and CS1 to be connected to CS pins of the SPI FLASHes respectively; an SPI FLASH to be measured is selected, and then an Xth data block in the SPI FLASH to be measured and a CRC check code of the Xth data block are read; a CRC check code corresponding to the read Xth data block is calculated, and is compared with the CRC check code stored in the SPI FLASH to be measured; if the CRC check code corresponding to the read Xth data block is equal to the CRC check code stored in the SPI FLASH to be measured, it is indicated that the check is passed, and the data is correct; if the CRC check code corresponding to the read Xth data block is not equal to the CRC check code stored in the SPI FLASH to be measured, it is indicated that the data is incorrect, and the next SPI FLASH needs to be continuously read, and the detection is sequentially performed. The application improves the reliability of the system, and is beneficial to long-time stable operation of the equipment.

Description

Technical Field

[0001] This invention relates to a method for redundant boot firmware using multiple SPI flashes, belonging to the field of embedded chip technology. Background Technology

[0002] Embedded chips typically contain a program stored in a BOOTROM (boot read only memory). When the chip is powered on, this BOOTROM program is run first. Then, the MCU reads the firmware program from the external storage medium SPI Flash (a flash memory chip with a serial communication interface) into memory and runs it. However, in some cases, the SPI Flash may be damaged, accidentally written to, or accidentally modified, resulting in inconsistent data reading with the expected data, firmware loading failure, and program inability to run normally. Summary of the Invention

[0003] The purpose of this invention is to provide a method for redundant boot firmware using multiple SPI flash chips, which can still boot and run the firmware program in the SPI flash chips normally even when multiple SPI flash chips are damaged or the data is mistakenly modified.

[0004] To achieve the above objectives, the present invention employs the following technical solution:

[0005] A method for redundant boot firmware using multi-SPI flash, characterized by comprising the following steps:

[0006] Step 1: Connect the SPI bus on the MCU to multiple SPI FLASH in parallel, and then use the MCU's GPIO pins as CS0 and CS1 to connect to the CS pin of the SPI FLASH respectively; divide the firmware into X sub-data blocks, and each sub-data block has its own CRC to verify whether the data in the sub-data block is correct, and then store the data blocks at the same offset position in the SPI FLASH simultaneously.

[0007] Step 2: Configure variable X = 0,

[0008] Step 3: Select the SPI FLASH to be measured, and then read the Xth data block and the CRC checksum of the Xth data block in the SPI FLASH to be measured;

[0009] Step 4: Calculate the CRC checksum corresponding to the Xth data block read and compare it with the CRC checksum stored in the SPI FLASH to be measured. If they are equal, the checksum is passed, the data is correct, and step 4 continues; if they are not equal, the data is incorrect, and the next SPI FLASH needs to be read.

[0010] Step 5: Increment the variable X to determine if X is the last data block, i.e., whether all parts of the firmware have been loaded. If it has been loaded, proceed to step 6. If it is not the last data block, proceed to step 3.

[0011] Step 6: Verify that the total CRC checksum is correct. If it is correct, let the MCU jump to the specified location where the SPI FLASH is stored in memory to complete the firmware loading.

[0012] Preferably, the specific method for selecting the SPI FLASH to be measured is as follows: the MCU controls the GPIO connected to the CS pin of the SPI FLASH to be measured to a low level, and controls the GPIO connected to the CS pin of the SPI FLASH not to be measured to a high level.

[0013] The advantages of this invention are: it eliminates the need for N sets of SPI buses, requiring only one set of SPI buses and N GPIO pins to achieve redundant backup of N SPI FLASH chips, significantly saving chip pin resources. The firmware in the SPI FLASH is divided into X sub-data (parts) for storage, each part having its own checksum (CRC). Even if all SPI FLASH chips are damaged, if the location of the damaged part is different for each chip, it can still boot and load data normally, greatly improving system reliability and facilitating long-term stable operation of the device. Attached Figure Description

[0014] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the embodiments of the invention to explain the invention and do not constitute a limitation thereof.

[0015] Figure 1 This is a schematic diagram of the connection structure between the MCU and two SPI FLASH chips.

[0016] Figure 2 This refers to the distributed placement method of firmware in SPI FLASH.

[0017] Figure 3 This is a schematic diagram of the process structure of the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] Taking a redundant backup of two SPI FLASH chips as an example, the hardware connection requires connecting the SPI bus on the MCU in parallel with SPIFLASH0 and SPIFLASH1 respectively. Then, use the GPIO pins of the two MCUs as CS0 and CS1, and connect them to the CS pin of the SPI FLASH respectively. Figure 1 As shown.

[0020] For the firmware storage format in SPI FLASH, such as Figure 2 As shown, the firmware needs to be split into X sub-data blocks (parts), and each sub-data block has its own CRC to verify whether the data in the sub-data block is correct. Then, these parts are stored at the same offset position in SPI FLASH 0 and SPI FLASH 1.

[0021] Once the above conditions are met, the BOOTROM program only needs to follow the steps below for booting. (Refer to...) Figure 3 Boot flowchart for 2 SPI Flash chips:

[0022] 1. Configure a variable X = 0 and execute step 2.

[0023] 2. The MCU controls the GPIO connected to CS0 to a low level and controls the GPIO connected to CS1 to a high level, thereby selecting SPI FLASH 0 for operation, then reading partX from SPI FLASH 0, and then executing step 3.

[0024] 3. Read crcX from SPI FLASH 0, and then execute step 4.

[0025] 4. Calculate the CRC checksum corresponding to the partX data read in step 2 and compare it with the crcX read in step 3. If they are equal, the checksum is passed and the data is correct. Continue to step 5. If they are not equal, the data is incorrect. We need to continue reading SPI FLASH 0, that is, continue to execute step 4.

[0026] 5. Increment the variable X and proceed to step 6.

[0027] 6. Determine if X is the last part, i.e., whether all parts of the firmware have been loaded. If it has been loaded, proceed to step 7. If it is not the last part, proceed to step 2 to continue execution.

[0028] 7. Verify that the total CRC checksum is correct. If it is correct, continue to step 8.

[0029] 8. Allow the MCU to jump to the specified location where the SPI FLASH is stored in memory, complete the firmware loading, and execute step 13.

[0030] 9. The MCU controls the GPIO connected to CS1 to be low and the GPIO connected to CS0 to be high, thereby selecting SPI FLASH 1 for operation, then reading partX from SPI FLASH 1, and then executing step 10.

[0031] 10. Read crcX from SPI FLASH 1, and then execute step 11.

[0032] 11. Calculate the CRC checksum corresponding to the partX data read in step 9, and compare it with the crcX read in step 10. If they are equal, it means that the check has passed, the data is correct, and continue to step 5; if they are not equal, it means that both SPI FLASH chips have failed to be read, and then proceed to step 12.

[0033] 12. Loading failed. The reason for the failure will be displayed. End.

[0034] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for redundant boot firmware using multiple SPI flashes, characterized in that, Includes the following steps: Step 1: Connect the SPI bus on the MCU to multiple SPI FLASH in parallel, and then use the GPIO pins of the MCU as CS0 and CS1 to connect to the CS pin of the SPI FLASH respectively; divide the firmware into X sub-data blocks, and each sub-data block has its own CRC to verify whether the data of the sub-data block is correct, and then store the data blocks at the same offset position in the SPI FLASH. Step 2: Configure variable X = 0, Step 3: Select the SPI FLASH to be measured, and then read the Xth data block and the CRC checksum of the Xth data block in the SPI FLASH to be measured; Step 4: Calculate the CRC checksum corresponding to the Xth data block read and compare it with the CRC checksum stored in the SPI FLASH to be measured. If they are equal, the checksum is passed and the data is correct. Proceed to Step 5. If they are not equal, the data is incorrect. Continue to read the Xth data block and the CRC checksum of the next SPI FLASH, and continue to Step 4. Step 5: Increment the variable X to determine if X is the last data block, i.e., whether all parts of the firmware have been loaded. If it has been loaded, proceed to step 6. If it is not the last data block, proceed to step 3. Step 6: Verify that the total CRC checksum is correct. If it is correct, let the MCU jump to the specified location where the SPI FLASH is stored in memory to complete the firmware loading. The specific method for selecting the SPI FLASH to be measured is as follows: the MCU controls the GPIO connected to the CS pin of the SPI FLASH to be measured to a low level, and controls the GPIO connected to the CS pin of the SPI FLASH not to be measured to a high level.

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