A Method for Single-Event Upset Directed Injection and a Recovery Method for SRAM-Type FPGAs

Abstract

The present invention belongs to the field of reliability analysis of electronic devices, and particularly relates to a single-event upset directed injection method and a recovery method for SRAM-based FPGAs, including: obtaining the hierarchical regions and script files of the engineering circuit; creating RTL-level user constraints and AREA GROUPs user constraints for the regions of interest in the hierarchical regions; generating a log file with the information of the regions of interest marked; performing placement and routing based on the above two user constraints; generating a basic bit file and a to-be-flipped bit file of the engineering circuit based on the log file and the placement and routing results; defining multiple groups of coordinates corresponding to the regions of interest in the FPGA in the floorplan view obtained after placement and routing, so as to obtain the basic bit rows corresponding to the regions of interest in the basic bit file, realizing single-event upset directed injection, and further proposing an anti-fuse-based FPGA and FLASH recovery method, with high method efficiency.

Description

Technical Field

[0001] The present invention belongs to the field of electronic equipment reliability analysis, and more specifically, relates to a SRAM type FPGA single particle upset directional injection method and a recovery method. Background Art

[0002] Since its birth, FPGA has gradually become a mainstream product in the integrated circuit application market with its high logic density, repeatable configuration and high performance. Its advantages of low power consumption and high density have made it widely used in aerospace electronic systems, especially in space missions involving small satellites. FPGA is often used to reduce the total cost of aerospace systems. However, due to the special structure of SRAM-type FPGA itself and the harsh space environment, it is extremely sensitive to the radiation effects in space, near space and aviation altitude environments. Continuous exposure to high-energy particle environments makes single-particle effects (SEE) very likely to occur. Single-particle effects will change the content in the FPGA storage unit, causing failures such as calculation structure failure and program execution sequence disorder, which will lead to FPGA function failure and even damage the device, seriously affecting the safety and stability of the system. Therefore, SRAM-type FPGAs used in aerospace electronic systems must be reinforced to improve the reliability of the system.

[0003] At present, there are three common methods used by domestic and foreign research institutions to evaluate the single-particle upset effect of FPGA: ground radiation testing, satellite-borne testing, and simulated fault injection. Ground radiation testing uses a particle accelerator to accelerate various particles and then hit the target device, so as to achieve the single-particle upset effect of the integrated device in the ground-simulated space radiation environment; satellite-borne testing refers to launching a carrier equipped with an SRAM-type FPGA device into space through an artificial satellite, and directly testing the single-particle upset effect sensitivity of the target device in a real space radiation environment; compared with these two methods, the fault injection technology has lower investment costs and stronger controllability, so it is also more widely used.

[0004] In recent years, the attention to analog fault injection technology and post-fault recovery technology at home and abroad has been increasing. Regarding the fault injection technology, Wang Zhimin et al. built a single event upset fault injection platform for Virtex-6 FPGA to achieve continuous and multiple single event upset fault injections into the user circuits of Virtex-6 FPGA, and then accurately evaluate the sensitivity of the user circuits to single event upsets when running on Virtex-6 FPGA; Lu Lingyun et al. grouped the resources in the circuit netlist by module and used the partial reconfiguration technology to randomly inject faults into the configuration frames related to the whole circuit and each group respectively. However, through these methods, only the configuration bits in the frame data can be randomly flipped, and the consequences of the flipped configuration frame data are unknown, and it is impossible to purposefully perform targeted fault injection on a certain function or a certain module in the user circuit. Regarding the recovery technology, the research solutions can be divided into two types. One is the in-chip read-back error correction method, that is, reading back the configuration frame data through the in-chip ICAP interface and performing error correction after encoding. However, this method has low reliability. If the in-chip encoding and error correction logic is interfered and an error occurs, the function cannot be completed. The other is the off-chip timing refresh method, that is, using off-chip highly reliable logic devices to read the configuration frame from the external non-volatile memory and refreshing the functional FPGA regularly. However, this solution reads the external memory whether or not a flip occurs, increasing the dynamic power consumption and being limited by the service life of the external memory. Summary of the Invention

[0005] In view of the defects and improvement requirements of the prior art, the present invention provides a method for single event upset targeted injection and a recovery method for SRAM-based FPGA, aiming to achieve single event upset targeted fault injection for a specified module and improve the effective fault injection rate of the system.

[0006] To achieve the above object, according to one aspect of the present invention, a method for single event upset targeted injection for SRAM-based FPGA is provided, including:

[0007] S1. Complete the engineering circuit design to obtain the hierarchical regions and script files of the engineering circuit;

[0008] S2. Create RTL-level user constraints for the regions of interest in the hierarchical regions to partition the RTL during the placement and routing process to separate the regions of interest from other regions; create user constraints for AREA GROUPs to map the regions of interest into one or more AREA GROUPs and isolate them from other hierarchical regions during the placement and routing process; modify the script file and run it to generate a log file marked with the information of the regions of interest;

[0009] S3. Perform placement and routing based on the user constraints at the RTL level and the user constraints of the AREA GROUPs; generate the basic bit EBD file of the engineering circuit and the bit file to be overturned for the FPGA based on the log file and the results of the placement and routing.

[0010] S4. Define multiple groups of coordinates in the floorplan view obtained after the placement and routing, representing the specific positions of the placement blocks surrounded by the resources corresponding to the area of interest in the FPGA; based on the linear slope-intercept equation relationship existing between the FPGA area and the EBD file lines, use the multiple groups of coordinates to obtain the EBD lines corresponding to the area of interest in the basic bit EBD file.

[0011] S5. Overturn the positions corresponding to the EBD lines in the bit file to be overturned to achieve single-event upset directed injection for SRAM-based FPGAs.

[0012] Furthermore, the multiple groups of coordinates are specifically two groups of coordinates.

[0013] The present invention also provides a recovery method for a SRAM-based FPGA after single-event upset, including:

[0014] S1. Read back the configuration frame data of the FPGA to be recovered through the ICAP port, and the configuration frame data is the bit file overturned in a single-event upset directed injection method for a SRAM-based FPGA as described above; parse the configuration frame address in the bit file to obtain the configuration frame type.

[0015] S2. Read out the original configuration frame data of the bit file stored in the external Flash of the antifuse-based FPGA by the antifuse-based FPGA before being overturned, perform RS coding on this data, and store the obtained error correction code in the on-chip memory of the antifuse-based FPGA.

[0016] S3. Transmit the read-back configuration frame data to the antifuse-based FPGA, and through the antifuse-based FPGA, compare and correct the configuration frame data with the error correction code in units of frames. According to the comparison and correction results, if the error correction is successful, the recovery is completed; if not, combine the configuration frame type, and reconfigure or rewrite the read-back configuration frame data to complete the recovery.

[0017] Furthermore, the specific implementation manner of S2 is:

[0018] Read the original configuration frame data before the bit file was corrupted from the external Flash of the antifuse FPGA through the Flash read control logic of the antifuse FPGA, and perform RS encoding on this data through the RS encoding module of the antifuse FPGA, and store the obtained check code in the on-chip BRAM storage area of the antifuse FPGA.

[0019] Further, in step S3, the implementation method of the comparison and error correction is as follows:

[0020] Decode the error correction code to obtain multiple groups of parity check symbols for error correction of the read-back configuration frame data in units of frames;

[0021] Perform RS encoding on the error-corrected configuration frame data to obtain a new error correction code, compare the new error correction code with the error correction code stored in the on-chip of the antifuse FPGA to obtain the comparison and error correction result.

[0022] Further, the usage method of the comparison and error correction result is specifically as follows:

[0023] Through the antifuse FPGA, according to the comparison and error correction result and the configuration frame type, output flag bits flag1, flag2[1:0] that mark the single-event upset type of each frame; where, if there is no single-event upset in the read-back configuration frame data, use flag1 = 0 to indicate no single-event upset, otherwise flag1 = 1 to indicate a single-event upset; if the current frame type is a configurable logic resource type and a single-event upset occurs, use flag2 = 00 to indicate a single-event upset in other logic resources other than the configurable logic resources; if the frame type of the current frame is a configurable logic resource type, a single-event upset occurs in this frame and RS error correction is successful, use flag2 = 01 to indicate a single-event upset that can be corrected by RS; if the frame type of the current frame is a configurable logic resource type, a single-event upset occurs in this frame and RS error correction is unsuccessful, use flag2 = 10 to indicate a single-event upset with an error bit greater than the RS error correction ability;

[0024] According to the status of flag1 and flag2, control the configuration refresh process in units of frames to achieve reconfiguration or rewriting of the read-back configuration frame data and complete the recovery.

[0025] Further, the configuration refresh process is specifically as follows:

[0026] If flag1 = 0, no action is taken; if flag1 = 1 and flag2 = 00, the configuration storage area of the FPGA to be restored is erased first, and then reconfiguration is performed through the Select Map port to start the reconfiguration process; if flag1 = 1 and flag2 = 01, the corrected configuration frame data is written back to the configuration storage area of the FPGA to be restored through the Select Map port to update the bit file; if flag1 = 1 and flag2 = 10, the original configuration frame data is read from the Flash and written back to the configuration storage area of the FPGA to be restored through the Select Map port.

[0027] The present invention also provides a computer-readable storage medium, which includes a stored computer program. When the computer program is run by a processor, it controls the device where the storage medium is located to execute a single-event upset directed injection method for an SRAM-based FPGA and / or a recovery method as described above.

[0028] Generally speaking, through the above technical solutions conceived by the present invention, the following beneficial effects can be achieved:

[0029] (1) In view of the problem that the number of configuration frame data of SRAM-based FPGA devices is too large, through in-depth research on the basic bit technology, the configuration bits that account for the vast majority and have nothing to do with the user circuit design function in the configuration frame data are removed, and a subset of configuration bits that only contains the resources used by specific application programs programmed into the FPGA is separated, that is, the EBD file of the basic bits, which greatly reduces the number of configuration frames to be processed, extracts the configuration frames corresponding to the configuration RAM resources, and improves the directivity of single-event upset injection of SRAM-based FPGAs.

[0030] (2) In view of the problem that it is difficult to implement single-event upset fault injection at a specified part, since the obtained EBD file only contains basic bits and is composed of a simple ASCII character set of "0" and "1", in order to further translate it into a configuration frame address recognizable by the fault injector, an automatic configuration memory fault injection method is proposed. A rectangular area is artificially defined in the floorplan view of the FPGA series FPGA, and after calculating the vertex coordinates of this area and the EBD file through an equation, the fault injection instruction of the fault injector SEM IP is obtained, and the single-event upset fault injection of a specific module of the FPGA user circuit is completed through this instruction, which is of great significance for improving the fault injection rate of the system.

[0031] (3) The recovery method proposed by the present invention uses an external antifuse FPGA for configuration, which has high reliability. In addition, the original configuration frame data pre-stored in the external FLASH is read by the antifuse FPGA and RS coding is performed. By comparing the RS coding with the bit file in the FPGA to be recovered read back, error correction and configuration frame data recovery are carried out, and the recovery efficiency is high.

[0032] (4) The present invention proposes to read back frame data for error correction verification, classify the single-event upset types, and perform targeted processing on different types, which improves the processing efficiency against upsets. In addition, it also greatly reduces the number of times of reading the configuration frame from the external FLASH and increases its service life.

[0033] (5) Both the single-event upset directed injection method and the recovery method of the present invention have relatively high efficiency and can be used as methods for detecting each other's performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a flowchart of a single-event upset directed injection method for an SRAM-based FPGA provided by an embodiment of the present invention;

[0035] Figure 2 It is a schematic diagram of the basic bit file design process provided by an embodiment of the present invention;

[0036] Figure 3 It is a schematic diagram of the constraints used in the construction of the basic bit file provided by an embodiment of the present invention;

[0037] Figure 4 It is a schematic diagram of the directed fault injection process using SEM IP provided by an embodiment of the present invention;

[0038] Figure 5 It is a schematic diagram of the formula for the EBD file line to the fault injection address provided by an embodiment of the present invention;

[0039] Figure 6 It is a schematic diagram of the hardware for fault injection provided by an embodiment of the present invention;

[0040] Figure 7 It is a schematic diagram of the frame structure analysis process based on the ICAP read-back technology provided by an embodiment of the present invention;

[0041] Figure 8 It is a schematic diagram of the ICAP interface control circuit provided by an embodiment of the present invention;

[0042] Figure 9 It is a schematic diagram of the state transition of the ICAP read / write control module provided by an embodiment of the present invention;

[0043] Figure 10 It is a schematic diagram of the ICAP interface timing relationship provided by an embodiment of the present invention;

[0044] Figure 11 Schematic diagram of the ICAP operation bit exchange operation example provided by the embodiment of the present invention;

[0045] Figure 12 Schematic diagram of the frame address acquisition circuit provided by the embodiment of the present invention;

[0046] Figure 13 Schematic diagram of the host computer receiving valid address data provided by the embodiment of the present invention;

[0047] Figure 14 Flash read timing diagram provided by the embodiment of the present invention;

[0048] Figure 15 RS coding circuit diagram provided by the embodiment of the present invention;

[0049] Figure 16 Configuration refresh flow chart provided by the embodiment of the present invention. Detailed implementation manners

[0050] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0051] First, the English abbreviations appearing below are explained: ICAP is the abbreviation of Internal Configuration Access Port, EBD is the abbreviation of Essential Bit Data, SEM IP is the abbreviation of Soft Error Mitigation, FAR is the abbreviation of Frame Address Register, DUT is the abbreviation of Design Under Test, CMD ROM is the abbreviation of Command Register ROM, and RTL is the abbreviation of Register Transfer Level.

[0052] Embodiment 1

[0053] A method for single-event upset directed injection of SRAM-based FPGAs, as Figure 1 shown, includes:

[0054] S1. Use an EDA design tool to complete the engineering circuit design and obtain the hierarchical area and script file of the engineering circuit;

[0055] S2. Create RTL-level user constraints for the region of interest in the hierarchical region, which are used to partition the RTL during the placement and routing process to separate the region of interest from other regions; create user constraints for AREA GROUPs, which are used to map the region of interest into one or more AREA GROUPs and isolate it from other hierarchical regions during the placement and routing process; modify the script file and run it to generate a log file with the region of interest information marked.

[0056] S3. Use the PlanAhead tool for placement and routing based on the RTL-level user constraints and the user constraints for AREA GROUPs; use the bit file generation tool to generate the basic bit EBD file for the engineering circuit and the bit file to be flipped for the FPGA based on the log file and the results of the placement and routing.

[0057] S4. Define multiple sets of coordinates in the floorplan view obtained after placement and routing, which represent the specific positions of the placement blocks surrounded by the resources corresponding to the region of interest in the FPGA; based on the linear slope-intercept equation relationship between the FPGA region and the EBD file lines, use the multiple sets of coordinates to obtain the EBD lines corresponding to the region of interest in the basic bit EBD file.

[0058] S5. Flip the positions corresponding to the EBD lines in the bit file to be flipped to achieve single-event upset directed injection for SRAM-based FPGAs.

[0059] Regarding the acquisition of the basic bit EBD file: The basic bit EBD file (basic bits refer to the bit positions directly related to the function) separates a subset of the configuration bits that only contain the resources used by the specific application programmed into the FPGA for a specific module of interest in the project, that is, the basic bit EBD file. The process of creating and using the priority basic bit technology is as Figure 2 shown.

[0060] Specifically, it includes the following sub-steps:

[0061] (1) Identify the region of interest and conduct comprehensive design: The user identifies a region of interest that plays a key role in the circuit design. By adding RTL-level constraints for the region of interest in the RTL-level design, the RTL (Register Transfer Level) is partitioned. The constraint usage statements are as Figure 3 shown in ① below;

[0062] Define the user constraint file for AREA GROUPs: Further place the identified region of interest into one or more AREA GROUPs to isolate the region of interest from other regions. The constraint usage statements are asFigure 3 as shown in ②;

[0063] Log file generation: After completing the engineering design, the script file essential.scr is obtained. The script is modified by running instructions to generate a log file containing components and netlists of the region of interest. The script file is run using statements such as Figure 3 as shown in ③;

[0064] (4) EBD file generation: After obtaining the log file containing components and netlists in the region of interest, BitGen is used to receive the created log file and generate an EBD file, which contains only the bits identified as priority basic bits. The script uses statements such as Figure 3 as shown in ④.

[0065] Regarding obtaining the fault injection address from the EBD file: The configuration memory basic bits (i.e., the EBD file) extracted from the region of interest in the SRAM-based FPGA are further processed and converted into the injection address of the Xilinx SEM IP controller for automatic configuration memory fault injection. The process of implementing single-event upset directed fault injection using the automatic configuration memory fault injection method is as Figure 4 shown.

[0066] Specifically, it includes the following sub-steps:

[0067] (1) Manually select the region of interest: According to the above-completed design project, a placement block Pblock that encloses the relevant resources of the module of interest is drawn in the floorplan view of the FPGA generated by the PlanAhead tool. By defining two sets of coordinates in the floorplan view, the specific position of the Pblock in the FPGA is drawn, and the selected coordinates are recorded. The Pblock is a manually laid-out rectangular area designed to impose an area constraint on the logic units in a specific area of the FPGA and deploy the corresponding logic units to the physical area of the FPGA after differentiation. The size of the rectangular area of the Pblock limits the number of FPGA logic resources it contains; the position of the rectangular area of the Pblock specifies its actual position in the physical area of the FPGA; the types of FPGA logic resources used in the rectangular area of the Pblock limit the types of logic resources it contains. By defining two sets of coordinates in the floorplan view, the specific position of the Pblock in the FPGA is drawn, and the selected coordinates are recorded as the input parameters for the subsequent automatic configuration memory fault injection method.

[0068] (2) Obtain EBD file lines: Using the coordinates recorded by the Pblock, based on the linear slope-intercept equation existing between the FPGA region and the EBD file lines, the coordinates of the Pblock are used to obtain its EBD lines;

[0069] (3) Fault injection address acquisition: The format requirement of the fault injection address is as Figure 13 shown. According to the line number of the basic bit in the EBD file, obtain the fault injection command, send it to the SEM IP to execute the fault injection, and the formula from the EBD file line to the fault injection address is as Figure 5 shown. Use the line number of the basic bit in the EBD file to calculate the 17-bit linear frame address, 7-bit word address, and 5-bit bit address.

[0070] The hardware schematic of the EBD file and fault injection is as Figure 6 shown. In this embodiment, it is considered that not all single-event upset effects occurring on configuration bits will cause a change in the logic function of the designed circuit. Only a subset of these bits that configure the resources used by a specific application programmed into the FPGA are relevant, and these bits are called basic bits. By finding the basic bit file in the module of interest and finding the mapping relationship with the bit file, targeted single-event fault injection can be performed, and targeted fault injection can be achieved. Based on this, this embodiment proposes a technical solution for parsing the basic bit technology and separating the frame data in the region of interest, and further proposes an automatic configuration memory fault injection method, a method of translating it into a frame address recognizable by the fault injector.

[0071] Embodiment 2

[0072] A recovery method for a SRAM-based FPGA after single-event upset as described in Embodiment 1, including:

[0073] S1. Read back the configuration frame data of the FPGA to be recovered through the ICAP port. The configuration frame data is the bit file overturned in a single-event upset directional injection method for a SRAM-based FPGA as described in Embodiment 1; parse the configuration frame address in the bit file to obtain the configuration frame type;

[0074] Specifically, the FPGA ICAP port can be operated in a specified packet format to read back the configuration frame data, and the read configuration frame data is output, as Figure 7 shown.

[0075] Based on the ICAP interface control circuit as Figure 8As shown, after the read command sequence word undergoes bit swapping through the configuration logic, it is stored in the CMD ROM in the specified order; the CS ROM and the READ ROM are respectively used to store the corresponding chip select signal and read control signal; the Data Counter records the number of configuration data words read from the configuration memory. Each time a data read operation is completed, a total of 202 words of data need to be received, and only the last 101 words contain valid data. The Counter_r and Counter_w counters are respectively used to record the number of command sequence words that have been written and read. The ICAP state machine controls the values of these command sequences and gives the ROM addresses during read and write operations. The base addresses of the command sequences read and written in the ROM are generated after decoding the start signal, and the actual addresses of the corresponding operation command sequences in the ROM are obtained after adding the values counted above.

[0076] The schematic diagram of the state transition of the ICAP read / write control module is as Figure 9 shown. When in the initial state, it is judged whether the start_icap signal is valid, and at the same time the controller samples the mode signal to select whether to perform a read or write operation. When it is judged as a read operation, it jumps to the READ_CMD state to send the read configuration data command sequence. After the command sequence is received and correctly recognized, it jumps to the READ_DATA state to wait for the received read data. After completion, it returns to the previous state to resend the desynchronization command sequence, and finally returns to the initial state. When it is judged as a write operation, it jumps to the WRITE_CMD state and sends the write operation command sequence, and then enters the WRITE_DATA state to write the configuration data into the configuration memory. After completion, it jumps back to the previous state to continue sending commands such as desynchronization, and finally returns to the initial state to complete an operation of writing to the configuration memory.

[0077] That is, the steps for reading back the configuration frame data of the FPGA to be restored include the following sub-steps:

[0078] (1) Sending the ICAP port read packet: Using the ICAP read / write control module, the bitstream command sequence is sent to the configuration control logic according to the timing requirements of the ICAP interface to realize the sending of the read command for the frame data in the configuration memory. The read / write timing of the ICAP interface is as Figure 10 shown. For the method of reading back using the ICAP interface, it is necessary to ensure that the current state is write. After the FPGA receives the read start command sequence and frame address data sent by the ICAP interface, it then switches the ICAP to the read operation; for the method of outputting the ICAP bitstream command sequence, before writing the command packet to the configuration memory area through the ICAP interface, it is necessary to perform a bit swapping operation on the command packet, as Figure 11As shown, the process of bit swapping for two bytes of data (0xABCD) is shown. After the swap, the data bits are (0xD5B3). The specific bit swapping rule is as follows: The most significant bit (MSB) and the least significant bit (LSB) of each byte are swapped, the second most significant bit and the second least significant bit are swapped, and so on.

[0079] (2) Configure frame data error detection output: The read configuration frame data is processed by the internally instantiated primitive FRAME_ECC module to perform error detection and correction on the configuration RAM frame data and then output.

[0080] (3) Read frame data reception: After the command sequence is received and correctly recognized, wait to receive the read frame data, and use a counter to record the number of words of configuration data read from the configuration memory.

[0081] (4) All data frame readout judgment: Determine whether to read back all data according to the counter status value. When all data is read back, the process ends.

[0082] In addition, the logic circuit of FRAME_ECC embedded in the FPGA can be used to output the frame address in the FAR register while reading back the configuration data for frame address parsing. The configuration frame address parsing structure diagram is as Figure 12 shown.

[0083] Specifically, frame address parsing includes the following sub-steps:

[0084] (1) Obtain the frame address using the primitive: Instantiate the primitive of FRAME_ECC, and output the physical address of the current configuration frame in the last cycle of reading back each frame of configuration data.

[0085] (2) Transmit the frame address to the host computer: Use the UART_32 module to divide the received 32-bit frame address into 4 times and transmit it to the host computer through the universal asynchronous transceiver. The host computer receives partial data.

[0086] (3) The host computer performs frame address parsing: After the host computer analyzes and arranges the received valid address data according to the frame structure, it obtains the specific frame address distribution of the FPGA series FPGA. The specific frame address distribution of the FPGA series FPGA is as Figure 13As shown. It is mainly composed of two parts, Top and Bottom. The Top part contains 4 rows, and the Bottom part contains 3 rows. Each row has 103 columns, and the number of configuration frames contained in each column is not fixed. The number of configuration frames varies according to the type of logical resources. In order to realize the fault injection function for the frame address in the configuration RAM, it is only necessary to obtain the frame data in which Block Type is 000, of which the first 96 columns are composed of CLB columns, CLK columns, IOB columns and BRAM interconnection columns, and the rest are BRAM content columns. The method of the present invention only studies the frame data set related to the configuration RAM storage unit. Combined with the valid frame data set obtained in the experiment, the configuration RAM resource contains a total of 21762 frames.

[0087] S2, reading the original configuration frame data of the above bit file before being overturned from the external Flash of the anti-fuse FPGA through the anti-fuse FPGA, performing RS encoding on the data, and storing the error correction code obtained by encoding in the chip of the anti-fuse FPGA;

[0088] Specifically, the steps may include:

[0089] (1) Flash control read logic: Figure 14 As shown, the Flash interface enable signal OE# is set to 0, the Flash write enable signal WE# is set to 1, the read address Addresses is calculated and sent out, and the data Output is read out after a certain time delay as valid configuration frame data. The counter counts to control the change of the read address Addresses until all the current configuration frame data is read.

[0090] (2) RS encoding: RS encoding is performed on the configuration frame data read from the FLASH in units of frames; that is, an error correction code is added after each frame of configuration frame data; the RS code encoding process is as follows:

[0091] Using the primitive polynomial, P(x) = x 8 +x 7 +x 2 +x+1;

[0092] Let m be the primitive element in GF(q), the RS code that can correct 2t errors, and its generating polynomial g(x) has α, α2, … αt as all its roots. The generating polynomial of the RS code is:

[0093] g(x) = (x-α)(x-α 2 )...(x-α 2t )=g0+g1x+g2x 2 +...+g 2t-1 x 2t-1 +x 2t :

[0094] Among them, αi ∈ GF(2m).

[0095] After the coding method is determined, generate start is 112. The coefficients g0, g1, …, g2t of the generating polynomial g(x) are all known constants.

[0096] Let the information vector to be encoded be (mk-1, mk-2, …, m2, m1, m0), and the information polynomial formed is:

[0097] m(x) = m0 + m1x + m2x 2 +... + m k-1 x k-1 , where k = n - 2t;

[0098] The check vector is (rn-k-1, rn-k-2, …, r2, r1, r0), and the check polynomial formed is:

[0099] r(x) = r n-k-1 x n-k-1 +... + r1x + r0;

[0100] In the form of a systematic code, the 2t parity check symbols are exactly the coefficients of the remainder obtained by dividing the information polynomial x2tm(x) by the generating polynomial. According to the form of systematic coding, the coding expression is written as:

[0101] c(x) = x 2t m(x) mod g(x)

[0102] From the above analysis, the encoding of the systematic RS code is achieved in three steps:

[0103] 1) First, multiply the information polynomial m(x) by x2t to obtain x2tm(x);

[0104] 2) Divide x2tm(x) by the generating polynomial g(x) to obtain the remainder r(x), and r(x) is the required check bit;

[0105] 3) The encoded codeword polynomial is obtained from x2tm(x) and r(x).

[0106] The flowchart of the hardware implementation of RS encoding is as Figure 15 shown.

[0107] (3) Write the error correction code after RS encoding for each frame into the BRAM for storage.

[0108] S3. Transmit the above read-back configuration frame data to the antifuse FPGA. Through the antifuse FPGA, compare and correct the read-back configuration frame data with the error correction code in units of frames. According to the comparison and error correction results, if the error correction is successful, the restoration is completed; if not, combine the configuration frame type to reconfigure or rewrite the read-back configuration frame data to complete the restoration.

[0109] In recent years, many related studies have been done on the restoration scheme after single-event upset of FPGA at home and abroad. The research schemes can be divided into two types. One is the in-chip read-back error correction method, that is, read the configuration frame data through the in-chip ICAP interface, and perform error correction after encoding. However, this method has low reliability. If the in-chip encoding and error correction logic is interfered and makes an error, the function cannot be completed. The other is the off-chip timing refresh method, that is, use off-chip highly reliable logic devices to read the configuration frame from the external non-volatile memory and refresh the functional FPGA regularly. But this scheme reads the external memory whether or not an upset occurs, increasing the dynamic power consumption and being limited by the service life of the external memory.

[0110] The restoration method proposed in this embodiment uses an external antifuse FPGA for configuration, with high reliability.

[0111] Preferably, the specific implementation manner of the above S2 is:

[0112] Read the original configuration frame data stored in the external Flash of the antifuse FPGA before the bit file is overturned through the Flash read control logic of the antifuse FPGA, and perform RS encoding on this data through the RS encoding module of the antifuse FPGA, and store the encoded check code in the on-chip BRAM storage area of the antifuse FPGA.

[0113] Preferably, in S3, the implementation manner of the comparison and error correction is:

[0114] Decode the error correction code to obtain multiple groups of parity check symbols for error correction of the read-back configuration frame data in units of frames;

[0115] Perform RS encoding on the error-corrected configuration frame data to obtain a new error correction code, and compare the new error correction code with the error correction code stored in the on-chip of the antifuse FPGA to obtain the comparison and error correction result.

[0116] Preferably, the usage manner of the comparison and error correction result is specifically:

[0117] According to the error correction result and the configured frame type read back, output flag bits flag1 and flag2[1:0] to mark the single event upset type of the current frame. (1) According to the parity check results of multiple groups, if there is no single event upset in the read-back configured frame, use flag1 = 0 to indicate no single event upset, otherwise use flag1 = 1 to indicate that a single event upset has occurred; (2) According to the current configured frame type, if the frame type is not equal to 000, i.e., the logical resource type, and a single event upset occurs, use flag2 = 00 to indicate a single event upset of other logical resources; (3) If the frame type is equal to 000, a single event upset occurs, and the RS error correction is successful, use flag2 = 01 to indicate a single event upset that can be corrected by RS; (4) If the frame type is equal to 000, a single event upset occurs, and the RS error correction is unsuccessful, use flag2 = 10 to indicate a single event upset with the number of error bits greater than the RS error correction ability.

[0118] According to the status of flag1 and flag2, control the configuration refresh process in units of frames, so as to reconfigure or rewrite the read-back configured frame data and complete the recovery.

[0119] Preferably, the configuration refresh process is specifically as follows:

[0120] Adopt the control and judgment module in the anti-fuse type FPGA to control the configuration refresh process in units of frames according to the status of flag1 and flag2; (1) flag1 = 0, no action; (2) flag1 = 1, flag2 = 00, start the reconfiguration process by first erasing the configuration storage area of the FPGA to be tested and then reconfiguring through the Select Map port; (3) flag1 = 1, flag2 = 01, write the error-corrected configured frame data back to the configuration storage area of the FPGA to be tested through the Select Map port to update the bit file; (4) flag1 = 1, flag2 = 10, read the configured frame data from the Flash and write it back to the configuration storage area of the FPGA to be tested through the Select Map port. The flow chart is as Figure 16 shown.

[0121] In this embodiment, the ICAP interface is used to read back the frame data for error correction verification, classify the single event upset types, and perform targeted processing on different types, improving the recovery processing efficiency against upsets. In addition, it also greatly reduces the number of times of reading the configured frame from the external FLASH and increases its service life.

[0122] Embodiment 3

[0123] A computer-readable storage medium, the computer-readable storage medium including a stored computer program, wherein when the computer program is run by a processor, it controls the device where the storage medium is located to execute an SRAM-based FPGA single-event upset directed injection method as described above and / or a recovery method as described above.

[0124] Generally speaking, the method of the present invention includes: (1) controlling the FPGA ICAP (Internal Configuration Access Port) to read back the configuration frame data to obtain all frame address sets; (2) parsing the configuration frame addresses to obtain the FPGA series frame address distribution; (3) separating a subset of configuration bits that only contain the resources used by a specific application configured into the FPGA, that is, the EBD (Essential Bit Data) file of the basic bits; (4) using the Xilinx SEM IP (Soft Error Mitigation) controller to perform automatic configuration memory fault injection according to the basic bit file; (5) recovering the configuration frame data after fault injection according to the configuration frame type. The method of the present invention aims at the problem that the frame structure in the configuration memory of FPGA series FPGA devices is unknown, obtains all frame address data through the internal configuration interface ICAP, and further parses according to different frame address types to obtain the configuration frames corresponding to the configuration RAM resources; the present invention performs automatic configuration memory fault injection based on the basic bit technology, can complete fault injection for specified functional modules, and compared with the method of random fault injection, the effective fault injection rate is greatly improved. In addition, an anti-fuse type FPGA and an external Flash are used to improve the efficiency and reliability of the configuration frame data recovery, and at the same time avoid the problem of short hardware life caused by traditional recovery methods.

[0125] It is easy for those skilled in the art to understand that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for single-event upset directed injection in SRAM-based FPGAs, characterized in that, Including: S1. Complete the engineering circuit design to obtain the hierarchical regions and script files of the engineering circuit; S2. Create RTL-level user constraints for the regions of interest in the hierarchical regions to partition the RTL during the placement and routing process to separate the regions of interest from other regions; create user constraints for AREA GROUPs to map the regions of interest into one or more AREA GROUPs and isolate them from other hierarchical regions during the placement and routing process; modify the script file and run it to generate a log file with the regions of interest information marked; S3. Perform placement and routing based on the RTL-level user constraints and the AREA GROUPs user constraints; Generate the basic bit EBD file of the engineering circuit and the bit file to be flipped for the FPGA based on the log file and the result of the placement and routing; S4. Define multiple sets of coordinates in the floorplan view obtained after the placement and routing to represent the specific positions of the placement blocks surrounded by the resources corresponding to the regions of interest in the FPGA; based on the linear slope-intercept equation relationship between the FPGA regions and the EBD file rows, use the multiple sets of coordinates to obtain the EBD rows corresponding to the regions of interest in the basic bit EBD file; S5. Flip the positions corresponding to the EBD rows in the bit file to be flipped to achieve single-event upset directed injection for SRAM-based FPGAs.

2. The single-event upset directed injection method for SRAM-based FPGA according to claim 1, wherein The multiple sets of coordinates are specifically two sets of coordinates.

3. A recovery method after single event upset of an SRAM-based FPGA as described in claim 1 or 2, characterized in that, Including: S1. Read back the configuration frame data of the FPGA to be restored through the ICAP port, and the configuration frame data is the bit file flipped in a single-event upset directed injection method for SRAM-based FPGAs as described in claim 1 or 2; parse the configuration frame address in the bit file to obtain the configuration frame type; S2. Read out the original configuration frame data before flipping of the stored bit file from the external Flash of the antifuse-based FPGA through the antifuse-based FPGA, perform RS coding on this data, and store the obtained error correction code in the on-chip BRAM of the antifuse-based FPGA; S3. Transmit the read-back configuration frame data to the antifuse-based FPGA, and through the antifuse-based FPGA, compare and correct the configuration frame data with the error correction code in units of frames. According to the comparison and correction result, if the error correction is successful, the restoration is completed; if not, reconfigure or rewrite the read-back configuration frame data in combination with the configuration frame type to complete the restoration.

4. The recovery method according to claim 3, wherein The specific implementation method of S2 is: Read out the original configuration frame data before flipping of the stored bit file from the external Flash of the antifuse-based FPGA through the Flash read control logic of the antifuse-based FPGA, and perform RS coding on this data through the RS coding module of the antifuse-based FPGA, and store the obtained check code in the on-chip BRAM storage area of the antifuse-based FPGA.

5. The recovery method according to claim 3, characterized in that In S3, the implementation method of the comparison and error correction is: Decode the error correction code to obtain multiple groups of parity check symbols for error correction of the read-back configuration frame data on a frame-by-frame basis; Perform RS encoding on the error-corrected configuration frame data to obtain a new error correction code, and compare the new error correction code with the error correction code stored in the on-chip of the antifuse FPGA to obtain a comparison error correction result.

6. The recovery method according to claim 5, wherein The specific usage method of the comparison error correction result is as follows: Through the antifuse FPGA, according to the comparison error correction result and the configuration frame type, output flag bits flag1 and flag2[1:0] that mark the single-event upset type of each frame; among them, if there is no single-event upset in the read-back configuration frame data, flag1 = 0 indicates no single-event upset, otherwise flag1 = 1 indicates a single-event upset; if the current frame type is a configurable logic resource type and a single-event upset occurs, then flag2 = 00 indicates that a single-event upset occurs in other logic resources other than the configurable logic resources; if the frame type of the current frame is a configurable logic resource type, a single-event upset occurs in this frame and the RS error correction is successful, then flag2 = 01 indicates a single-event upset that can be corrected by RS; if the frame type of the current frame is a configurable logic resource type, a single-event upset occurs in this frame and the RS error correction is unsuccessful, then flag2 = 10 indicates a single-event upset with an error bit greater than the RS error correction ability; According to the states of flag1 and flag2, control the configuration refresh process on a frame-by-frame basis to realize reconfiguration or rewriting of the read-back configuration frame data and complete the restoration.

7. The restoration method according to claim 6, characterized in that, The specific configuration refresh process is as follows: If flag1 = 0, do nothing; if flag1 = 1 and flag2 = 00, then first erase the configuration storage area of the FPGA to be restored, and then start the reconfiguration process by reconfiguring through the Select Map port; If flag1 = 1 and flag2 = 01, write the error-corrected configuration frame data back to the configuration storage area of the FPGA to be restored through the Select Map port to update the bit file; if flag1 = 1 and flag2 = 10, then read the original configuration frame data from the Flash and write it back to the configuration storage area of the FPGA to be restored through the Select Map port.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a stored computer program, wherein when the computer program is run by a processor, it controls the device where the storage medium is located to execute a single-event upset directed injection method for an SRAM-type FPGA as described in claim 1 or 2 and / or a restoration method as described in any one of claims 3 to 7.

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