A signal generation circuit, method, and semiconductor memory

Abstract

Embodiments of the present application disclose a signal generation circuit, a method, and a semiconductor memory. The signal generation circuit includes: a clock module configured to generate a clock signal based on a flag signal; a control module configured to generate a control signal according to the number of transitions of the clock signal within a fixed time; a generation module connected to the clock module and the control module respectively, configured to receive the clock signal, the control signal, and the flag signal, and generate a target signal; when the flag signal changes from a first level to a second level, the target signal changes from a third level to a fourth level, and after the target signal maintains a target duration at the fourth level, the target signal changes from the fourth level to the third level; the generation module is further configured to determine the target duration according to the clock signal and the control signal.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and particularly to a signal generation circuit, method, and semiconductor memory. Background Art

[0002] Semiconductor memories can include volatile memories (such as dynamic random access memories or static random access memories) and non-volatile memories (such as flash memories, phase change memories, ferroelectric memories, magnetic memories, or resistive memories). Generally, volatile memories support high-speed random access and are often used as the main memory of computing systems (such as personal computers, servers, or workstations).

[0003] During the manufacturing process of semiconductor memories, due to the position differences on the same wafer or the parameter differences of field effect transistors between wafers of different batches, the manufactured semiconductor memories have different process corners. Therefore, the clock signals generated by ring oscillators inside the semiconductor memories will change with the process variation, and the signals controlled by the clock signals will also change with the process, resulting in a certain error between the signals controlled by the clock signals in different semiconductor memories and the expected values at different process corners, and even exceeding the standard requirements. Summary of the Invention

[0004] In view of this, embodiments of the present application provide a signal generation circuit, method, and semiconductor memory to solve at least one problem existing in the prior art.

[0005] To achieve the above object, the technical solutions of the embodiments of the present application are implemented as follows:

[0006] In a first aspect, an embodiment of the present application provides a signal generation circuit, the circuit including:

[0007] A clock module, configured to generate a clock signal based on a flag signal;

[0008] A control module, configured to generate a control signal according to the number of transitions of the clock signal within a fixed time;

[0009] A generation module, respectively connected to the clock module and the control module, configured to receive the clock signal, the control signal, and the flag signal, and generate a target signal; when the flag signal changes from a first level to a second level, the target signal changes from a third level to a fourth level, and after the target signal maintains a target duration at the fourth level, it changes from the fourth level to the third level; the generation module is further configured to determine the target duration according to the clock signal and the control signal.

[0010] In an alternative embodiment, the clock module includes a ring oscillator; when the flag signal changes from the first level to the second level, the ring oscillator generates the clock signal.

[0011] In an alternative embodiment, the generation module includes a counter; when the flag signal changes from the first level to the second level, the counter starts counting the clock signal, and when the count value reaches the target value represented by the control signal, it controls the target signal to change back from the fourth level to the third level.

[0012] In an alternative embodiment, the first level is a low level, the second level is a high level, the third level is a low level, and the fourth level is a high level.

[0013] In an alternative embodiment, the flag signal is a check flag signal, and the check flag signal is used to represent a parity check error or a redundancy check error.

[0014] In an alternative embodiment, the period of the clock signal increases with the change of the process; the target value represented by the control signal decreases with the change of the process;

[0015] The change of the process is the change from the FF process corner to the SS process corner.

[0016] In an alternative embodiment, the control module includes a process monitor and an arithmetic unit; wherein,

[0017] The process monitor is used to output a process monitor code representing the number of transitions of the clock signal occurring within a fixed time;

[0018] The arithmetic unit is used to receive the process monitor code and output the process monitor code multiplied by a coefficient as the control signal.

[0019] In a second aspect, an embodiment of the present application provides a signal generation method, and the method includes:

[0020] Generating a clock signal based on a flag signal through a clock module and outputting the clock signal to a generation module;

[0021] Generating a control signal according to the number of transitions of the clock signal within a fixed time through a control module and outputting the control signal to the generation module;

[0022] The generating module receives the clock signal, the control signal, and the flag signal, and generates a target signal; when the flag signal changes from a first level to a second level, the target signal changes from a third level to a fourth level, and after the target signal maintains a target duration at the fourth level, it changes from the fourth level to the third level; the target duration is determined by the generating module according to the clock signal and the control signal.

[0023] In an alternative embodiment, the generating the clock signal by the clock module based on the flag signal includes:

[0024] When the flag signal changes from the first level to the second level, the ring oscillator generates the clock signal.

[0025] In an alternative embodiment, the when the flag signal changes from a first level to a second level, the target signal changes from a third level to a fourth level, and after the target signal maintains a target duration at the fourth level, it changes from the fourth level to the third level, includes:

[0026] When the flag signal changes from the first level to the second level, the counter counts the clock signal, and when the count value reaches the target value represented by the control signal, the counter controls the target signal to change from the fourth level to the third level.

[0027] In an alternative embodiment, the first level is a low level, the second level is a high level, the third level is a low level, and the fourth level is a high level.

[0028] In an alternative embodiment, the flag signal is a parity check flag signal, and the parity check flag signal is used to represent an odd-even check error or a redundancy check error.

[0029] In an alternative embodiment, the period of the clock signal increases with the change of the process; the target value represented by the control signal decreases with the change of the process;

[0030] The change of the process is the change from the FF process corner to the SS process corner.

[0031] In an alternative embodiment, the generating the control signal by the control module according to the number of transitions of the clock signal within a fixed time includes:

[0032] The process monitor outputs a process monitor code representing the number of transitions of the clock signal within a fixed time;

[0033] The arithmetic unit receives the process monitor code, and multiplies the process monitor code by a coefficient and outputs it as the control signal.

[0034] In a third aspect, an embodiment of the present application provides a semiconductor memory, including the signal generation circuit described in any one of the first aspects.

[0035] In an optional implementation manner, the semiconductor memory is a dynamic random access memory DRAM chip.

[0036] In an optional implementation manner, the dynamic random access memory DRAM chip complies with the DDR4 memory specification.

[0037] In the technical solution provided by the present application, a control module is configured in the signal generation circuit, and the control module can generate a control signal according to the number of transitions of the clock signal within a fixed time. In the embodiment of the present application, generating the control signal according to the number of transitions of the clock signal within a fixed time can ensure that the control signal is associated with the frequency / cycle change trend of the clock signal, so that the target signal finally generated by the generating module is not limited by the influence of the clock signal; and the target duration for which the target signal is maintained at the fourth level is determined by the clock signal and the control signal, thereby controlling the pulse width of the target signal. Description of the Drawings

[0038] In the drawings, unless otherwise specified, the same reference numerals throughout the several views denote the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in accordance with the present application and should not be regarded as limiting the scope of the present application.

[0039] Figure 1 It is the parity check alarm circuit of a common DDR4 chip;

[0040] Figure 2 It is a schematic diagram of the pulse width deviation of the ALERT signal under different processes;

[0041] Figure 3 It is a schematic structural diagram of a signal generation circuit provided by an embodiment of the present application;

[0042] Figure 4 It is a trend chart of the process monitoring code changing with the process provided by an embodiment of the present application;

[0043] Figure 5 It is a trend chart of the period of the clock signal changing with the process provided by an embodiment of the present application;

[0044] Figure 6 It is a trend chart of the target duration changing with the process provided by an embodiment of the present application;

[0045] Figure 7Schematic diagram of the pulse width of the ALERT signal under different processes;

[0046] Figure 8 Schematic diagram of the implementation process of a signal generation method provided by an embodiment of the present application. Detailed implementation manners

[0047] The exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided so that the present application can be more thoroughly understood and the scope of the present application disclosed can be fully communicated to those skilled in the art.

[0048] In the following description, numerous specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some well-known technical features are not described; that is, not all features of the actual embodiments are described here, and the well-known functions and structures are not described in detail.

[0049] In addition, the accompanying drawings are only schematic diagrams of the present application and are not necessarily drawn to scale. The same reference numerals in the drawings represent the same or similar parts, and thus their repeated description will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0050] The flowcharts shown in the accompanying drawings are only illustrative and do not necessarily include all steps. For example, some steps can be decomposed, and some steps can be combined or partially combined, so the actual execution order may be changed according to the actual situation.

[0051] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present application. When used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. When used herein, the term "and / or" includes any and all combinations of the related listed items.

[0052] In the SPEC (Specification) of DDR4 chips, the pulse width tPAR_ALERT_PW of the ALERT signal output by the Command / Address Bus Parity Alert system (C / A Parity Alert) is specified to be between 60 ns and 120 ns. Figure 1 For the parity check alert circuit of a common DDR4 chip, in this circuit design, after a parity check error occurs, a PAR_Error_Flag signal is output to enable a ring oscillator, so that the ring oscillator generates a clock signal CLK with a fixed period of T'. Then, according to the SPEC requirements of tPAR_ALERT_PW, the number of stages N' of the counter is determined. Through such a circuit design, the parity check alert circuit outputs logic 1 when receiving the PAR_Error_Flag signal, and then outputs logic 0 after the counting of the counter ends. The final result is that the pulse width tPAR_ALERT_PW of the output ALERT signal is tPAR_ALERT_PW = T' × N', where T' is the period of the clock signal generated by the ring oscillator and N' is the number of stages of the counter.

[0053] However, although the pulse width of the ALERT signal output by this circuit design does not change with the chip operating frequency, it will change with the process. During the manufacturing process of semiconductor devices, due to the position difference on the same wafer or the parameter differences of field effect transistors between different batches of wafers, deviations will occur, and this deviation is called the process corner. The process corner is generally divided into three types: slow-slow (SS), typical-typical (TT), and fast-fast (FF). Figure 2 As the pulse width deviation of the ALERT signal under different process corners, as Figure 2 shown, in the case of particularly large process variations, the period T' of the clock signal CLK generated by the ring oscillator will have a large difference. For example, in the FF process corner, the period T' of the clock signal CLK generated by the ring oscillator is smaller, while in the SS process corner, the period T' of the clock signal CLK generated by the ring oscillator is larger. Under the amplification of the number of stages N' of the counter, finally, the pulse width tPAR_ALERT_PW of the ALERT signal in the SS process corner is very likely to exceed the 60 ns - 120 ns interval specified by the SPEC, and the pulse width tPAR_ALERT_PW of the ALERT signal in the FF process is also very likely to be less than the 60 ns - 120 ns interval specified by the SPEC.

[0054] Therefore, the following technical solutions of the embodiments of the present application are proposed.

[0055] An embodiment of the present application provides a signal generation circuit. Figure 3 As shown in the structural schematic diagram of a signal generation circuit provided by an embodiment of the present application, Figure 3 as shown, the circuit includes:

[0056] A clock module 310, configured to generate a clock signal based on a flag signal;

[0057] A control module 320, configured to generate a control signal according to the number of transitions of the clock signal within a fixed time;

[0058] A generation module 330, respectively connected to the clock module 310 and the control module 320, configured to receive the clock signal, the control signal, and the flag signal, and generate a target signal; when the flag signal changes from a first level to a second level, the target signal changes from a third level to a fourth level, and after the target signal maintains a target duration at the fourth level, it changes from the fourth level to the third level; the generation module 330 is further configured to determine the target duration according to the clock signal and the control signal.

[0059] Here, the target duration that the target signal output by the generation module 330 maintains at the fourth level is the pulse width of the target signal output by the generation module 330.

[0060] In the embodiment of the present application, the control signal is generated according to the number of transitions of the clock signal within a fixed time, so that the control signal is a signal related to the clock signal. Therefore, when the frequency / period of the clock signal changes, the control signal can also change accordingly. Thus, the pulse width of the target signal can be adjusted by the clock signal and the control signal.

[0061] Furthermore, in the embodiment of the present application, the pulse width of the target signal is adjusted by the clock signal and the control signal to control the pulse width of the target signal within a certain range, weaken or eliminate the change of the pulse width of the target signal with the clock signal, and make the pulse width of the target signal stable.

[0062] An embodiment of the present application provides a signal generation circuit for generating a target signal and adjusting the pulse width of the target signal to make it stable within a certain range. This signal generation circuit can be widely used in semiconductor memories, such as DDR2, DDR3, DDR4, LPDDR2, LPDDR3, etc., which will not be listed one by one here.

[0063] The clock module 310 provided by the embodiment of the present application includes a ring oscillator; when the flag signal changes from the first level to the second level, the ring oscillator generates the clock signal. In the embodiment of the present application, the ring oscillator is utilized to generate the clock signal as the internal clock signal.

[0064] In the embodiment of the present application, the control module 320 includes a process monitor 321 and an arithmetic unit 322; wherein, the process monitor 321 is configured to output a process monitor code representing the number of transitions of the clock signal occurring within a fixed time; the arithmetic unit 322 is configured to receive the process monitor code and output the process monitor code multiplied by a coefficient as the control signal. In the embodiment of the present application, the control signal is obtained by multiplying the process monitor code by a coefficient.

[0065] Here, the process monitor code (Process Monitor Code) is a parameter representing the number of transitions of the clock signal occurring within a fixed time in the test mode (Test Mode). Since the number of transitions of the clock signal occurring within a fixed time changes with the process, the process monitor code also changes with the process. Specifically, different chips on the same wafer or wafers of the same batch may have different process corners, so the frequencies / periods of the clock signals of these chips with different process corners will all have differences, and thus the process monitor codes representing the number of transitions of the clock signal occurring within a fixed time will also have differences. In the embodiment of the present application, the difference caused by different process corners is referred to as the change with the process. In the embodiment of the present application, the change of the process monitor code with the process and the change of the clock signal with the process are utilized to adjust the pulse width of the target signal, so as to control the pulse width of the target signal within a certain range, thereby weakening or eliminating the change of the pulse width of the target signal with the process and making the pulse width of the target signal stable.

[0066] Since the frequency of the clock signal decreases with the change of the process, in other words, the period of the clock signal increases with the change of the process. Thus, when the frequency of the clock signal decreases or the period of the clock signal increases, the number of transitions of the clock signal within a fixed time will decrease, and in this way, the process monitor code will also decrease with the change of the process. And the control signal is a signal obtained by multiplying the process monitor code by a coefficient, so the control signal will also decrease with the change of the process. Wherein, the change of the process is the change from the FF process corner to the SS process corner.

[0067] In a specific embodiment, when the signal generation circuit is applied to a DDR4 chip, the process monitor 321 is used to output a process monitor code P; the arithmetic unit 322 is used to receive the process monitor code P, and multiply the process monitor code by a coefficient N and then output it as the control signal. Figure 4 FIG. Figure 4 is a graph showing the variation trend of the process monitor code with the process provided by the embodiment of the present application. Since the process monitor code P represents the number of transitions of the clock signal within a fixed time, the process monitor code P decreases with the change of the process, and the variation trend of the process monitor code P with the process is opposite to the variation trend of the period of the clock signal with the process. Therefore, the control signal generated based on the process monitor code P can effectively compensate for the variation of the pulse width of the target signal with the process.

[0068] Here, the coefficient N is the amplification coefficient of the process monitor code. In practical applications, the corresponding coefficient N can be selected according to the pulse width of the actual target signal. Here, the number of stages of the counter is the target value N×P represented by the control signal. In the embodiment of the present application, the process monitor code P decreases with the change of the process, so the target value represented by the control signal decreases with the change of the process; the change of the process is from the FF process corner to the SS process corner.

[0069] Here, the control signal is the counter stage selection signal of the counter. The counter can determine its number of stages according to the control signal, and then perform counting based on the number of stages.

[0070] In the embodiment of the present application, the flag signal is a parity check flag signal, and the parity check flag signal is used to represent a parity check error or a redundancy check error.

[0071] In the embodiment of the present application, the generation module 330 includes a counter; when the flag signal changes from the first level to the second level, the counter starts to count the clock signal. When the count value reaches the target value represented by the control signal, the target signal is controlled to change from the fourth level to the third level. When the flag signal is used to represent a parity check error, after a parity check error occurs, the flag signal PAR_Error_Flag is output. The flag signal PAR_Error_Flag is active high. Therefore, when the flag signal PAR_Error_Flag changes from low level to high level, the generation module controls the target signal to change from low level to high level, and at the same time the counter starts to count the clock signal. When the count value reaches the target value represented by the control signal, the target signal is controlled to change from high level to low level.

[0072] In some embodiments, the flag signal is used to characterize a parity error. After a parity error occurs, a parity check flag signal PAR_Error_Flag is output. Then, the target signal generated by the generation module is a parity check alert signal ALERT. Thus, the pulse width tPAR_ALERT_PW of the parity check alert signal can be adjusted by the signal generation circuit provided in the embodiments of the present application, so as to control the pulse width tPAR_ALERT_PW of the parity check alert signal within a certain range, weaken or eliminate the variation of the pulse width tPAR_ALERT_PW of the parity check alert signal with the process, and make the pulse width tPAR_ALERT_PW of the parity check alert signal stable within the range specified by SPEC.

[0073] It should be noted that the ALERT signal here is not the signal finally output through the alert_n pin. The ALERT signal needs to go through several inverters or output buffer circuits before it is output to the alert_n pin of the chip. In a specific example, the ALERT signal can be output to the alert_n pin of the chip after passing through an odd number of inverters, so as to ensure that the alert_n signal output from the alert_n pin is active low.

[0074] Here, the number of stages of the counter is the target value N×P represented by the control signal. If the period of the clock signal is T, then the target duration (the pulse width of the target signal) is T×N×P. Among them, the variation trends of P and T with the process are opposite. Therefore, the target duration (the pulse width of the target signal) hardly changes with the process. In other words, the target duration (the pulse width of the target signal) is stable within the range specified by SPEC under different processes. Among them, the change of the process is the change from the FF process corner to the SS process corner.

[0075] Figure 5 This is a graph showing the variation trend of the period of the clock signal provided in the embodiments of the present application with the process. Figure 6 This is a graph showing the variation trend of the target length provided in the embodiments of the present application with the process. Figure 5 In it, the ordinate is the period of the clock signal and the abscissa is the process. Figure 6 In it, the ordinate is the target duration and the abscissa is the process. Combining Figure 4 、 Figure 5 and Figure 6As shown, the period T of the clock signal increases with the change of the process, the process monitoring code P representing the number of transitions of the clock signal occurring within a fixed time decreases with the change of the process, and thus the target value N×P represented by the control signal also decreases with the change of the process. Then, the target duration T×N×P obtained based on the period T of the clock signal and the target value N×P represented by the control signal can also be stabilized within the range specified by SPEC under process variations.

[0076] Figure 7 It is a schematic diagram of the pulse width of the ALERT signal under different processes. Figure 7 The ALERT signal in [reference] is generated based on the signal generation circuit provided in the embodiments of the present application. As Figure 7 shown, at the FF process corner, the period T of the clock signal CLK generated by the ring oscillator is small, but the target value N×P (the number of stages of the counter) represented by the control signal is large; at the SS process corner, the period T of the clock signal CLK generated by the ring oscillator is large, but the target value N×P (the number of stages of the counter) represented by the control signal is small. Therefore, the pulse width of the finally output ALERT signal changes little at the FF process corner and the SS process corner. That is, through the common control of the clock signal and the control signal, the pulse width of the target signal can be controlled within a certain range, weakening or eliminating the change of the pulse width of the target signal with the process, and stabilizing the pulse width of the target signal within the range specified by SPEC.

[0077] In the embodiments of the present application, the first level is a low level, the second level is a high level, the third level is a low level, and the fourth level is a high level. Then, when the flag signal changes from a low level to a high level, the target signal changes from a low level to a high level. After the target signal maintains the target duration at the high level, it changes from a high level to a low level. Here, the flag signal is a check flag signal, and the check flag signal is active high. When the check flag signal is at a high level, it indicates that a check error has occurred; when the check flag signal is at a low level, it indicates that no check error has occurred. In the embodiments of the present application, the target duration is determined according to the period of the clock signal and the target value represented by the control signal, and the period of the clock signal and the target value represented by the control signal have opposite trends with the change of the process. Thus, the target duration (the pulse width of the target signal) hardly changes with the change of the process. In other words, the target duration (the pulse width of the target signal) remains stable under different processes.

[0078] Based on the same technical concept as the aforementioned signal generation circuit, the embodiments of the present application provide a signal generation method. Figure 8 It is a schematic diagram of the implementation process of a signal generation method provided by the embodiments of the present application. As Figure 8 shown, the method mainly includes the following steps:

[0079] Step 810: Generate a clock signal based on a flag signal by a clock module, and output the clock signal to a generation module.

[0080] Step 820: Generate a control signal according to the number of transitions of the clock signal within a fixed time by a control module, and output the control signal to the generation module.

[0081] Step 830: The generation module receives the clock signal, the control signal, and the flag signal, and generates a target signal; when the flag signal changes from a first level to a second level, the target signal changes from a third level to a fourth level, and after the target signal maintains a target duration at the fourth level, it changes from the fourth level to the third level; the target duration is determined by the generation module according to the clock signal and the control signal.

[0082] Here, the target duration that the target signal output by the generation module maintains at the fourth level is the pulse width of the target signal output by the generation module.

[0083] In an embodiment of the present application, the flag signal is a check flag signal, and the check flag signal is used to represent an odd parity check error or a redundancy check error.

[0084] In an embodiment of the present application, step 810 includes: when the flag signal changes from the first level to the second level, a ring oscillator generates the clock signal. In an embodiment of the present application, the ring oscillator is used to generate the clock signal as an internal clock signal.

[0085] The control signal in an embodiment of the present application is generated according to the number of transitions of the clock signal within a fixed time, so that the control signal is a signal related to the clock signal. Thus, when the frequency / period of the clock signal changes, the control signal can also change accordingly. Thus, the pulse width of the target signal can be adjusted by the clock signal and the control signal.

[0086] Further, in an embodiment of the present application, the pulse width of the target signal is adjusted by the clock signal and the control signal to control the pulse width of the target signal within a certain range, weaken or eliminate the change of the pulse width of the target signal with the clock signal, and make the pulse width of the target signal stable.

[0087] In an embodiment of the present application, step 820 includes: outputting a process monitoring code representing the number of transitions of the clock signal within a fixed time by a process monitor; a calculator receives the process monitoring code and outputs the process monitoring code multiplied by a coefficient as the control signal.

[0088] Here, the Process Monitor Code is a parameter that characterizes the number of transitions of the clock signal within a fixed time in the Test Mode. Since the number of transitions of the clock signal within a fixed time changes with the process, the Process Monitor Code also changes with the process. In the embodiments of the present application, the pulse width of the target signal is adjusted by using the change of the Process Monitor Code with the process and the change of the clock signal with the process, so as to control the pulse width of the target signal within a certain range, thereby weakening or eliminating the change of the pulse width of the target signal with the process and making the pulse width of the target signal stable.

[0089] Since the frequency of the clock signal decreases with the change of the process, in other words, the period of the clock signal increases with the change of the process. Thus, when the frequency of the clock signal decreases or the period of the clock signal increases, the number of transitions of the clock signal within a fixed time will decrease. In this way, the Process Monitor Code also decreases with the change of the process. And the control signal is a signal obtained by multiplying the Process Monitor Code by a coefficient, so the control signal also decreases with the change of the process. Wherein, the change of the process is from the FF process corner to the SS process corner.

[0090] In the embodiments of the present application, when the flag signal changes from the first level to the second level, the target signal changes from the third level to the fourth level. After the target signal maintains the target duration at the fourth level, it changes from the fourth level to the third level, including: when the flag signal changes from the first level to the second level, the clock signal is counted by a counter. When the count value reaches the target value represented by the control signal, the counter controls the target signal to change from the fourth level to the third level.

[0091] Here, the number of stages of the counter is the target value N×P represented by the control signal. If the period of the clock signal is T, then the target duration (pulse width of the target signal) is T×N×P. Wherein, the change trends of P and T with the process are opposite. Therefore, the target duration (pulse width of the target signal) hardly changes with the process. In other words, the target duration (pulse width of the target signal) remains stable under different processes.

[0092] In the embodiments of the present application, the first level is a low level, the second level is a high level, the third level is a low level, and the fourth level is a high level.

[0093] The embodiment of the present application further provides a semiconductor memory, including the signal generation circuit described above. The semiconductor memory referred to in the present application includes, but is not limited to, dynamic random access memory, etc. The semiconductor memory can adopt the signal generation circuit of the present application to adjust the pulse width of the target signal generated by it, so that the pulse width of the target signal is not affected by the process and is stabilized within a certain range. In other words, the semiconductor memory can adopt the signal generation circuit of the present application to adjust the pulse width of the target signal generated by it, so that the pulse width of the target signal is not affected by its process corner and is stabilized within a certain range.

[0094] In the embodiment of the present application, the dynamic random access memory DRAM chip complies with the DDR4 memory specification.

[0095] The methods disclosed in several method embodiments provided by the present application can be arbitrarily combined without conflict to obtain new method embodiments.

[0096] The features disclosed in several device embodiments provided by the present application can be arbitrarily combined without conflict to obtain new device embodiments.

[0097] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A signal generation circuit, characterized in that, The circuit includes: A clock module for generating a clock signal based on a flag signal; A control module for generating a control signal according to the number of transitions of the clock signal within a fixed time; A generating module connected to the clock module and the control module respectively, for receiving the clock signal, the control signal and the flag signal, and generating a target signal; when the flag signal changes from a first level to a second level, the target signal changes from a third level to a fourth level, and after the target signal maintains a target duration at the fourth level, it changes from the fourth level to the third level; the generating module is further configured to determine the target duration according to the clock signal and the control signal; The control module includes a process monitor and an arithmetic unit; wherein, The process monitor is configured to output a process monitor code characterizing the number of transitions of the clock signal within a fixed time; The arithmetic unit is configured to receive the process monitor code and output the process monitor code multiplied by a coefficient as the control signal; Denote the process monitor code as P and the coefficient as N; If the period of the clock signal is T, then the target duration is T×N×P.

2. The signal generation circuit according to claim 1, wherein The clock module includes a ring oscillator; when the flag signal changes from the first level to the second level, the ring oscillator generates the clock signal.

3. The signal generation circuit according to claim 1, characterized in that The generating module includes a counter; when the flag signal changes from the first level to the second level, the counter starts to count the clock signal, and when the count value reaches the target value represented by the control signal, controls the target signal to change back from the fourth level to the third level.

4. The signal generation circuit according to any one of claims 1 to 3, characterized in that, The first level is a low level, the second level is a high level, the third level is a low level, and the fourth level is a high level.

5. The signal generation circuit according to claim 1, wherein The flag signal is a parity check flag signal, and the parity check flag signal is used to characterize a parity check error or a redundancy check error.

6. The signal generating circuit according to claim 1, wherein The period of the clock signal increases with the change of the process; the target value represented by the control signal decreases with the change of the process; The change of the process is from the FF process corner to the SS process corner.

7. A signal generation method, characterized in that, The method includes: Generating a clock signal based on a flag signal through a clock module and outputting the clock signal to a generating module; Generating a control signal according to the number of transitions of the clock signal within a fixed time through a control module and outputting the control signal to the generating module; The generating module receives the clock signal, the control signal and the flag signal, and generates a target signal; when the flag signal changes from a first level to a second level, the target signal changes from a third level to a fourth level, and after the target signal maintains a target duration at the fourth level, it changes from the fourth level to the third level; the target duration is determined by the generating module according to the clock signal and the control signal; The generating the control signal according to the number of transitions of the clock signal within a fixed time through the control module includes: Output a process monitoring code through a process monitor to characterize the number of transitions of the clock signal occurring within a fixed time; The arithmetic unit receives the process monitoring code and outputs the process monitoring code multiplied by a coefficient as the control signal; Let the process monitoring code be P and the coefficient be N; If the period of the clock signal is T, then the target duration is T×N×P.

8. The signal generation method according to claim 7, wherein The generating the clock signal by the clock module based on the flag signal includes: When the flag signal changes from the first level to the second level, the ring oscillator generates the clock signal.

9. The signal generation method according to claim 7, wherein When the flag signal changes from the first level to the second level, the target signal changes from the third level to the fourth level, and after the target signal maintains the target duration at the fourth level, it changes from the fourth level to the third level, including: When the flag signal changes from the first level to the second level, the clock signal is counted by a counter, and when the count value reaches the target value represented by the control signal, the counter controls the target signal to change from the fourth level to the third level.

10. The signal generation method according to any one of claims 7 to 9, characterized in that, The first level is a low level, the second level is a high level, the third level is a low level, and the fourth level is a high level.

11. The signal generation method according to claim 7, wherein The flag signal is a parity check flag signal, and the parity check flag signal is used to characterize a parity check error or a redundancy check error.

12. The signal generation method according to claim 7, wherein The period of the clock signal increases with the change of the process; the target value represented by the control signal decreases with the change of the process; The change of the process is from the FF process corner to the SS process corner.

13. A semiconductor memory, characterized in that, It includes the signal generation circuit according to any one of claims 1 to 6.

14. The semiconductor memory according to claim 13, wherein, The semiconductor memory is a dynamic random access memory DRAM chip.

15. The semiconductor memory according to claim 14, wherein, The dynamic random access memory DRAM chip conforms to the DDR4 memory specification.

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