Test assembly, test system, and test method

Abstract

The embodiment of the present disclosure provides a test assembly, a test system and a test method, the test assembly comprising: an interposer and a test fixture matched with the interposer; the test fixture comprising a first test board configured to fix a chip to be tested and realize electrical connection between the chip to be tested and the interposer during testing; the test fixture further comprising a second test board located above the first test board and electrically connected with the first test board, the second test board being configured to be electrically connected with a test device during testing to realize test on the chip to be tested.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a test assembly, a test system and a test method. BACKGROUND

[0002] With the continuous development of Internet technology, the application of solid state disk (SSD) is becoming more and more widespread. In order to improve the performance of the final product, it is necessary to test the solid state disk, for example, to perform signal integrity (SI) test on the chips in the solid state disk. However, the test results of some current chip test methods have large errors. Therefore, how to improve the test accuracy has become a problem to be solved. SUMMARY

[0003] According to a first aspect of embodiments of the present disclosure, a test assembly is provided, comprising:

[0004] an interposer and a test fixture adapted to the interposer; the test fixture comprising a first test board configured to fix a chip under test and realize electrical connection between the chip under test and the interposer during testing;

[0005] the test fixture further comprises a second test board located above the first test board and electrically connected to the first test board, the second test board being configured to be electrically connected to a test device during testing to realize testing of the chip under test.

[0006] In some embodiments, the test fixture is further configured to move towards the interposer when subjected to a pressure towards the interposer to realize electrical connection between the test fixture and the interposer.

[0007] In some embodiments, the second test board comprises a printed circuit board.

[0008] In some embodiments, the interposer comprises a first surface, the first surface comprising a chip fixing area, and the chip under test is located in the chip fixing area.

[0009] In some embodiments, the chip under test is fixed on the chip fixing area of the interposer by means of adhesive or welding.

[0010] According to a second aspect of embodiments of the present disclosure, a test system is provided, comprising a test assembly as described in the above embodiments; and

[0011] a substrate;

[0012] The intermediate plate is configured to be electrically connected with the substrate and the chip under test respectively during testing, so as to transmit a test input signal between the substrate and the chip under test.

[0013] In some embodiments, the second test plate is specifically configured to transmit a test output signal fed back by the chip under test based on the test input signal to the test device, so as to realize testing of the chip under test.

[0014] In some embodiments, the test fixture further comprises a contact probe penetrating through the first test plate, one end of the contact probe being electrically connected with the second test plate; wherein,

[0015] After the test fixture moves towards the intermediate plate, the other end of the contact probe is electrically connected with the intermediate plate;

[0016] When the other end of the contact probe is electrically connected with the intermediate plate, the contact probe is configured to receive the test output signal transmitted by the intermediate plate and transmit the test output signal to the second test plate.

[0017] In some embodiments, the first test plate comprises a plurality of moving modules, each of the moving modules being provided with a contact probe penetrating through the moving module;

[0018] The intermediate plate comprises a first surface parallel to the substrate, the first surface being provided with a first interface corresponding to the contact probe; wherein,

[0019] After the test fixture moves towards the intermediate plate, the other end of the contact probe is electrically connected with the first interface.

[0020] In some embodiments, the surface of the first test plate relatively close to the substrate comprises a first region and a second region surrounding the first region; wherein, the moving modules and the contact probes are located in the second region;

[0021] The first test plate further comprises a spring, one end of the spring being located at a central position of the first region, the other end of the spring being fixedly connected with the moving modules;

[0022] The spring is configured to adjust the position of the moving modules by stretching and retracting, so as to adjust the position of the contact probes.

[0023] In some embodiments, the test device comprises an oscilloscope, and the second test plate comprises a test contact point, the test contact point being located on a surface of the second test plate relatively far away from the substrate; wherein,

[0024] The test contact is configured to transmit the test output signal of the chip under test to the oscilloscope.

[0025] In some embodiments, a test probe of the oscilloscope is fixedly connected to the test contact.

[0026] In some embodiments, the test device comprises a logic analyzer, and the second test board comprises a test probe located on a surface of the second test board opposite to the substrate; wherein,

[0027] The test probe is configured to transmit the test output signal of the chip under test to the logic analyzer.

[0028] In some embodiments, the intermediate board comprises a second surface parallel to the substrate, and a plurality of second interfaces are arranged on the second surface, and a third interface corresponding to the second interface is arranged on the substrate; wherein, the second interface is electrically connected to the third interface.

[0029] According to a third aspect of the embodiments of the present disclosure, a test method is provided, comprising:

[0030] providing a substrate and an intermediate board; wherein, the intermediate board is electrically connected to the substrate;

[0031] clamping a chip under test by a test clamp;

[0032] moving the test clamp clamping the chip under test towards the intermediate board, so that the test clamp is electrically connected to the intermediate board; wherein, the test clamp comprises a first test board, the first test board is electrically connected to the intermediate board, the chip under test is electrically connected to the intermediate board, and the intermediate board is used to transmit a test input signal between the substrate and the chip under test;

[0033] receiving, by a test device, a test output signal transmitted by the chip under test based on the test input signal to test the chip under test; wherein, the test device is electrically connected to a second test board, the second test board is electrically connected to the first test board, and the second test board is located above the first test board.

[0034] In some embodiments, the test clamp further comprises a contact probe penetrating through the first test board, one end of the contact probe is electrically connected to the second test board, and the intermediate board comprises a first surface parallel to the substrate, and a first interface corresponding to the contact probe is arranged on the first surface.

[0035] The test fixture clamping the to-be-tested chip is moved towards the direction of the intermediate board, so that the test fixture is electrically connected with the intermediate board, including:

[0036] A pressure is applied to the test fixture towards the direction of the intermediate board, so that the other end of the contact probe is electrically connected with the first interface.

[0037] In some embodiments, the test method further includes:

[0038] After the test work on the to-be-tested chip is completed, the connection between the test fixture and the test device is disconnected;

[0039] After the connection between the test fixture and the test device is disconnected, the test fixture is controlled to release the fixation on the to-be-tested chip.

[0040] The test assembly provided by the embodiments of the present disclosure fixes the to-be-tested chip through the test fixture, improves the contact stability of the to-be-tested chip, reduces the probability of test signal interruption caused by shaking of the to-be-tested chip during testing, and improves the test accuracy. The test fixture includes a first test board and a second test board. The first test board is electrically connected with the intermediate board during testing. The second test board is electrically connected with the first test board and is located above the first test board. The test output signal of the to-be-tested chip is transmitted to the second test board at the top of the test fixture through the intermediate board. Therefore, when the test device is connected to the second test board at the top of the test fixture, there is a large operation space, which increases the operation space for welding the test device to the test fixture, thereby saving the welding time and reducing the probability of welding errors, and finally improving the test accuracy of the to-be-tested chip. BRIEF DESCRIPTION OF DRAWINGS

[0041] Figure 1 A test structure schematic diagram according to an exemplary embodiment is shown.

[0042] Figure 2 Another test structure schematic diagram according to an exemplary embodiment is shown.

[0043] Figure 3a A test assembly schematic diagram according to an embodiment of the present disclosure is shown.

[0044] Figure 3b A test system schematic diagram according to an embodiment of the present disclosure is shown.

[0045] Figure 4 A schematic diagram of a test fixture after movement according to an embodiment of the present disclosure is shown.

[0046] Figure 5 A test fixture schematic diagram according to an embodiment of the present disclosure is shown.

[0047] Figure 6 FIG. 1 is a top view of a first test board in a test fixture according to an embodiment of the present disclosure;

[0048] Figure 7 FIG. 2 is a top view of a second test board in a test fixture according to an embodiment of the present disclosure;

[0049] Figure 8 FIG. 3 is a flow diagram of a test method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0050] The technical solutions of the present disclosure are further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0051] In the embodiments of the present disclosure, the terms "first", "second", and the like are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0052] In the embodiments of the present disclosure, the term "A is in contact with B" includes the case where A is in direct contact with B, or the case where A is indirectly in contact with B with other components interposed between A and B.

[0053] In the embodiments of the present disclosure, the term "layer" refers to a portion of material that includes a region having a thickness. The layer can extend over the entirety of an underlying or overlying structure, or can have a scope less than the scope of an underlying or overlying structure. Further, a layer can be a region of a homogenous or inhomogenous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer can be located between a top surface and a bottom surface of a continuous structure, or the layer can be between any horizontal pair of planes at the top surface and the bottom surface of the continuous structure. A layer can extend horizontally, vertically, and / or along an inclined surface. Also, a layer can include a plurality of sub-layers.

[0054] It can be understood that the meanings of "on", "over", and "above" in the present disclosure should be interpreted in the broadest way, such that "on" not only means "on" something with no intervening features or layers therebetween (i.e., directly on something), but also includes "on" something with intervening features or layers therebetween.

[0055] In the present disclosure, unless specifically defined otherwise and limited, the terms "mount", "connect", "connection", "fixed", and the like should be interpreted broadly, for example, can be fixed connection, can also be detachable connection, or integrated; can be mechanical connection, can also be electrical connection or can communicate with each other; can be directly connected, or indirectly connected through an intermediate medium; can be the internal communication of two elements or the interaction relationship between two elements. The specific meanings of the above terms in the present disclosure can be understood according to the specific circumstances.

[0056] With the increasing demand for storage capacity, the density of solid state disk on-board devices gradually increases. In the process of timing test of storage chips of solid state disk, since most of the on-board storage chips exist back paste, it is impossible to increase test points near the storage chips during test wiring. If test points are increased far away from the storage chips, there are signal integrity (SI) problems such as reflection, which cannot accurately reflect the actual signal waveform of the storage chip.

[0057] During signal wiring, it is required to have less via and less branch during wiring to avoid stub. The stub will generate parasitic capacitance, causing signal reflection and crosstalk or generating large electromagnetic radiation, reducing signal quality. Therefore, in order to improve the accuracy of the actual test signal waveform as much as possible, and to reduce the influence of via stub on signal quality as much as possible, and to reduce the influence of external test environment on the actual signal waveform, an interposer is added to introduce the signal to be tested through the test points on the surface of the interposer and then test.

[0058] In one solid state disk test method, as shown in Figure 1 , a stepped interposer 10 is used to test the storage chip 11 as shown in Figure 1 . The stepped interposer 10 has a two-layer structure, including a first layer 12 and a second layer 13, and the second layer 13 is located above the first layer 12. In order to reduce the influence of the interposer on the signal, a buried resistor can be added in the interposer, so that the volume of the second layer 13 of the stepped interposer 10 is larger than that of the first layer 12 of the interposer 10, as shown in Figure 1 . In the area where the second layer 13 of the stepped interposer 10 does not cover the first layer 12, there is a height limit between the second layer 13 of the stepped interposer 10 and the bottom substrate. Therefore, when the stepped interposer 10 is used in the test environment, there may be interference problems in the height limited area, which causes the signal to be unable to be normally transmitted.

[0059] In another solid state disk test method, as shown in Figure 2 , a single-layer interposer 20 is smaller than the stepped interposer as shown in Figure 1 , and the single-layer interposer 20 is used to test the storage chip 21 as shown in Figure 2 . When the single-layer interposer 20 is used for signal integrity (SI) test, since the width of the single-layer interposer 20 can be 1mm larger than the width of the storage chip 21, which is the size parallel to the substrate surface, the signal to be tested of the storage chip 21 needs to be introduced to the stamp hole around the single-layer interposer 20 during test, as shown in Figure 2The probe of the oscilloscope or the probe of the logic analyzer is welded to the stamp hole on the middle test point 22, however, the space for operation on the stamp hole around the small single-layer interposer 20 is small, and the connection risk exists between the two adjacent welding points, which causes the test signal to be unable to be normally output. It can be seen that the welding difficulty is large due to the small space for operation, and the test timeliness and the test result accuracy are both adversely affected.

[0060] Therefore, the embodiment of the present disclosure provides a test assembly.

[0061] Reference Figure 3a , Figure 3a A structural schematic diagram of a test assembly 100 provided by the embodiment of the present disclosure is shown in FIG. 1. The test assembly 100 comprises:

[0062] An interposer 102 and a test fixture 103 matched with the interposer 102; the test fixture 103 comprises a first test plate 1031 configured to fix a chip under test 200 and realize electrical connection between the chip under test 200 and the interposer 102 during testing.

[0063] The test fixture 103 further comprises a second test plate 1032 located above the first test plate 1031 and electrically connected with the first test plate 1031, and the second test plate 1032 is configured to be electrically connected with a test device 104 during testing to realize testing of the chip under test 200.

[0064] Exemplarily, the chip under test is fixed by the test fixture 103, the contact stability of the chip under test is improved, the probability of test signal interruption caused by shaking of the chip under test during testing is reduced, and the test accuracy is improved.

[0065] It should be noted that the test fixture 103 comprises the first test plate 1031 and the second test plate 1032, the second test plate 1032 is electrically connected with the first test plate 1031, and the second test plate 1032 is located above the first test plate 1031, the test output signal of the chip under test 200 can be transmitted to the second test plate 1032 on the top of the test fixture 103, therefore, when the test device 104 is connected on the second test plate 1032 on the top of the test fixture 103, there is a large operation space, the operation space of the test device 104 welded to the test fixture 103 is increased, and then the welding time is saved and the probability of welding error is reduced, and finally the test accuracy of the chip under test is improved.

[0066] In some embodiments, with reference to Figure 3a The test fixture 103 is further configured to move towards the interposer 102 when subjected to a pressure in the direction of the interposer 102, so as to realize electrical connection between the test fixture 103 and the interposer 102.

[0067] In an example, the test fixture 103 can be pressed down manually by a tester to move the test fixture 103 towards the interposer 102 to achieve the electrical connection between the test fixture 103 and the interposer 102.

[0068] In another example, the test system further comprises a pressing rod (not shown) for moving the test fixture 103 away from the substrate 101 and applying pressure to the test fixture 103 to achieve the electrical connection between the test fixture 103 and the interposer 102. It should be noted that the up-and-down movement of the pressing rod can be driven by a pneumatic cylinder to adjust the position of the test fixture 103. In addition, the up-and-down movement of the pressing rod can also be driven by a motor.

[0069] In the embodiments of the present disclosure, the test fixture 103 is pressed down to achieve the electrical connection between the test fixture 103 and the interposer 102, and then the chip under test 200 is tested. When the test fixture 103 and the interposer 102 are in a disconnected state, the test of the chip under test 200 is stopped, which can improve the test flexibility of the chip under test.

[0070] In some embodiments, the second test board 1032 comprises a printed circuit board.

[0071] Exemplarily, the second test board 1032 comprises a low-power printed circuit board to optimize the power consumption of the test fixture. On the basis of achieving signal transmission through the second test board 1032, the overall power consumption of the test fixture can be reduced, and the test cost can be reduced.

[0072] In some embodiments, the interposer 102 comprises a first surface parallel to the substrate 101, and the first surface comprises a chip fixing area, and the chip under test 200 is located on the chip fixing area.

[0073] The width of the interposer 102 is greater than or equal to the width of the chip under test, so as to provide the chip fixing area to accommodate the chip under test 200. The width is the dimension parallel to the surface of the substrate 101.

[0074] In some embodiments, the chip under test 200 is fixed on the chip fixing area of the interposer 102 by an adhesive or welding.

[0075] In an example, the chip under test 200 is fixed on the chip fixing area of the interposer 102 by welding. Taking a chip with a ball grid array package as an example, the layout of the pads on the interposer 102 needs to correspond to the package balls of the specific chip under test 200. For example, the pads on the interposer 102 correspond to the balls A of the chip under test A. When the chip under test B is used, the pads on the interposer 102 correspond to the balls B of the chip under test B.

[0076] In another example, the chip 200 to be tested is fixed on the chip fixing area of the intermediate plate 102 by an adhesive. The fixing method using the adhesive instead of welding can reduce the number of weldings, increase the number of repeated uses of the intermediate plate 102, reduce resource waste and save testing costs.

[0077] Reference Figure 3b , Figure 3b A structural schematic diagram of a test system is provided for the embodiments of the present disclosure, and the test system includes the test assembly as described in the above embodiments.

[0078] The substrate 101;

[0079] The intermediate plate 102 is configured to be electrically connected with the substrate 101 and the chip 200 to be tested respectively during testing, so as to transmit a test input signal between the substrate 101 and the chip 200 to be tested.

[0080] In some embodiments, the second test plate 1032 is specifically configured to transmit a test output signal fed back by the chip 200 to be tested based on the test input signal to the test device 104, so as to realize the test on the chip 200 to be tested.

[0081] Specifically, reference is made to Figure 3b and Figure 5 , Figure 3b A structural schematic diagram of a test system is provided for the embodiments of the present disclosure, and the test system includes: a substrate 101; an intermediate plate 102 configured to be electrically connected with the substrate 101 during testing; a test fixture 103 including a first test plate 1031 configured to be electrically connected with the intermediate plate 102 during testing and to fix the intermediate plate 102 and a chip 200 to be tested; wherein the chip 200 to be tested is electrically connected with the intermediate plate 102 during testing; the intermediate plate 102 is configured to transmit a test input signal between the substrate 101 and the chip 200 to be tested; the test fixture 103 further includes a second test plate 1032 electrically connected with the first test plate 1031 and located above the first test plate 1031; the second test plate 1032 is configured to be electrically connected with a test device 104 during testing and to transmit a test output signal fed back by the chip 200 to be tested based on the test input signal to the test device 104, so as to realize the test on the chip 200 to be tested. It should be noted that the test input signal includes but is not limited to a read operation signal, a write operation signal or other control signals sent to the chip 200 to be tested through the substrate 101.

[0082] Reference Figure 3bThe substrate 101 includes a carrier plate and other electronic components disposed on the carrier plate. The carrier plate can include a printed circuit board (PCB), and thus the substrate 101 can be a printed circuit board assembly (PCBA). As shown in FIG. 2A, a dashed box 201 illustrates a packaging position of a storage chip in a single-chip solid state disk product. Before the single-chip solid state disk product is manufactured, the storage chip needs to be tested to improve product yield. Exemplarily, a chip 200 to be tested is a storage chip (NAND Flash). Figure 3b

[0083] To improve the accuracy of the actual test signal waveform as much as possible and reduce the influence of the external test environment on the actual signal waveform, an interposer 102 is added. The signal to be tested is led out through a test point (e.g., a first interface 1021 shown in FIG. 2B) on the surface of the interposer 102 and then tested. Figure 3b Figure 3b As shown in FIG. 2C, the interposer 102 is a single-layer interposer. Exemplarily, the interposer 102 is taken as a ball grid array package for illustration. The pad layout on the side of the interposer 102 close to the substrate 101 needs to correspond to the packaging solder balls of the substrate 101, and the interposer 102 is electrically connected to the substrate 101 by soldering. The pad layout on the side of the interposer 102 away from the substrate 101 needs to correspond to the packaging solder balls of the chip 200 to be tested, and the chip 200 to be tested is electrically connected to the interposer 102. In this way, the interposer 102 transmits electrical signals between the substrate 101 and the chip 200 to be tested.

[0084] Compared with directly connecting the chip to be tested to the interposer without setting a test fixture, the chip to be tested can shake during testing, which can cause interruption of the test signal. In the embodiment of the present disclosure, a test fixture 103 is used to fix the chip 200 to be tested, so that the chip to be tested is stably connected to the interposer during testing, and the position stability of the chip to be tested is maintained. The structure of the test fixture 103 can have various different shapes. For example, the test fixture 103 can be in the shape of a clamp (as shown in FIG. 2D) to clamp the chip 200 to be tested on both sides of the chip 200 to be tested. The test fixture 103 can also be in the shape of a holder (not shown) provided with a pressing member. The chip 200 to be tested is placed on the holder and pressed by the pressing member. The test fixture 103 can also fix the chip 200 to be tested in other ways, which are not limited in the present disclosure. Figure 3b

[0085] It should be noted that the shape and size of the test fixture 103 are adapted to the shape and size of the chip 200 to be tested. For example, the width of the test fixture 103 needs to be adapted to the width of the chip 200 to be tested, so as to better clamp the chip 200 to be tested on both sides of the chip 200 to be tested. For example, as shown in FIG. 2D, the width of the test fixture 103 is adapted to the width of the chip 200 to be tested. Figure 3a or​​​Figure 3b As shown, the distance between the contact probes 1033 of the test fixture 103 is equal to the width of the chip under test 200, which is the dimension parallel to the surface of the substrate 101.

[0086] Referring to Figure 5 The test fixture 103 includes a first test board 1031 and a second test board 1032, wherein the second test board 1032 is electrically connected to the first test board 1031, the first test board 1031 is electrically connected to the intermediate board 102, and the second test board 1032 is electrically connected to the test equipment 104. In this way, the test output signal of the chip under test 200 is transmitted to the second test board 1032 through the intermediate board 102 and the first test board 1031, forming a test output signal transmission path.

[0087] It should be noted that, referring to Figure 5 The second test board 1032 is located on the side of the first test board 1031 that is relatively far away from the substrate 101, and the test equipment 104 can be connected to the top surface of the second test board 1032 that is relatively far away from the first test board 1031. The second test board 1032 is provided with multiple layers of wiring for signal transmission. The test output signal is transmitted to the top surface of the second test board 1032 through the multiple layers of wiring in the second test board 1032. The top surface has test contacts or test probes that are connected to the test equipment 104. Therefore, the second test board 1032 transmits the test output signal of the chip under test 200 based on the test input signal to the test equipment 104 to realize the test of the chip under test 200. Compared to connecting the test equipment 104 to the side wall of a smaller single-layer intermediate board for testing, there is a problem of less operable space causing difficulty in welding. In the embodiment of the present disclosure, the test equipment 104 is connected to the top of the second test board 1032, which is the side relatively far away from the first test board 1031, and has a larger operating space. The test equipment 104 can be welded in the larger operating space, thereby saving welding time and reducing the probability of welding errors, and ultimately improving the test accuracy of the chip under test.

[0088] It can be understood that, depending on the type of chip under test 200, the test items for the chip under test 200 will also be different. The test items can include radio frequency test, signal stability test, leakage current test, etc. Depending on the different test items, different test equipment can be selected to be connected to the second test board 1032. The test equipment 104 can include an oscilloscope, a logic analyzer, and a voltmeter, etc.

[0089] Exemplarily, the testing device 104 can include a voltmeter, a probe of the voltmeter is welded to a testing contact on the surface of the second testing board 1032, the voltmeter is used to acquire a voltage value or a voltage waveform at the testing contact, and the tested chip 200 is detected for faults according to the acquired voltage value or voltage waveform.

[0090] In the embodiment of the present disclosure, the tested chip is fixed by the testing fixture and the intermediate plate, so as to improve the contact stability of the tested chip. The testing fixture includes a first testing board and a second testing board, the first testing board is electrically connected with the intermediate plate, the second testing board is electrically connected with the first testing board, and the second testing board is located above the first testing board. The testing output signal of the tested chip is transmitted to the second testing board on the top of the testing fixture through the intermediate plate. Therefore, when the testing device is connected to the second testing board on the top of the testing fixture, there is a larger operation space, the operation space for welding the testing device to the testing fixture is increased, thereby saving the welding time and reducing the probability of welding errors, and finally improving the testing accuracy of the tested chip.

[0091] In some embodiments, referring to Figures 3a to 5 The testing fixture 103 further includes a contact probe 1033, the contact probe 1033 penetrates through the first testing board 1031, and one end of the contact probe 1033 is electrically connected with the second testing board 1032; wherein

[0092] After the testing fixture 103 moves towards the intermediate plate 102, the other end of the contact probe 1033 is electrically connected with the intermediate plate 102.

[0093] When the other end of the contact probe 1033 is electrically connected with the intermediate plate 102, the contact probe 1033 is configured to receive the testing output signal transmitted by the intermediate plate 102 and transmit the testing output signal to the second testing board 1032.

[0094] Referring to Figure 3b The testing fixture 103 is in a first position state, the testing fixture 103 is in a disconnected state with the intermediate plate 102, and the tested chip 200 is not tested. Referring to Figure 4 After the testing fixture 103 moves towards the intermediate plate 102, the testing fixture 103 is in a second position state, at this time, the testing fixture 103 is in a connected state with the intermediate plate 102 through the contact probe 1033.

[0095] The contact probe 1033 is arranged on the testing fixture 103, when the testing fixture 103 is in the second position state, the contact probe 1033 is electrically connected with the first interface 1021 on the intermediate plate 102.

[0096] In one example, the contact probe 1033 consists of an electrically connected needle sleeve and a needle core, with the needle sleeve fitted over the outside of the needle core. The needle sleeve can be mounted on the test fixture 103. When the test fixture 103 and the intermediate plate 102 are pressed together, the sidewall of the intermediate plate 102 includes a stamp hole, which includes a conductive ring and a blank center surrounded by the conductive ring. The needle core is pressed into the stamp hole and electrically connected to the conductive ring, thereby realizing the electrical connection between the contact probe 1033 and the first interface 1021 on the intermediate plate 102.

[0097] In another example, the contact probe 1033 consists of an electrically connected needle sleeve and a needle core. The needle sleeve is fitted over the outside of the needle core, and the needle core can elastically expand and contract within the needle sleeve. The needle sleeve can be mounted on the test fixture 103. When the test fixture 103 and the intermediate plate 102 are pressed together, the elastically expanding needle core is pressed onto the first interface 1021 of the intermediate plate 102.

[0098] In this embodiment, the test fixture 103 is provided with contact probes 1033. After the test fixture 103 moves toward the intermediate plate 102, the test fixture 103 is electrically connected to the first interface 1021 on the intermediate plate 102 through the contact probes 1033. The test output signal of the chip under test is transmitted to the test equipment through the intermediate plate and the test fixture. Compared with using connecting cables to connect the test fixture and the intermediate plate or soldering the test fixture and the intermediate plate, this disclosure realizes signal transmission through contact probes, reducing signal interference caused by adding connecting cables, and also reducing losses caused by soldering, ultimately improving the test accuracy of the chip under test.

[0099] In some embodiments, reference Figures 3a to 6 The first test board 1031 includes multiple moving modules 1034, and each moving module 1034 is provided with a contact probe 1033, which penetrates the moving module 1034.

[0100] Intermediate plate 102 includes a first surface parallel to substrate 101, and a first interface 1021 corresponding to contact probe 1033 is provided on the first surface; wherein,

[0101] After the test fixture 103 moves toward the intermediate plate 102, the other end of the contact probe 1033 is electrically connected to the first interface 1021.

[0102] refer to Figure 6 The following description uses the first test board 1031, which includes four moving modules 1034, as an example. Each moving module 1034 is equipped with several contact probes 1033. Figure 6 (Not shown in the image), for example, each moving module 1034 is provided with a contact probe 1033, which penetrates the moving module 1034. Therefore, the position of the contact probe 1033 can change with the position of the moving module 1034.

[0103] For example, such as Figure 6 As shown, moving modules 1034a and 1034c can move along the X direction, and moving modules 1034b and 1034d can move along the Y direction. Therefore, the position of the contact probe 1033 on moving modules 1034a and 1034c moves along the X direction, and the position of the contact probe 1033 on moving modules 1034b and 1034d moves along the Y direction.

[0104] In this embodiment, the first test board 1031 includes multiple moving modules 1034, and contact probes 1033 penetrate through the moving modules 1034. Compared to fixing the modules of the first test board, this disclosure allows the position of the contact probes 1033 to change with the position of the moving modules 1034 by setting the moving modules 1034. When connecting the test fixture 103 and the intermediary board 102, the contact probes 1033 can be adapted to intermediary boards 102 of different sizes, improving the testing diversity of the chip under test.

[0105] In some embodiments, the surface of the first test plate 1031 relative to the substrate 101 includes a first region and a second region surrounding the first region; wherein the moving module 1034 and the contact probe 1033 are located in the second region;

[0106] The first test board 1031 also includes: a spring 1035, one end of the spring 1035 is located at the center of the first region, and the other end of the spring 1035 is fixedly connected to the moving module 1034.

[0107] Spring 1035 is configured to adjust the position of movable module 1034 by telescoping, thereby adjusting the position of contact probe 1033.

[0108] refer to Figure 6 The first test board 1031 includes four moving modules 1034, which are arranged in a circle. One end of the spring 1035 is fixed at the center of the first area, and the other end of the spring 1035 is fixedly connected to the moving modules 1034a, 1034b, 1034c and 1034d respectively.

[0109] It can be understood that, in an example, the position of the moving module 1034 changes with the expansion and contraction of the spring 1035 by manual stretching of the tester, for example, the spring 1035 is arranged on the first test board 1031, and when the spring 1035 is in a stretched state, a certain elastic force can be applied to the moving module 1034. After the test clamp 103 moves towards the intermediate plate 102, the contact probe 1033 connects the test clamp 103 and the intermediate plate 102, and since the moving module 1034 is subjected to a certain elastic force of the spring 1035, the contact probe 1033 penetrating the moving module is also subjected to a certain elastic force, which can further improve the connection stability of the contact probe 1033 and the first interface 1021 of the intermediate plate 102. In another example, the spring stretching can be controlled by a mechanical device to change the position of the moving module 1034 with the expansion and contraction of the spring 1035.

[0110] It should be noted that the first test board 1031 can be provided with other expansion components in addition to the spring, and the present disclosure does not limit this.

[0111] In the embodiments of the present disclosure, the first test board 1031 further comprises the spring 1035, and the present disclosure can not only adjust the position of the moving module 1034 and further adjust the position of the contact probe 1033 by arranging the spring 1035, but also improve the connection stability of the contact probe 1033 and the first interface 1021 of the intermediate plate 102, thereby improving the test accuracy of the to-be-tested chip.

[0112] In some embodiments, the test device 104 comprises an oscilloscope, and the second test board 1032 comprises: a test contact 1036, the test contact 1036 being located on a surface of the second test board 1032 away from the substrate 101; wherein,

[0113] The test contact 1036 is configured to be electrically connected with the oscilloscope and is configured to transmit the test output signal of the to-be-tested chip 200 to the oscilloscope.

[0114] Reference Figure 7 A plurality of test contacts 1036 are arranged on the surface of the second test board 1032 away from the substrate 101, and a plurality of layers of wiring are arranged in the second test board 1032 for signal transmission. The test output signal of the to-be-tested chip 200 can be transmitted to the second test board 1032 through the intermediate plate 102 and the contact probe 1033, and then transmitted to the test contact 1036 on the surface of the second test board 1032 through the wiring in the second test board 1032. The test contact 1036 is electrically connected with the oscilloscope, and the test output signal is transmitted to the oscilloscope. Figure 7 An arrangement mode of the test contact 1036 is shown, and the layout of the test contact 1036 on the surface of the second test board 1032 away from the substrate 101 can also be adjusted according to actual conditions, and the present disclosure does not limit this.

[0115] It can be understood that the oscilloscope receives the test output signal, and the oscilloscope can record the waveform of the test output signal. Exemplarily, the oscilloscope de-embeds the recorded waveform according to the scattering parameter to obtain the test result. The second test board 1032 is provided with a transmission differential line and a calibration differential line. When the second test board 1032 of the embodiment of the present disclosure is used for testing, the scattering parameter (S parameter) of the calibration differential line needs to be measured first. The scattering parameters of the calibration differential line and the transmission differential line are the same. Then, the measured scattering parameter is imported into the oscilloscope during actual testing. The influence of the transmission differential line on the second test board 1032 is reduced by the de-embedding function of the oscilloscope, the accuracy of the test output signal is improved, and finally the accuracy of the test result is improved.

[0116] In some embodiments, the test probe of the oscilloscope is fixedly connected with the test contact 1036.

[0117] In an example, the test probe of the oscilloscope is welded to the test contact 1036 on the surface of the second test board 1032. In another example, the test probe of the oscilloscope is fixedly connected with the test contact 1036 on the surface of the second test board 1032 through a connecting cable.

[0118] In the embodiment of the present disclosure, in order to improve the connection stability of the test probe of the oscilloscope and the test contact 1036, it is preferred that the test probe of the oscilloscope is welded to the test contact 1036 on the surface of the second test board 1032, thereby improving the test accuracy.

[0119] In some embodiments, referring to Figure 4 and Figure 5 , the test device 104 includes a logic analyzer, and the second test board 1032 includes: a test probe 1037, the test probe 1037 being located on a surface of the second test board 1032 away from the substrate 101; wherein,

[0120] The test probe 1037 is electrically connected with the logic analyzer and is configured to transmit the test output signal of the chip under test 200 to the logic analyzer.

[0121] It should be noted that the logic analyzer can include a standalone (or single machine type) logic analyzer and a computer-based logic analyzer. The standalone logic analyzer integrates test software and operation management elements in one instrument, and the computer-based logic analyzer needs to be used together with a computer. The logic analyzer can include a data acquisition unit, a data storage unit, a data forwarding unit and a data processing unit, etc. Therefore, the logic analyzer can perform complex operations and be applied to many complex test occasions.

[0122] In the embodiments of the present disclosure, the test device 104 comprises a logic analyzer, the second test board 1032 comprises test probes 1037, and the probes of the logic analyzer can be directly connected to the test probes 1037 on the top of the second test board 1032, so that when the logic analyzer is tested, the probes of the logic analyzer do not need to be welded, thereby reducing the welding step, saving the test cost, and improving the test efficiency.

[0123] In some embodiments, the intermediate board 102 comprises a second surface parallel to the substrate 101, and a plurality of second interfaces are arranged on the second surface, and a third interface corresponding to the second interface is arranged on the substrate 101; wherein the second interface is electrically connected with the third interface.

[0124] For example, the solid state disk in the ball grid array package is taken as an example for illustration, the pad layout on the intermediate board 102 needs to correspond to the package solder balls of the substrate 101, therefore, the second interface arranged on the intermediate board 102 needs to correspond to the third interface arranged on the substrate 101, so as to facilitate the signal transmission between the intermediate board 102 and the substrate 101 after the electrical connection of the second interface and the third interface.

[0125] For example, a double-ended probe (not shown) is arranged in the intermediate board 102, the upper end of the double-ended probe is connected with the chip to be tested, and the lower end of the double-ended probe is connected with the substrate 101, the double-ended probe is used to connect the pads of the substrate 101 and the pins of the chip to be tested, so as to reduce the loss caused by welding and reduce the signal quality problem caused by poor welding.

[0126] In an example, in order to prevent the introduction of noise and interference to the signal, a filter capacitor can be additionally arranged on the intermediate board 102 for filtering, so as to reduce the loss and distortion of the signal on the intermediate board 102 and improve the integrity of the test signal transmitted by the intermediate board 102.

[0127] Figure 8 For the flowchart of the test method according to the embodiments of the present disclosure, as shown in Figure 8 The present disclosure also provides a test method, which comprises:

[0128] S10: providing a substrate and an intermediate board; wherein the intermediate board is electrically connected with the substrate;

[0129] S20: clamping a chip to be tested by a test clamp;

[0130] S30: moving the test clamp clamping the chip to be tested towards the intermediate board, so as to electrically connect the test clamp with the intermediate board; wherein the test clamp comprises a first test board, the first test board is electrically connected with the intermediate board, the chip to be tested is electrically connected with the intermediate board, and the intermediate board is used to transmit a test input signal between the substrate and the chip to be tested;

[0131] S40: receiving, by the testing device, the test output signal sent by the chip under test based on the test input signal to test the chip under test; wherein the testing device is electrically connected with the second test board, the second test board is electrically connected with the first test board, and the second test board is located above the first test board.

[0132] Reference Figures 3b to 5 To test the chip under test, the intermediate board and the substrate can be electrically connected by welding first, and then the testing fixture holding the chip under test is moved towards the intermediate board by manual operation of the tester or by providing a pressing device (such as a pressing rod) to make the testing fixture electrically connected with the intermediate board, and the testing device is electrically connected with the second test board of the testing fixture by welding, the second test board is electrically connected with the first test board, and the second test board is located above the first test board.

[0133] The second test board is provided with multiple layers of wiring for signal transmission, wherein the second test board is electrically connected with the first test board, the first test board is electrically connected with the intermediate board, and the second test board is electrically connected with the testing device. In this way, the test output signal of the chip under test is transmitted to the second test board on the top of the testing fixture through the intermediate board and the first test board, and then transmitted to the testing device, forming a test output signal transmission path.

[0134] It should be noted that the specific process of the test method in the embodiments of the present disclosure can refer to the above-mentioned embodiments of the test system, which will not be described here.

[0135] In the embodiments of the present disclosure, the intermediate board and the chip under test are fixed by the testing fixture to improve the contact stability of the chip under test. The testing fixture includes a first test board and a second test board, the first test board is electrically connected with the intermediate board, the second test board is electrically connected with the first test board, and the second test board is located above the first test board. The test output signal of the chip under test is transmitted to the second test board on the top of the testing fixture through the intermediate board. Therefore, when the testing device is connected to the second test board on the top of the testing fixture, there is a large operating space, which increases the operating space for welding the testing device to the testing fixture, thereby saving welding time and reducing the probability of welding errors, and finally improving the test accuracy of the chip under test.

[0136] In some embodiments, the testing fixture further includes a contact probe, the contact probe penetrates the first test board, one end of the contact probe is electrically connected with the second test board, and the intermediate board includes a first surface parallel to the substrate, the first surface is provided with a first interface corresponding to the contact probe.

[0137] Moving the testing fixture holding the chip under test towards the intermediate board to make the testing fixture electrically connected with the intermediate board includes:

[0138] A pressure is applied to the test fixture in a direction towards the interposer so as to electrically connect the other end of the contact probe to the first interface.

[0139] In an example, the test fixture can be pressed down manually by a test personnel so as to move the test fixture in a direction towards the interposer to achieve the electrical connection between the test fixture and the interposer.

[0140] In another example, a pressing rod is used to move the test fixture on a side opposite to the substrate and apply a pressure to the test fixture so as to electrically connect the test fixture to the interposer. It is to be noted that the up-and-down movement of the pressing rod can be driven by a pneumatic cylinder to adjust the position of the test fixture. In addition, the up-and-down movement of the pressing rod can also be driven by a motor.

[0141] In the embodiments of the present disclosure, the test fixture is pressed down to achieve the electrical connection between the test fixture and the interposer, and then the chip under test is tested. When the test fixture and the interposer are disconnected, the test of the chip under test is stopped, which can improve the test flexibility of the chip under test.

[0142] In some embodiments, the test method further comprises:

[0143] After the test of the chip under test is completed, the test fixture is disconnected from the test device;

[0144] After the test fixture is disconnected from the test device, the test fixture is controlled to release the fixation of the chip under test.

[0145] It is to be noted that after the substrate, the interposer, the test fixture (including the first test plate and the second test plate), the chip under test and the test device are connected, the substrate needs to be powered on to be in a working state. When the substrate is in the working state, the chip under test is tested.

[0146] After the test of the chip under test is completed, the power supply to the substrate can be stopped. The solder balls connecting the substrate, the interposer, the test fixture (including the first test plate and the second test plate), the chip under test and the test device can be cleaned by a hot air gun, and then disconnected to end the test of the chip under test.

[0147] It is to be noted that those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by a computer program instructing related hardware. The computer program can be stored in a computer readable storage medium, and when the program is executed, the processes of the above-mentioned embodiments can be included.

[0148] Furthermore, in describing representative embodiments, the specification can have presented the method and / or process as a particular sequence of steps. However, to the extent that the method or process depends on any particular order of steps, this description or implementation should not be construed to imply that the steps are carried out in the order described or implied unless expressly so described or implied. Thus, the specific order of steps or sequence of steps in the specification is not to be understood as a limitation on the scope of the embodiments, unless expressly so stated or implied by the specification.

[0149] The above description is only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A test component, characterized in that, The test components include: An intermediate board and a test fixture adapted to the intermediate board; the test fixture includes a first test board configured to fix the chip under test and to realize the electrical connection between the chip under test and the intermediate board during testing; The test fixture also includes a second test board located on top of the first test board and electrically connected to the first test board. The second test board is configured to be electrically connected to the test equipment during testing to perform testing on the chip under test. The test fixture further includes: a contact probe, which penetrates the first test plate and one end of the contact probe is electrically connected to the second test plate; The first test board includes multiple moving modules, each of which is provided with a contact probe that penetrates through the moving module; the position of the contact probe changes with the position of the moving module.

2. The test component according to claim 1, characterized in that, The test fixture is also configured to move toward the intermediary plate when subjected to pressure toward the intermediary plate, so as to achieve electrical connection between the test fixture and the intermediary plate.

3. The test component according to claim 1, characterized in that, The second test board includes a printed circuit board.

4. The test component according to claim 1, characterized in that, The interposer includes a first surface, the first surface including a chip fixing area, and the chip under test is located in the chip fixing area.

5. The test component according to claim 4, characterized in that, The chip under test is fixed to the chip fixing area of ​​the interposer plate by adhesive or welding.

6. A testing system, characterized in that, The testing system includes the testing components as described in any one of claims 1 to 5; and substrate; The interposer is configured to be electrically connected to the substrate and the chip under test during testing, respectively, to transmit test input signals between the substrate and the chip under test.

7. The testing system according to claim 6, characterized in that, The second test board is specifically configured to transmit the test output signal fed back by the chip under test based on the test input signal to the test equipment, so as to realize the test of the chip under test.

8. The testing system according to claim 6, characterized in that, After the test fixture moves toward the intermediate plate, the other end of the contact probe is electrically connected to the intermediate plate; When the other end of the contact probe is electrically connected to the intermediary plate, the contact probe is configured to receive the test output signal of the chip under test transmitted by the intermediary plate and transmit the test output signal to the second test board.

9. The testing system according to claim 6, characterized in that, The intermediate plate includes a first surface parallel to the substrate, and a first interface corresponding to the contact probe is provided on the first surface; wherein... After the test fixture moves toward the intermediate plate, the other end of the contact probe is electrically connected to the first interface.

10. The testing system according to claim 9, characterized in that, The surface of the first test board relatively close to the substrate includes a first region and a second region surrounding the first region; wherein the moving module and the contact probe are located in the second region; The first test board also includes a spring, one end of which is located at the center of the first region, and the other end of which is fixedly connected to the moving module. The spring is configured to adjust the position of the moving module by extending and retracting, thereby adjusting the position of the contact probe.

11. The testing system according to claim 6, characterized in that, The testing equipment includes an oscilloscope, and the second test board includes test contacts located on the surface of the second test board relatively away from the substrate; wherein... The test contact is used to electrically connect to the oscilloscope and is configured to transmit the test output signal of the chip under test to the oscilloscope.

12. The testing system according to claim 11, characterized in that, The test probe of the oscilloscope is fixedly connected to the test contact.

13. The testing system according to claim 6, characterized in that, The testing equipment includes a logic analyzer, and the second test board includes test probes located on a surface of the second test board relatively far from the substrate; wherein... The test probe is electrically connected to the logic analyzer and is configured to transmit the test output signal of the chip under test to the logic analyzer.

14. The testing system according to claim 6, characterized in that, The intermediate plate includes a second surface parallel to the substrate, and a plurality of second interfaces are provided on the second surface. The substrate is provided with a third interface corresponding to the second interface; wherein the second interface and the third interface are electrically connected.

15. A testing method, characterized in that, include: A substrate and an interposer are provided; wherein the interposer is electrically connected to the substrate; The chip under test is held in place by a test fixture; The test fixture holding the chip under test is moved toward the interposer plate to make the test fixture electrically connected to the interposer plate; wherein, the test fixture includes a first test plate, the first test plate is electrically connected to the interposer plate, the chip under test is electrically connected to the interposer plate, and the interposer plate is used to transmit test input signals between the substrate and the chip under test; The test fixture further includes: a contact probe and a second test plate, wherein the contact probe passes through the first test plate, one end of the contact probe is electrically connected to the second test plate, and the other end of the contact probe is electrically connected to the intermediate plate; The first test board includes multiple moving modules, each of which is provided with a contact probe that penetrates the moving module; the position of the contact probe changes with the position of the moving module. The test equipment receives the test output signal sent by the chip under test based on the test input signal to test the chip under test; wherein the test equipment is electrically connected to a second test board, the second test board is electrically connected to a first test board, and the second test board is located on top of the first test board.

16. The test method according to claim 15, characterized in that, The intermediate plate includes a first surface parallel to the substrate, and a first interface corresponding to the contact probe is provided on the first surface; Moving the test fixture holding the chip under test toward the interposer to electrically connect the test fixture to the interposer includes: Pressure is applied to the test fixture toward the intermediate plate so that the other end of the contact probe is electrically connected to the first interface.

17. The test method according to claim 15, characterized in that, The testing method also includes: After the testing of the chip under test is completed, disconnect the test fixture from the test equipment; After disconnecting the test fixture from the test equipment, control the test fixture to release its fixation on the chip under test.

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