A reaction gas processing method and a wafer etching system for wafer etching

Abstract

The application provides a reaction gas processing method for wafer etching, comprising: providing a plurality of wafer groups, wherein each of the plurality of wafer groups comprises a first wafer and a second wafer adjacent to each other when entering an etching chamber; performing a reaction gas processing step on each of the plurality of wafer groups, the reaction gas processing step comprising: etching the first wafer with an etching gas in the etching chamber; placing the etched first wafer in a first slot of a processing chamber; etching the second wafer with the etching gas in the etching chamber; moving the first wafer in the first slot to a second slot of the processing chamber, wherein the first slot is above the second slot; placing the etched second wafer in the first slot of the processing chamber; and performing a cleaning process on the second wafer and the first wafer. The reaction gas processing method for wafer etching can avoid HBr·2H2O crystallization on the surface of the etched wafer without contaminating the wafer.

Description

Technical Field

[0001] This application relates to the field of wafer etching technology, and in particular to a reactive gas processing method and a wafer etching system for wafer etching. Background Technology

[0002] Semiconductor etching technology is a crucial step in semiconductor manufacturing, microelectronics manufacturing, and micro / nanoscale manufacturing processes. It can be further divided into wet etching and dry etching. Among these, dry etching provides better precision for circuit patterns and is therefore increasingly widely used.

[0003] In semiconductor manufacturing, HBr is often used as the primary etching gas in dry etching processes, such as during the etching of single-crystal silicon to prepare shallow trench insulation (STI) or during the etching of polycrystalline silicon to prepare gate electrodes. After etching, HBr residue is easily left on the wafer surface. Moreover, due to the properties of HBr, after volatilization, HBr combines with moisture to form HBr•2H2O crystals. These HBr•2H2O crystals adhere to the wafer surface, causing contamination and defects in subsequent processes. Summary of the Invention

[0004] Based on the foregoing, this application provides a reactive gas treatment method and a wafer etching system for wafer etching to improve the problem of wafer cross-contamination.

[0005] To achieve the above objectives, this application provides a reactive gas processing method for wafer etching, comprising: providing multiple wafer groups, wherein each of the multiple wafer groups includes a first wafer and a second wafer that are adjacent to each other when entering an etching chamber; performing a reactive gas processing step on each of the multiple wafer groups, the reactive gas processing step including: etching the first wafer with an etching gas in an etching chamber; placing the etched first wafer in a first slot of the processing chamber; etching the second wafer with an etching gas in the etching chamber; moving the first wafer located in the first slot to a second slot of the processing chamber, wherein the first slot is located above the second slot; placing the etched second wafer in the first slot of the processing chamber; and performing a cleaning process on the second wafer and the first wafer.

[0006] In an embodiment of this application, the reactive gas processing method for wafer etching further includes: placing multiple sets of wafers in a wafer placement box, wherein a first wafer is located in a first placement area of ​​the wafer placement box, a second wafer is located in a second placement area of ​​the wafer placement box, and the first placement area is disposed on the second placement area.

[0007] In the embodiments of this application, the processing cavity is a wafer transfer box.

[0008] In embodiments of this application, a plurality of spacers are provided in the processing cavity to create first slots and second slots for placing multiple wafer sets within the processing cavity.

[0009] In an embodiment of this application, the cleaning process includes: removing surface residues from the first wafer and the second wafer with nitrogen gas and venting the nitrogen gas.

[0010] In embodiments of this application, the cleaning process includes: removing surface residues from the first wafer and the second wafer with inert gas and venting the inert gas.

[0011] To achieve the above objectives, this application provides a wafer etching system, including an etching chamber, a processing chamber, an inlet pipe, and an exhaust pipe. The etching chamber is used to etch multiple wafer sets using etching gas, each wafer set comprising a first wafer and a second wafer that are adjacent to each other upon entering the etching chamber, with the etching time of the first wafer preceding that of the second wafer. The processing chamber includes a first slot and a second slot, the first slot being located on the second slot, the first slot housing the second wafer, and the second slot housing the first wafer. The inlet pipe is connected to the processing chamber and is used to introduce nitrogen or an inert gas to remove surface residues from the multiple wafer sets. The exhaust pipe is connected to the processing chamber and is used to exhaust nitrogen or an inert gas.

[0012] In embodiments of this application, the wafer etching system further includes a wafer placement box, which holds multiple wafer groups, wherein a first wafer is located in a first placement area of ​​the wafer placement box, and a second wafer is located in a second placement area of ​​the wafer placement box, with the first placement area disposed on the second placement area.

[0013] In the embodiments of this application, the processing cavity is a wafer transfer box.

[0014] In embodiments of this application, a plurality of spacers are provided in the processing cavity to create first slots and second slots for placing multiple wafer sets within the processing cavity.

[0015] In summary, the reactive gas processing method and wafer etching system of this application, by adjusting the order in which the etched wafers are placed in the processing chamber, change the direction of the gas flow generated by the thermal effect of HBr within the processing chamber. This prevents HBr•2H2O crystals from forming on the surface of the etched wafers, thus avoiding wafer contamination. Furthermore, without adding additional hardware, it effectively improves defects caused by HBr sublimation, saving costs and increasing wafer yield.

[0016] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, the following describes the application in detail with reference to the preferred embodiments and accompanying drawings. Attached Figure Description

[0017] Figure 1 A block diagram of a wafer etching system is shown according to an embodiment of this application.

[0018] Figure 2 A configuration diagram of the processing cavity is shown according to an embodiment of this application.

[0019] Figure 3 A block diagram of a wafer etching system is shown according to another embodiment of this application.

[0020] Figure 4 A flowchart illustrating a reactive gas processing method for wafer etching according to an embodiment of this application is provided.

[0021] Figure 5 This is a wafer surface diagram without utilizing the reactive gas processing method for wafer etching described in this application.

[0022] Figure 6 A wafer surface diagram of the reactive gas processing method for wafer etching according to this application.

[0023] Explanation of the labels in the diagram:

[0024] 10: Etching cavity

[0025] 20: Processing the cavity

[0026] 30: Intake pipe

[0027] 31: Spacer

[0028] 40: Exhaust pipe

[0029] 50: Wafer Placement Box

[0030] WF1~WFM: Wafer

[0031] SLT1~SLTN: Slots

[0032] S11~S18: Steps Detailed Implementation

[0033] The following specific embodiments illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification.

[0034] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The present application will now be described in detail with reference to the accompanying drawings and embodiments. To enable those skilled in the art to better understand the solutions of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this application.

[0035] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or devices.

[0036] Please see Figure 1 and Figure 2 This is a block diagram illustrating a wafer etching system according to an embodiment of the present application and a configuration diagram illustrating a processing cavity according to an embodiment of the present application. Figure 1 and Figure 2 As shown, the wafer etching system 1A includes an etching chamber 10, a processing chamber 20, an inlet pipe 30, and an exhaust pipe 40. The etching chamber 10 is used to etch multiple wafers WF1 to WFM using etching gas. The processing chamber 20 includes multiple slots SLT1 to SLTN for holding the multiple wafers WF1 to WFM. The inlet pipe 30 is connected to the processing chamber 20 and is used to introduce nitrogen or inert gas to remove surface residues from the multiple wafers WF1 to WFM. The exhaust pipe 40 is connected to the processing chamber 20 and is used to exhaust nitrogen or inert gas.

[0037] Multiple wafers WF1 to WFM form multiple wafer groups. Each wafer group includes a first wafer and a second wafer that are adjacent to each other when entering the etching cavity 10. The etching time of the first wafer is earlier than that of the second wafer. The second wafer of one of the multiple wafer groups serves as the first wafer of another multiple wafer group. For example, the number of multiple wafers WF1 to WFM is three, and they include wafers WF1, WF2, and WF3 in sequence according to the time they enter the etching cavity 10. Wafers WF1 and WF2 form the first wafer group, and wafers WF2 and WF3 form the second wafer group. Wafer WF1 is the first wafer of the first wafer group, wafer WF2 is the second wafer of the first wafer group and the first wafer of the second wafer group, and wafer WF3 is the second wafer of the second wafer group. The etching gas may include HBr, Cl2 or SF6, and of course, other gases used for etching wafers may also be used, without being limited to the scope listed in this application.

[0038] In this embodiment, the processing cavity 20 can be a wafer transfer box and has multiple spacers 21 inside. The multiple spacers 21 space out multiple slots SLT1~SLTN in the processing cavity 20 for placing multiple wafer sets. For example, the processing cavity 20 consists of a bottom plate, a top plate, and two side plates. The two side plates are adjacent to opposite sides of the bottom plate and opposite sides of the top plate, respectively. The bottom plate, top plate, and two side plates form an accommodating space. The multiple spacers 21 are distributed on the two side plates. Two spacers 21 space out one slot with the bottom plate, two spacers 21 space out one slot with the top plate, and four spacers 21 space out one slot. One of the multiple slots SLT1~SLTN serves as the first slot, and the remaining slots SLT1~SLTN serve as the second slots. For example, slot STLN serves as the first slot, and slots STL(N-1) to SLT1 serve as the second slots; that is, the slot closest to the top plate serves as the first slot. It should be noted that the first slot and the second slot are only distinguished by category, not by the number of slots.

[0039] Please see Figure 3 This is a block diagram illustrating a wafer etching system according to another embodiment of this application. Figure 3 As shown, the wafer etching system 1B includes an etching chamber 10, a processing chamber 20, an air inlet pipe 30, an exhaust pipe 40, and a wafer placement box 50. The configuration of the etching chamber 10, the processing chamber 20, the air inlet pipe 30, and the exhaust pipe 40 is as follows: Figure 1 The embodiments shown have the same configuration, and will not be described again here.

[0040] In this embodiment, the wafer placement box 50 is adjacent to the etching cavity 10 and includes a first placement area and a second placement area. The first placement area includes a single receiving slot to accommodate a first wafer, and the second placement area includes multiple receiving slots to accommodate multiple second wafers.

[0041] Please see Figure 4 This is a flowchart illustrating a reactive gas treatment method for wafer etching according to an embodiment of this application. Figure 4 As shown, the reactive gas treatment method for wafer etching includes steps S11 to S17. Figure 4 The reactive gas treatment method shown for wafer etching is applicable to Figure 1 and Figure 2 The wafer etching systems 1A and 1B are shown, but are not limited to them. The following examples illustrate... Figure 1 The wafer etching system 1A shown illustrates steps S11 to S18.

[0042] Step S11: Provide multiple wafer sets, each of which includes a first wafer and a second wafer that are adjacent to each other when entering the etching cavity. For example, there are two wafer sets, namely a first wafer set and a second wafer set. The first wafer set and the second wafer set each include a first wafer and a second wafer. The first wafer set and the second wafer set are wafer WF1 and wafer WF2, respectively, and the first wafer set and the second wafer set are wafer WF2 and wafer WF3, respectively. The first wafer set and the second wafer set enter the etching cavity 10 for etching, respectively, with the first wafer set entering the etching cavity 10 earlier than the second wafer set; in other words, the etching time of the first wafer set is earlier than the etching time of the second wafer set.

[0043] Accordingly, the processing cavity 20 includes three slots STL1~STL3, with slot STL3 serving as the first slot, and slots STL2 and STL1 serving as two second slots. Slot STL3 is located on slot STL2, and slot STL2 is located on slot STL1.

[0044] Step S12: Perform a reactive gas treatment step on each of the multiple wafer groups. Specifically, the first wafer group is treated with a reactive gas first, followed by the second wafer group. That is, steps S13 to S17 are performed on the first wafer group first, and then steps S13 to S17 are performed on the second wafer group.

[0045] Step S13: Within the etching chamber 10, the first wafer of the first wafer group is etched using etching gas. Specifically, wafer WF1 is etched using etching gas within the etching chamber 10.

[0046] Step S14: Place the etched first wafer of the first wafer group into the first slot of the processing cavity 20. Specifically, place the etched wafer WF1 into slot STL3 of the processing cavity 20.

[0047] Step S15: Within the etching chamber 10, the second wafer of the first wafer group is etched using etching gas. Specifically, wafer WF2 is etched using etching gas within the etching chamber 10.

[0048] Step S16: Move the first wafer in the first wafer group located in the first slot to the second slot of the processing cavity 20, wherein the first slot is located above the second slot. Specifically, move the wafer WF1 located in slot STL3 to slot STL2 of the processing cavity 20.

[0049] Step S17: Place the etched second wafer of the first wafer group into the first slot of the processing cavity 20. Specifically, place the etched wafer WF2 into slot STL3 of the processing cavity 20. Since wafer WF2 also serves as the first wafer of the second wafer group, the first wafer of the second wafer group is also etched. Then return to step S15 to perform the reactive gas treatment step on the second wafer of the second wafer group.

[0050] Step S15: Within the etching chamber 10, the second wafer of the second wafer group is etched using etching gas. Specifically, wafer WF3 is etched using etching gas within the etching chamber 10.

[0051] Step S16: Move the first wafer in the second wafer group located in the first slot to the second slot of the processing cavity 20, wherein the first slot is located above the second slot. Specifically, move the wafer WF1 located in slot STL2 to slot STL1 of the processing cavity 20, and then move the wafer WF2 located in slot STL3 to slot STL2 of the processing cavity 20.

[0052] Step S17: Place the second wafer of the etched second wafer group into the first slot of the processing cavity 20. Specifically, place the etched wafer WF3 into slot STL3 of the processing cavity 20.

[0053] Step S18: Perform a cleaning process on the second wafer and the first wafer. Specifically, perform a cleaning process on wafers WF1 to WF3. In one embodiment, the cleaning process includes: introducing nitrogen gas from the inlet pipe 30 into the processing chamber 20 to remove surface residues from wafers WF1 to WF3, and discharging the nitrogen gas from the exhaust pipe 40. In another embodiment, the cleaning process includes: introducing an inert gas (e.g., helium) from the inlet pipe 30 into the processing chamber 20 to remove surface residues from wafers WF1 to WF3, and discharging the inert gas from the exhaust pipe 40.

[0054] In another embodiment, the reactive gas treatment method for wafer etching of this application may further include:

[0055] Multiple wafer assemblies are placed in a wafer placement box 50, where a first wafer is located in a first placement area of ​​the wafer placement box 50, and a second wafer is located in a second placement area of ​​the wafer placement box 50. The first placement area is located on the second placement area. Specifically, the first wafer of the wafer assembly that is etched first is placed in a receiving slot in the first placement area, and the remaining wafer assemblies are placed in multiple receiving slots in the second placement area. For example, wafer WF1 is placed in a receiving slot in the first placement area, and wafers WF2 and WF3 are placed in two receiving slots in the second placement area.

[0056] Please see Figure 5 and Figure 6 The images show wafer surface views without and with the reactive gas processing method for wafer etching described in this application. Figure 5 As shown, taking the etched wafer WF1 as an example, the etched wafer WF1 still has many wafer defects caused by the etching gas (such as... Figure 5 (The black dots shown). Figure 6 As shown, taking the etched wafer WF1 as an example, after the etched wafer WF1 undergoes the reactive gas treatment method for wafer etching of this application, wafer defects (such as...) are reduced. Figure 6 The number of black dots shown has decreased significantly.

[0057] In summary, the reactive gas processing method and wafer etching system of this application, by adjusting the order in which the etched wafers are placed in the processing chamber, change the direction of the gas flow generated by the thermal effect of HBr within the processing chamber. This prevents HBr•2H2O crystals from forming on the surface of the etched wafers, thus avoiding wafer contamination. Furthermore, without adding additional hardware, it effectively improves defects caused by HBr sublimation, saving costs and increasing wafer yield.

Claims

1. A method for treating reactive gases for wafer etching, characterized in that, include: Multiple wafer sets are provided, each of which includes a first wafer and a second wafer that are adjacent to each other when entering the etching cavity (10). as well as A reactive gas processing step is performed on each of the multiple wafer groups, the reactive gas processing step including: The first wafer is etched in the etching chamber (10) with an etching gas, wherein the etching gas includes HBr; The etched first wafer is placed in the first slot of the processing cavity (20); The second wafer is etched in the etching cavity (10) using the etching gas; Move the first wafer located in the first slot to the second slot of the processing cavity (20), wherein the first slot is located above the second slot; Place the etched second wafer into the first slot of the processing cavity (20); and A cleaning process is performed on the second wafer and the first wafer.

2. The reactive gas treatment method for wafer etching as described in claim 1, further comprising: Multiple wafer sets are placed in a wafer placement box (50), wherein the first wafer is located in a first placement area of ​​the wafer placement box (50), the second wafer is located in a second placement area of ​​the wafer placement box (50), and the first placement area is disposed on the second placement area.

3. The reactive gas processing method for wafer etching as described in claim 1, wherein the processing chamber (20) is a wafer transfer box.

4. The reactive gas processing method for wafer etching as claimed in claim 1, wherein the processing chamber (20) is provided with a plurality of spacers (21) to space out the first slot and the second slot for placing the plurality of wafer sets within the processing chamber (20).

5. The reactive gas treatment method for wafer etching as described in claim 1, wherein the cleaning step includes: Nitrogen gas is used to remove surface residues from the first and second wafers and to vent nitrogen gas.

6. The reactive gas treatment method for wafer etching as described in claim 1, wherein the cleaning step includes: The surface residues of the first and second wafers are removed with an inert gas, and the inert gas is then discharged.

7. A wafer etching system, characterized in that, include: An etching chamber (10) is used to etch multiple wafer groups through an etching gas, wherein each of the multiple wafer groups includes a first wafer and a second wafer that are adjacent to each other when entering the etching chamber, the etching time point of the first wafer is earlier than the etching time point of the second wafer, and the etching gas includes HBr. The processing cavity (20) includes a first slot and a second slot, the first slot being located on the second slot, the first slot holding the second wafer, and the second slot holding the first wafer; An air inlet pipe (30) is connected to the processing chamber (20) and is used to introduce nitrogen or inert gas to remove surface residues from the multiple wafer sets. as well as An exhaust pipe (40) is connected to the processing chamber (20) and is used to exhaust the nitrogen or the inert gas.

8. The wafer etching system of claim 7 further includes a wafer placement box (50) for placing the plurality of wafer groups, wherein the first wafer is located in a first placement area of ​​the wafer placement box (50), the second wafer is located in a second placement area of ​​the wafer placement box (50), and the first placement area is disposed on the second placement area.

9. The wafer etching system of claim 7, wherein the processing chamber (20) is a wafer transport box.

10. The wafer etching system of claim 7, wherein the processing cavity (20) is provided with a plurality of spacers (21) to space out the first slot and the second slot for placing the plurality of wafer sets within the processing cavity (20).

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