A method, apparatus and storage medium for setting a reference clock frequency

Abstract

This application discloses a reference clock frequency setting method, apparatus, and storage medium, relating to the field of electronic engineering technology. It reduces the time required for high-speed transceivers to set the reference clock frequency, improving communication efficiency. Applied to a high-speed transceiver connected to a control unit, the method includes: receiving multiple first clock signals transmitted by a transmitting end to recover a clock frequency response (CDR) sequence; sampling the multiple first CDR sequences to obtain multiple first CDR sample sequences; calculating a first reference clock frequency for the transmitting end based on the multiple first CDR sample sequences; wherein the first reference clock frequency is the transmission frequency of the multiple first CDR sequences; and generating a first locking signal; wherein the first locking signal indicates locking the first reference clock frequency and, upon detection of the first locking signal by the control unit, sets the reference clock frequency of the high-speed transceiver to the first reference clock frequency.

Description

Technical Field

[0001] This application relates to the field of electronic engineering technology, and in particular to a reference clock frequency setting method, apparatus and storage medium. Background Technology

[0002] Field-programmable gate arrays (FPGAs) are a type of semi-custom circuit within application-specific integrated circuits (ASICs), and are programmable logic arrays. For FPGA high-speed transceiver reference clock frequency modulation techniques, traditional methods require continuously changing the clock frequency of the FPGA's clock unit to ensure the high-speed transceiver's reference clock frequency differs from the transmitter's reference clock frequency within a certain range. This method involves the clock unit determining a clock frequency by approaching the transmitter's reference clock frequency each time. This clock unit then inputs this clock frequency as the reference clock frequency into the high-speed transceiver. At this point, the high-speed transceiver's internal clock data recovery (CDR) unit locks this reference clock frequency. The FPGA then detects the bit error rate (BER) of the received signal. If the BER is low, the clock frequency is considered a suitable reference clock frequency; if the BER is high, the clock frequency is considered unsuitable, and the CDR-locked clock frequency is reset to re-establish a new clock frequency. Since the reference clock frequency at the transmitting end is uncertain, sometimes the reference clock frequency of the high-speed transceiver differs from the reference clock frequency at the transmitting end by tens of thousands of offsets per million units (PPM). In this case, the method often needs to change the frequency of the clock unit multiple times to determine the reference clock frequency suitable for the high-speed transceiver, which takes a long time and results in low communication efficiency. Summary of the Invention

[0003] This application provides a reference clock frequency setting method, apparatus, and storage medium, which can reduce the time required for high-speed transceivers to set the reference clock frequency and improve communication efficiency.

[0004] To achieve the above technical objectives, this application adopts the following technical solution:

[0005] In a first aspect, embodiments of this application provide a reference clock frequency setting method applied to a high-speed transceiver connected to a control unit. The method includes: receiving multiple first clock signals transmitted by a transmitting end to recover a clock response sequence (CDR); wherein the first CDR sequence is a transition sequence; sampling the multiple first CDR sequences to obtain multiple first CDR sampling sequences; wherein the first CDR sequence corresponds one-to-one with the first CDR sampling sequence; calculating a first reference clock frequency of the transmitting end based on the multiple first CDR sampling sequences; wherein the first reference clock frequency is the transmission frequency of the multiple first CDR sequences; generating a first locking signal; wherein the first locking signal is used to indicate locking the first reference clock frequency, and is used by the control unit to set the reference clock frequency of the high-speed transceiver to the first reference clock frequency after detecting the first locking signal.

[0006] Understandably, this method receives the CDR sequence sent by the transmitter and samples the CDR sequence. It then quickly calculates the reference clock frequency of the transmitter using the sampled CDR sequence. This method reduces the time required to determine the reference clock frequency of the high-speed transceiver and improves communication efficiency.

[0007] In one possible implementation, after setting the reference clock frequency of the high-speed transceiver to the first reference clock frequency, the method further includes: receiving multiple second CDR sequences; wherein the second CDR sequences are transition sequences; when it is determined that the first reference clock frequency is out of lock based on the multiple second CDR sequences, calculating the second reference clock frequency of the transmitting end; wherein the out-of-lock condition is used to characterize that the difference between the reference clock frequency of the transmitting end and the reference clock frequency of the high-speed transceiver is greater than a preset difference; the high-speed transceiver generates a second locking signal; wherein the second locking signal is used to indicate locking the second reference clock frequency, and is used by the control unit to set the reference clock frequency of the high-speed transceiver to the second reference clock frequency after detecting the second locking signal.

[0008] Understandably, to avoid the high-speed transceiver losing lock during subsequent communication, the high-speed transceiver can receive and analyze the second CDR sequence to determine if it has lost lock. If it has, it can recalculate the transmitter's reference clock frequency based on the second CDR sequence and relock the high-speed transceiver to the transmitter's reference clock frequency. This method can detect changes in the transmitter's reference clock frequency through the CDR sequence, and the high-speed transceiver can quickly lock onto the transmitter's reference clock frequency each time a change occurs.

[0009] In another possible implementation, the first reference clock frequency is determined to be out of lock when the bit error rate of multiple second CDR sequences exceeds a preset value.

[0010] Understandably, by judging the bit error rate of multiple second CDR sequences, it is possible to quickly determine whether the first reference clock frequency of the high-speed transceiver has lost lock, thus improving the judgment efficiency.

[0011] In another possible implementation, after adjusting the reference clock frequency of the high-speed transceiver to the first reference clock frequency, the method further includes: receiving multiple second CDR sequences; wherein the second CDR sequences are transition sequences; calculating the second reference clock frequency of the transmitting end based on the multiple second CDR sequences; generating a second locking signal when the difference between the first reference clock frequency and the second reference clock frequency is greater than a preset difference; wherein the second locking signal is used to indicate locking the second reference clock frequency, and is used by the control unit to set the reference clock frequency of the high-speed transceiver to the second reference clock frequency after detecting the second locking signal.

[0012] Understandably, this method calculates the transmitter's reference clock frequency using multiple second CDR sequences. This method can more accurately determine whether the high-speed transceiver's first reference clock frequency has lost lock, and if so, it can quickly relock. This method is more efficient in the relocking process.

[0013] In another possible implementation, the first reference clock frequency of the transmitting end is calculated based on multiple first CDR sampling sequences, including: obtaining the number of first CDR sequences among the multiple first CDR sequences based on the number of transitions of one first CDR sequence and the total number of transitions of the multiple first CDR sequences; wherein the total number of transitions of the multiple first CDR sequences is the same as the total number of transitions of the multiple first CDR sampling sequences; and calculating the first reference clock frequency of the transmitting end based on the number of multiple first CDR sequences and the time of receiving the multiple first CDR sequences.

[0014] In another possible implementation, the above-mentioned method of obtaining the number of first CDR sequences among multiple first CDR sequences based on the number of transitions of a first CDR sequence and the total number of transitions of multiple first CDR sequences includes: dividing the total number of transitions of multiple first CDR sequences by the number of transitions of a single first CDR sequence to obtain the number of first CDR sequences among multiple first CDR sequences; the above-mentioned method of calculating the first reference clock frequency of the transmitting end based on the number of multiple first CDR sequences and the time of receiving multiple first CDR sequences includes: dividing the number of first CDR sequences among multiple first CDR sequences by the time of receiving multiple first CDR sequences to obtain the first reference clock frequency of the transmitting end.

[0015] Understandably, this method can quickly calculate the transmission frequency of the CDR sequence sent by the transmitter using multiple first CDR sampling sequences, and the transmission frequency is the first reference clock frequency.

[0016] In another possible implementation, sampling multiple first CDR sequences includes upsampling multiple first CDR sequences based on a preset sampling frequency.

[0017] Understandably, upsampling multiple first CDR sequences can improve sampling accuracy and avoid missed sampling due to low sampling frequency.

[0018] Secondly, embodiments of this application provide a processing apparatus such as an FPGA, including a high-speed transceiver and a control unit, wherein the high-speed transceiver is applied to various modules of the reference clock frequency setting method of the first aspect or any possible design scheme in the first aspect.

[0019] Thirdly, embodiments of this application provide a high-speed transceiver, which includes various modules of a reference clock frequency setting method applied to the first aspect or any possible design scheme in the first aspect.

[0020] Fourthly, embodiments of this application provide a high-speed transceiver, including a memory and a processor. The memory and the processor are coupled; the memory stores computer program code, which includes computer instructions. When the processor executes the computer instructions, it causes the high-speed transceiver to perform a reference clock frequency setting method as described in the first aspect and any of its possible design embodiments.

[0021] Fifthly, this application provides a computer-readable storage medium including computer instructions. When executed on a high-speed transceiver, the computer instructions cause the high-speed transceiver to perform a reference clock frequency setting method as described in the first aspect and any of its possible design embodiments.

[0022] Sixthly, this application provides a computer program product including computer instructions. When the computer instructions are executed on a high-speed transceiver, they cause the high-speed transceiver to perform a reference clock frequency setting method as described in the first aspect and any of its possible design embodiments.

[0023] For a detailed description of aspects two through six and their various implementations in this application, please refer to the detailed description in aspect one and its various implementations; and for a detailed description of the beneficial effects of aspects two through five and their various implementations, please refer to the beneficial effect analysis in aspect one and its various implementations, which will not be repeated here.

[0024] These or other aspects of this application will become more readily apparent in the following description. Attached Figure Description

[0025] Figure 1An implementation environment diagram of a reference clock frequency setting method provided in this application embodiment;

[0026] Figure 2 An implementation environment diagram for another reference clock frequency setting method provided in this application embodiment;

[0027] Figure 3 A flowchart illustrating a reference clock frequency setting method provided in this application embodiment;

[0028] Figure 4 This application provides a schematic diagram of sequence transmission and sampling in an embodiment.

[0029] Figure 5 A flowchart of a reference clock frequency pulling method provided in an embodiment of this application;

[0030] Figure 6 Flowchart of another high-speed transceiver reference clock frequency pulling method provided in the embodiments of this application;

[0031] Figure 7 This is a schematic diagram of the structure of a high-speed transceiver provided in an embodiment of this application. Detailed Implementation

[0032] Hereinafter, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," or "third," etc., may explicitly or implicitly include one or more of that feature.

[0033] Field-programmable gate arrays (FPGAs) are a type of semi-custom circuit within application-specific integrated circuits (ASICs), and are programmable logic arrays. For FPGA high-speed transceiver reference clock frequency modulation techniques, traditional methods require continuously changing the clock frequency of the FPGA's clock unit to ensure the high-speed transceiver's reference clock frequency differs from the transmitter's reference clock frequency within a certain range. This method involves the clock unit determining a clock frequency by approaching the transmitter's reference clock frequency each time. This clock unit then inputs this clock frequency as the reference clock frequency into the high-speed transceiver. At this point, the high-speed transceiver's internal clock data recovery (CDR) unit locks this reference clock frequency. The FPGA then detects the bit error rate (BER) of the received signal. If the BER is low, the clock frequency is considered a suitable reference clock frequency; if the BER is high, the clock frequency is considered unsuitable, and the CDR-locked clock frequency is reset to re-establish a new clock frequency. Since the reference clock frequency at the transmitting end is uncertain, sometimes the reference clock frequency of the high-speed transceiver differs from the reference clock frequency at the transmitting end by tens of thousands of offsets per million units (PPM). In this case, the method often needs to change the frequency of the clock unit multiple times to determine the reference clock frequency suitable for the high-speed transceiver, which takes a long time and results in low communication efficiency.

[0034] Based on this, this application proposes a reference clock frequency setting method, which is applied to a high-speed transceiver connected to a control unit. In this method, the high-speed transceiver first receives multiple CDR sequences sent by the transmitting end, obtains multiple CDR sample sequences by sampling these sequences, calculates the reference clock frequency of the transmitting end based on the sample sequences, and generates a locking signal. Finally, the control unit sets the reference clock frequency of the high-speed transceiver to the reference clock frequency of the transmitting end based on the locking signal. It can be understood that this method quickly calculates the reference clock frequency of the transmitting end by receiving the CDR sequences sent by the transmitting end, reducing the time required to determine the reference clock frequency of the high-speed transceiver and improving communication efficiency.

[0035] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0036] Please refer to Figure 1 , Figure 1 This is a diagram illustrating an implementation environment for a reference clock frequency setting method provided in this application. The implementation environment is applied to an FPGA 100, which includes a high-speed transceiver 110, a control unit 120, and a clock unit 130 (optional).

[0037] The high-speed transceiver 110 is used to receive the CDR sequence sent by the transmitter. The high-speed transceiver 110 includes a CDR unit and a frequency calculation unit. The CDR unit can be used to sample the CDR sequence. The frequency calculation unit calculates the reference clock frequency of the transmitter based on the CDR sampled sequence, and then the CDR unit generates a lock signal.

[0038] The control unit 120 is used to detect the lock signal generated by the high-speed transceiver 110 and control the clock unit 130 to set the reference clock frequency of the high-speed transceiver 110.

[0039] Clock unit 130 is used to provide a reference clock frequency for high-speed transceiver 110.

[0040] The high-speed transceiver 110 and control unit 120 are located inside the FPGA 100, while the clock unit 130 can be located inside or outside the FPGA 100. Figure 2 As shown, Figure 2 This is an implementation environment diagram for another reference clock frequency setting method provided in this application embodiment. The location of the clock unit 130 is not limited in this application embodiment.

[0041] Please refer to Figure 3 This is a flowchart illustrating a reference clock frequency setting method provided in an embodiment of this application, applied to a high-speed transceiver, which is connected to a control unit. Figure 3 As shown, the method may include S101-S106.

[0042] S101: The transmitter sends multiple first CDR sequences to the high-speed transceiver. Correspondingly, the high-speed transceiver receives the multiple first CDR sequences sent by the transmitter. The first CDR sequences are transition sequences.

[0043] A jump series is a sequence of numbers that contains digits representing at least two voltage levels. It is understood that this sequence represents the transition relationship between these two voltage levels; hence, it is called a jump series. For example, a jump series could be 01010101, where "0" represents a low voltage level and "1" represents a high voltage level. When adjacent digits are "01", it indicates a transition from a low voltage level to a high voltage level; when adjacent digits are "10", it indicates a transition from a high voltage level to a low voltage level.

[0044] Multiple first CDR sequences are a series of sequences containing rich 01 transitions sent by the transmitting end, such as: 01010101, or 00110011, etc.

[0045] The first CDR sequence is parallel data, which is sent to the high-speed transceiver via serialization by the transmitter, and received by the high-speed transceiver via serialization. The line rate at which the transmitter serializes the CDR is a predefined value.

[0046] Before the transmitter and the high-speed transceiver establish communication based on a standard communication protocol (such as PCIE or Vbyone protocol) or a custom communication protocol, there is a handshake process. During this handshake process, the transmitter can send a CDR sequence to the high-speed transceiver.

[0047] S102: The high-speed transceiver samples multiple first CDR sequences to obtain multiple first CDR sample sequences. Each first CDR sequence corresponds one-to-one with a first CDR sample sequence.

[0048] The high-speed transceiver upsamples multiple first CDR sequences based on a preset sampling frequency.

[0049] The preset sampling frequency is set based on the transmission line rate of the first CDR sequence. Due to the frequency offset of the reference clock, the actual transmission line rate may be greater than the agreed line rate during actual transmission. To improve the accuracy of the sampling results, the preset sampling frequency will be larger than the agreed transmission line rate, such as 2x or 3x. This application does not limit the specific multiple of the preset sampling frequency.

[0050] In one example, the agreed-upon first CDR sequence transmission line rate is 16 bits / s, while the actual first CDR sequence transmission rate might be 18 bits / s. If the sampling frequency is set to 16 samples per second based on the agreed-upon first CDR sequence transmission line rate, characters may be missed. Therefore, the sampling frequency needs to be higher than the agreed-upon first CDR sequence transmission line rate, so it can be set to twice the sampling frequency, such as 32 samples per second.

[0051] Multiple first CDR sequences are obtained by sampling multiple first CDR sequences, and each first CDR sequence corresponds to a first CDR sampling sequence.

[0052] In one example, such as Figure 4 As shown, Figure 4 The process involves the transmitter serializing and sending the first CDR sequence to the high-speed transceiver, and the high-speed transceiver serially receiving and upsampling the first CDR sequence to obtain the first CDR sample sequence. The first CDR sequence is exemplified by parallel data 0101010101010101 with a bit width of 16.

[0053] The reference clock frequency of the transmitting end can be calculated from the CDR sequence; therefore, high-speed transceivers need to sample multiple CDR sequences. To improve sampling accuracy, the CDR sequence is typically upsampled using an upsampling frequency.

[0054] S103: The high-speed transceiver calculates the first reference clock frequency of the transmitting end based on multiple first CDR sampling sequences. The first reference clock frequency is the transmission frequency of the multiple first CDR sequences.

[0055] Specifically: 1. Based on the number of transitions of a first CDR sequence and the total number of transitions of multiple first CDR sequences, the number of first CDR sequences in the multiple first CDR sequences is obtained; wherein, the total number of transitions of multiple first CDR sequences is the same as the total number of transitions of multiple first CDR sampling sequences. 2. Based on the number of multiple first CDR sequences and the time for receiving multiple first CDR sequences, the first reference clock frequency of the transmitting end is calculated.

[0056] In one example, the first CDR sequence is a 16-bit wide sequence of 0101010101010101, with 8 0-1 transitions (n). After upsampling, the first CDR sequence becomes 001100110011001100110011001100110011, with 8 0-1 transitions.

[0057] Understandably, upsampling the first CDR sequence will not change the number of transitions in the first CDR sequence.

[0058] The formula for calculating the first reference clock frequency of the transmitting end can be: Where f represents the first reference clock frequency of the transmitting end, k represents the total number of transitions of multiple first CDR sequences, n represents the number of transitions of a single first CDR sequence, and t represents the time for receiving multiple first CDR sequences.

[0059] In one example, the high-speed transceiver receives multiple first CDR sequences, for example, a 16-bit wide sequence of 0101010101010101, with 8 0-1 transitions (n). The high-speed transceiver counts the total number of 0-1 transitions across these multiple first CDR sequences as 800,000, meaning the total number of 0-1 transitions (k) is 800,000. Therefore, the total number of these first CDR sequences can be calculated to be 100,000. The transmission time (t) is 1 ms, meaning it takes 1 ms to transmit 100,000 first CDR sequences. Therefore, the number of first CDR sequences that the transmitter can send per second is 100 * 10^ ... 6 If there are 100 MHz, then the transmitting frequency of the transmitting end is 100 MHz, that is, the reference clock frequency of the transmitting end is 100 MHz.

[0060] Since the number of 0-1 transitions of the first CDR sequence and the first CDR sampled sequence after upsampling is the same, the total number of 0-1 transitions of multiple first CDR sequences and multiple first CDR sampled sequences is the same. At this time, the total number of 0-1 transitions of multiple first CDR sequences can be obtained by counting the total number of 0-1 transitions of multiple first CDR sampled sequences.

[0061] S104: The high-speed transceiver generates a first lock signal. This first lock signal indicates that the first reference clock frequency is locked.

[0062] After calculating the first reference clock frequency of the transmitting end, the high-speed transceiver will lock onto that frequency and generate a first locking signal.

[0063] In one example, the CDR locking unit in the high-speed transceiver includes a lock indicator pin: cdr_stable. When the lock indicator pin is 0, it indicates that the first reference clock frequency is not locked, and when the lock indicator pin is 1, it indicates that the first reference clock frequency is locked.

[0064] In this method, by setting the reference clock frequency of the high-speed transceiver to the first reference clock frequency, the transmitter and the high-speed transceiver operate at the same reference clock frequency, reducing the number of times the reference clock frequency of the high-speed transceiver needs to be set and improving the communication efficiency between the two parties.

[0065] S105: The control unit detected the first lock signal.

[0066] S106: The control unit sets the reference clock frequency of the high-speed transceiver to the first reference clock frequency.

[0067] Optionally, the control unit controls the clock unit to set the reference clock frequency of the high-speed transceiver to the first reference clock frequency.

[0068] After step S105, the high-speed transceiver locks onto the first reference clock frequency. At this point, the high-speed transceiver's reference clock frequency is the first reference clock frequency. During subsequent communication between the transmitter and the high-speed transceiver, if the transmitter's reference clock frequency changes (e.g., shifts), and the change exceeds a preset amount, the high-speed transceiver needs to relock onto the transmitter's reference clock frequency. Changes in the transmitter's reference clock frequency cause corresponding changes in the high-speed transceiver's reference clock frequency.

[0069] like Figure 5 As shown, Figure 5 This application provides a flowchart of a high-speed transceiver reference clock frequency pulling method. The method may include: S201-S206.

[0070] S201: The transmitter sends multiple second CDR sequences to the high-speed transceiver. Correspondingly, the high-speed transceiver receives multiple second CDR sequences.

[0071] The second CDR sequence is a jump sequence.

[0072] In one example, the sender periodically (e.g., every hour) sends multiple second CDR sequences to the high-speed transceiver. These multiple second CDR sequences may be the same as or different from the multiple CDR sequences.

[0073] In another example, the high-speed transceiver sends a signal to the transmitter instructing the transmitter to send multiple second CDR sequences to the high-speed transceiver.

[0074] S202: The high-speed transceiver determines whether the first reference clock frequency is out of lock based on multiple second CDR sequences.

[0075] Loss of lock is used to characterize a difference between the reference clock frequency of the transmitter and the reference clock frequency of the high-speed transceiver that is greater than a preset difference.

[0076] When the first reference clock frequency is lost, execute S203;

[0077] This process ends when the first reference clock frequency is not lost.

[0078] Specifically, the high-speed transceiver calculates the bit error rate of multiple CDR sequences based on multiple second CDR sequences. The second CDR sequence is a transition sequence.

[0079] Bit error rate (BER) is the percentage of erroneous bits in a sequence of multiple second CDR sequences received by a high-speed transceiver from the transmitter.

[0080] When the bit error rate of multiple second CDR sequences exceeds a preset value, the first reference clock frequency is determined to be out of lock.

[0081] When the bit error rate of multiple second CDR sequences is less than or equal to a preset value, it is determined that the first reference clock frequency has not lost lock.

[0082] S203: The high-speed transceiver calculates the second reference clock frequency of the transmitting end based on multiple second CDR sequences.

[0083] For the specific method of calculating the second reference clock frequency of the transmitting end based on multiple second CDR sequences, please refer to S102-S103.

[0084] S204: The high-speed transceiver generates a second lock signal.

[0085] The second locking signal is used to lock the second reference clock frequency.

[0086] For a description related to S204, please refer to S104.

[0087] S205: The control unit detected a second lock signal.

[0088] S206: The control unit sets the reference clock frequency of the high-speed transceiver to the second reference clock frequency.

[0089] Optionally, the control unit controls the clock unit to set the reference clock frequency of the high-speed transceiver to a second reference clock frequency.

[0090] like Figure 6 As shown, Figure 6 A flowchart of another high-speed transceiver reference clock frequency pulling method provided in this application embodiment. The method may include: S301-S305.

[0091] S301: The transmitter sends multiple second CDR sequences to the high-speed transceiver. Correspondingly, the high-speed transceiver receives multiple second CDR sequences.

[0092] The second CDR sequence is a jump sequence.

[0093] The sending end periodically (e.g., every hour) sends multiple second CDR sequences to the high-speed transceiver. These multiple second CDR sequences may be the same as or different from the multiple CDR sequences.

[0094] S302: The high-speed transceiver calculates the second reference clock frequency of the transmitting end based on multiple second CDR sequences.

[0095] For the specific method of calculating the second reference clock frequency of the transmitting end based on multiple second CDR sequences, please refer to S102-S103.

[0096] If the difference between the first reference clock frequency and the second reference clock frequency is greater than a preset difference, the first reference clock frequency is unlocked.

[0097] If the difference between the first reference clock frequency and the second reference clock frequency is less than or equal to a preset difference, then the first reference clock frequency has not lost lock.

[0098] When the first reference clock frequency is lost, execute S303;

[0099] This process ends when the first reference clock frequency is not lost.

[0100] S303: The high-speed transceiver generates a second lock signal.

[0101] The second locking signal is used to lock the second reference clock frequency.

[0102] For a description of S303, please refer to S104.

[0103] S304: The control unit detected a second lock signal.

[0104] S305: The control unit sets the reference clock frequency of the high-speed transceiver to the second reference clock frequency.

[0105] Optionally, the control unit controls the clock unit to set the reference clock frequency of the high-speed transceiver to a second reference clock frequency.

[0106] This application provides a reference clock frequency setting method applied to a high-speed transceiver connected to a control unit. In this method, the high-speed transceiver first receives multiple CDR sequences transmitted by the transmitting end. It then samples these CDR sequences to obtain multiple CDR sample sequences, calculates the reference clock frequency of the transmitting end based on the sample sequences, and generates a locking signal. Finally, the control unit sets the reference clock frequency of the high-speed transceiver to the reference clock frequency of the transmitting end based on the locking signal. It is understood that this method quickly calculates the reference clock frequency of the transmitting end by receiving the CDR sequences, reducing the time required to determine the reference clock frequency of the high-speed transceiver and improving communication efficiency.

[0107] The foregoing primarily describes the solutions provided by the embodiments of this application from a methodological perspective. To achieve the aforementioned functions, it includes corresponding hardware structures and / or software modules for executing each function. Those skilled in the art should readily recognize that, in conjunction with the units and algorithm steps of the various examples described in the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0108] This application also provides a high-speed transceiver 200. For example... Figure 7 The diagram shown is a structural schematic of a high-speed transceiver 200 provided in an embodiment of this application.

[0109] The high-speed transceiver 200 includes: a receiving unit 210 for receiving multiple first clock signals transmitted by a transmitting end to recover CDR sequences; wherein the first CDR sequences are transition sequences; a sampling unit 220 for sampling the multiple first CDR sequences to obtain multiple first CDR sampling sequences; wherein the first CDR sequences correspond one-to-one with the first CDR sampling sequences; a calculation unit 230 for calculating a first reference clock frequency of the transmitting end based on the multiple first CDR sampling sequences; wherein the first reference clock frequency is the transmission frequency of the multiple first CDR sequences; and a locking unit 240 for generating a first locking signal; wherein the first locking signal is used to indicate locking the first reference clock frequency, and is used by the control unit to set the reference clock frequency of the high-speed transceiver to the first reference clock frequency after detecting the first locking signal.

[0110] Optionally, after setting the reference clock frequency of the high-speed transceiver to the first reference clock frequency, the receiving unit 210 is further configured to receive multiple second CDR sequences; wherein the second CDR sequence is a transition sequence; the high-speed transceiver also includes a determining unit 250, which is configured to calculate the second reference clock frequency of the transmitting end when the first reference clock frequency is determined to be out of lock based on multiple second CDR sequences; wherein the out of lock is used to characterize that the difference between the reference clock frequency of the transmitting end and the reference clock frequency of the high-speed transceiver is greater than a preset difference; the locking unit 240 is further configured to generate a second locking signal; wherein the second locking signal is used to indicate locking the second reference clock frequency, and is used to set the reference clock frequency of the high-speed transceiver to the second reference clock frequency after the control unit detects the second locking signal.

[0111] Optionally, the determining unit 250 is specifically used to determine that the first reference clock frequency is out of lock when the bit error rate of multiple second CDR sequences is greater than a preset value.

[0112] Optionally, after setting the reference clock frequency of the high-speed transceiver to the first reference clock frequency, the receiving unit 210 is further configured to receive multiple second CDR sequences; wherein the second CDR sequence is a transition sequence; the calculation unit 230 is further configured to calculate the second reference clock frequency of the transmitting end based on the multiple second CDR sequences; the locking unit 240 is further configured to generate a second locking signal when the difference between the first reference clock frequency and the second reference clock frequency is greater than a preset difference; wherein the second locking signal is used to indicate locking the second reference clock frequency, and is used to control the unit to set the reference clock frequency of the high-speed transceiver to the second reference clock frequency after detecting the second locking signal.

[0113] Optionally, the calculation unit 230 is specifically used to: obtain the number of first CDR sequences among the multiple first CDR sequences based on the number of transitions of a first CDR sequence and the total number of transitions of the multiple first CDR sequences; wherein the total number of transitions of the multiple first CDR sequences is the same as the total number of transitions of the multiple first CDR sampling sequences; and calculate the first reference clock frequency of the transmitting end based on the number of multiple first CDR sequences and the time of receiving the multiple first CDR sequences.

[0114] Optionally, the calculation unit 230 is specifically used to: divide the total number of transitions of the multiple first CDR sequences by the number of transitions of a single first CDR sequence to obtain the number of first CDR sequences in the multiple first CDR sequences; and divide the number of first CDR sequences in the multiple first CDR sequences by the time of receiving the multiple first CDR sequences to obtain the first reference clock frequency of the transmitting end.

[0115] Optionally, the sampling unit 220 is specifically used to upsample multiple first CDR sequences based on a preset sampling frequency.

[0116] Of course, the high-speed transceiver 200 provided in this application embodiment includes, but is not limited to, the modules described above.

[0117] In actual implementation, the receiving unit 210, sampling unit 220, calculation unit 230, locking unit 240, and determining unit 250 of the high-speed transceiver 200 can be implemented by the processor calling computer program code in memory. The specific execution process can be found in the description of the method section above, and will not be repeated here.

[0118] Another embodiment of this application provides a high-speed transceiver, including a memory and a processor. The memory and the processor are coupled; the memory stores computer program code, which includes computer instructions. When the processor executes the computer instructions, the high-speed transceiver performs the steps of the reference clock frequency setting method shown in the above-described method embodiment.

[0119] Another embodiment of this application provides a computer-readable storage medium storing computer instructions that, when executed on a high-speed transceiver, cause the high-speed transceiver to perform each step of the reference clock frequency setting method flow shown in the above method embodiment.

[0120] Another embodiment of this application provides a chip system applied to a high-speed transceiver. The chip system includes one or more interface circuits and one or more processors. The interface circuits and processors are interconnected via lines. The interface circuits are used to receive signals from the high-speed transceiver's memory and send signals to the processor, the signals including computer instructions stored in the memory. When the high-speed transceiver processor executes the computer instructions, the high-speed transceiver performs each step of the reference clock frequency setting method flow shown in the above method embodiment.

[0121] In another embodiment of this application, a computer program product is also provided, which includes computer instructions that, when executed on a high-speed transceiver, cause the high-speed transceiver to perform each step of the reference clock frequency setting method flow shown in the above method embodiment.

[0122] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented using software programs, implementation can be, in whole or in part, in the form of a computer program product. This computer program product includes one or more computer instructions. When these computer instructions are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device containing one or more servers, data centers, etc., that can be integrated with the medium. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state disks, SSDs).

[0123] The above description is merely a specific embodiment of this application. Any variations or substitutions conceived by those skilled in the art based on the specific embodiments provided in this application should be covered within the protection scope of this application.

Claims

1. A method for setting a reference clock frequency, characterized in that, Applied to a high-speed transceiver connected to a control unit, the method includes: Receive multiple first CDR sequences sent by the transmitting end; wherein, the first CDR sequence is a transition sequence; The plurality of first CDR sequences are sampled to obtain a plurality of first CDR sample sequences; wherein, the first CDR sequence corresponds one-to-one with the first CDR sample sequence; Based on the number of transitions of a first CDR sequence and the total number of transitions of the plurality of first CDR sequences, the number of first CDR sequences in the plurality of first CDR sequences is obtained; wherein, the total number of transitions of the plurality of first CDR sequences is the same as the total number of transitions of the plurality of first CDR sampling sequences; Based on the number of the plurality of first CDR sequences and the time of receiving the plurality of first CDR sequences, the first reference clock frequency of the transmitting end is calculated; wherein, the first reference clock frequency is the transmission frequency of the plurality of first CDR sequences; A first locking signal is generated; wherein the first locking signal is used to indicate locking the first reference clock frequency, and is used by the control unit to set the reference clock frequency of the high-speed transceiver to the first reference clock frequency after detecting the first locking signal.

2. The method according to claim 1, characterized in that, After setting the reference clock frequency of the high-speed transceiver to the first reference clock frequency, the method further includes: Receive multiple second CDR sequences; wherein, the second CDR sequence is a transition sequence; When the first reference clock frequency is determined to be out of lock based on the plurality of second CDR sequences, the second reference clock frequency of the transmitting end is calculated; wherein, the out of lock is used to characterize that the difference between the reference clock frequency of the transmitting end and the reference clock frequency of the high-speed transceiver is greater than a preset difference; The high-speed transceiver generates a second lock signal; wherein the second lock signal is used to indicate locking the second reference clock frequency, and is used by the control unit to set the reference clock frequency of the high-speed transceiver to the second reference clock frequency after detecting the second lock signal.

3. The method according to claim 2, characterized in that, The method further includes: When the bit error rate of the plurality of second CDR sequences is greater than a preset value, it is determined that the first reference clock frequency is out of lock.

4. The method according to claim 1, characterized in that, After adjusting the reference clock frequency of the high-speed transceiver to the first reference clock frequency, the method further includes: Receive multiple second CDR sequences; wherein, the second CDR sequence is a transition sequence; Based on the plurality of second CDR sequences, the second reference clock frequency of the transmitting end is calculated; When the difference between the first reference clock frequency and the second reference clock frequency is greater than a preset difference, a second locking signal is generated; wherein, the second locking signal is used to indicate locking the second reference clock frequency, and is used by the control unit to set the reference clock frequency of the high-speed transceiver to the second reference clock frequency after detecting the second locking signal.

5. The method according to claim 1, characterized in that, The method of obtaining the number of first CDR sequences among the plurality of first CDR sequences based on the number of transitions of a single first CDR sequence and the total number of transitions of the plurality of first CDR sequences includes: The number of first CDR sequences in the plurality of first CDR sequences is obtained by dividing the total number of transitions of the plurality of first CDR sequences by the number of transitions of the first CDR sequence. The calculation of the first reference clock frequency of the transmitting end based on the number of the plurality of first CDR sequences and the time of receiving the plurality of first CDR sequences includes: The first reference clock frequency of the transmitting end is obtained by dividing the number of the first CDR sequences in the plurality of first CDR sequences by the time of receiving the plurality of first CDR sequences.

6. The method according to claim 1, characterized in that, The sampling of the plurality of first CDR sequences includes: Based on a preset sampling frequency, the plurality of first CDR sequences are upsampled.

7. A high-speed transceiver, characterized in that, The high-speed transceiver is connected to a control unit, including: A receiving unit is configured to receive multiple first CDR sequences sent by a transmitting end; wherein the first CDR sequence is a transition sequence; A sampling unit is used to sample the plurality of first CDR sequences to obtain a plurality of first CDR sampling sequences; wherein, the first CDR sequence corresponds one-to-one with the first CDR sampling sequence; A calculation unit is configured to: obtain the number of first CDR sequences among the plurality of first CDR sequences based on the number of transitions of a single first CDR sequence and the total number of transitions of the plurality of first CDR sequences; wherein the total number of transitions of the plurality of first CDR sequences is the same as the total number of transitions of the plurality of first CDR sampling sequences; and calculate a first reference clock frequency of the transmitting end based on the number of the plurality of first CDR sequences and the time for receiving the plurality of first CDR sequences; wherein the first reference clock frequency is the transmission frequency of the plurality of first CDR sequences. A locking unit is used to generate a first locking signal; wherein the first locking signal is used to indicate locking the first reference clock frequency, and is used by the control unit to set the reference clock frequency of the high-speed transceiver to the first reference clock frequency after detecting the first locking signal.

8. The high-speed transceiver according to claim 7, characterized in that, After setting the reference clock frequency of the high-speed transceiver to the first reference clock frequency, the receiving unit is further configured to receive a plurality of second CDR sequences; wherein the second CDR sequences are transition sequences; the high-speed transceiver further includes a determining unit, which is configured to determine that the first reference clock frequency is out of lock based on the plurality of second CDR sequences; the calculating unit is further configured to calculate the second reference clock frequency of the transmitting end when the first reference clock frequency is out of lock based on the plurality of second CDR sequences; wherein the out of lock is used to characterize that the difference between the reference clock frequency of the transmitting end and the reference clock frequency of the high-speed transceiver is greater than a preset difference; the locking unit is further configured to generate a second locking signal; wherein the second locking signal is used to indicate locking the second reference clock frequency, and is used by the control unit to set the reference clock frequency of the high-speed transceiver to the second reference clock frequency after detecting the second locking signal; The determining unit is specifically used to determine that the first reference clock frequency is out of lock when the bit error rate of the plurality of second CDR sequences is greater than a preset value; After setting the reference clock frequency of the high-speed transceiver to the first reference clock frequency, the receiving unit is further configured to receive a plurality of second CDR sequences; wherein the second CDR sequences are transition sequences; the calculation unit is further configured to calculate the second reference clock frequency of the transmitting end based on the plurality of second CDR sequences; the locking unit is further configured to generate a second locking signal when the difference between the first reference clock frequency and the second reference clock frequency is greater than a preset difference; wherein the second locking signal is used to indicate locking the second reference clock frequency, and is used by the control unit to set the reference clock frequency of the high-speed transceiver to the second reference clock frequency after detecting the second locking signal; The calculation unit is specifically used to: divide the total number of transitions of the plurality of first CDR sequences by the number of transitions of one of the first CDR sequences to obtain the number of first CDR sequences in the plurality of first CDR sequences; and divide the number of first CDR sequences in the plurality of first CDR sequences by the time of receiving the plurality of first CDR sequences to obtain the first reference clock frequency of the transmitting end. The sampling unit is specifically used to upsample the plurality of first CDR sequences based on a preset sampling frequency.

9. A high-speed transceiver, characterized in that, The transceiver includes a memory and a processor; the memory and the processor are coupled; the memory is used to store computer program code, the computer program code including computer instructions; wherein, when the processor executes the computer instructions, it causes the high-speed transceiver to perform the method as described in any one of claims 1-6.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions; wherein, when the computer instructions are executed on the high-speed transceiver, the high-speed transceiver causes the high-speed transceiver to perform the method as described in any one of claims 1-6.

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