A circuit quality testing method, device, server, medium and system

Abstract

The present application provides a circuit quality testing method, device, server, medium and system, the method comprising obtaining multiple destination addresses to be tested on a dedicated line circuit of a user to be tested from a primary aggregation point or an aggregation switch, sending test requests to terminal devices corresponding to the destination addresses to be tested respectively, and obtaining circuit quality data corresponding to each destination address to be tested; obtaining a comprehensive circuit quality result corresponding to the destination address to be tested using a circuit quality quantification model according to the circuit quality data corresponding to the destination address to be tested; obtaining a total quality result of the dedicated line circuit of the user to be tested according to each comprehensive quality result of the circuit; and according to the total quality result, as well as the acquired fault statistical data and bandwidth utilization data of the dedicated line circuit of the user to be tested within a preset statistical period, when it is determined that the dedicated line circuit of the user to be tested is a poor-quality circuit, performing corresponding optimization processing on the dedicated line circuit of the user to be tested.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a circuit quality testing method, device, server, medium and system. Background Art

[0002] At present, the scale of broadband services is constantly expanding, especially the Internet dedicated line services for enterprises, institutions or group users are booming. Correspondingly, users' requirements for circuit quality and service capabilities are also getting higher and higher.

[0003] However, the existing technology still lacks circuit quality testing for Internet dedicated line services. The existing network management system can only obtain circuit alarm information and on-off data through access equipment to learn about major circuit failures, but cannot test the circuit quality before a major circuit failure occurs to optimize the circuit with poor quality in advance. Summary of the invention

[0004] The present application provides a circuit quality testing method, device, server, medium and system, which are used to solve the problem of lack of circuit quality testing for Internet dedicated line services in the prior art.

[0005] In a first aspect, the present application provides a circuit quality testing method, comprising: obtaining multiple destination addresses to be tested on a dedicated line circuit of a user to be tested from a first-level aggregation point or an aggregation switch, and sending test requests to terminal devices corresponding to the destination addresses to be tested respectively, so as to obtain circuit quality data corresponding to each destination address to be tested; for each destination address to be tested, according to the circuit quality data corresponding to the destination address to be tested, using a circuit quality quantification model, obtaining a comprehensive circuit quality result corresponding to the destination address to be tested; wherein the circuit quality quantification model includes weights, indicator intervals and quality intervals corresponding to each indicator in the circuit quality data; according to the comprehensive circuit quality result corresponding to each destination address to be tested, obtaining a total quality result of the dedicated line circuit of the user to be tested; according to the total quality result of the dedicated line circuit of the user to be tested, and the acquired fault statistical data and bandwidth utilization data of the dedicated line circuit of the user to be tested within a preset statistical period, when it is determined that the dedicated line circuit of the user to be tested is a poor quality circuit, the dedicated line circuit of the user to be tested is optimized accordingly.

[0006] In a specific implementation manner, for each destination address to be tested, according to the circuit quality data corresponding to the destination address to be tested, using a circuit quality quantification model, obtaining a comprehensive circuit quality result corresponding to the destination address to be tested, including: for each destination address to be tested, using a circuit quality quantification model, respectively determining an indicator interval and a quality interval corresponding to each indicator in the circuit quality data corresponding to the destination address to be tested; for each indicator, using the circuit quality quantification model, obtaining an upper limit value and a lower limit value of the indicator interval corresponding to the indicator, an upper limit value and a lower limit value of the quality interval, and a weight, and using a formula in the circuit quality quantification model: Kn=(lower limit value of the quality interval+difference between upper and lower limits in the quality interval*(upper limit value of the indicator interval-value of the indicator) / difference between upper and lower limits in the indicator interval)*weight, to obtain an indicator quality value Kn corresponding to the indicator; according to the indicator quality value corresponding to each indicator, obtaining a comprehensive circuit quality result corresponding to the destination address to be tested.

[0007] In a specific implementation, the indicators include average delay, packet loss rate and average jitter.

[0008] In a specific implementation, the method of obtaining the total quality result of the dedicated line circuit of the user to be tested based on the comprehensive quality result of the circuit corresponding to each destination address to be tested includes: obtaining the comprehensive quality result of the circuit corresponding to each destination address to be tested on the dedicated line circuit of the user to be tested, taking the average of multiple comprehensive quality results of the circuit to obtain the total quality result of the dedicated line circuit of the user to be tested.

[0009] In a specific implementation manner, according to the total quality result of the dedicated line circuit of the user to be tested, and the fault statistical data and bandwidth utilization data obtained within a preset statistical period of the dedicated line circuit of the user to be tested, when it is determined that the dedicated line circuit of the user to be tested is a poor quality circuit, the dedicated line circuit of the user to be tested is optimized accordingly, including: obtaining the fault duration, the number of repeated faults and the bandwidth utilization peak value of the dedicated line circuit of the user to be tested within a preset statistical period, and using the formula: availability = (1-fault duration / 720)*100% to obtain the availability; respectively obtaining the quality values ​​corresponding to the availability, the fault duration, the number of repeated faults and the bandwidth utilization peak value; adding the quality value corresponding to the availability, the quality value corresponding to the fault duration, the quality value corresponding to the number of repeated faults and the quality value corresponding to the bandwidth utilization peak value to the total quality result of the dedicated line circuit of the user to be tested to obtain the circuit comprehensive result of the dedicated line circuit of the user to be tested; when the circuit comprehensive result is less than the circuit comprehensive result threshold, it is determined that the dedicated line circuit of the user to be tested is a poor quality circuit, and the dedicated line circuit of the user to be tested is optimized accordingly.

[0010] In a specific implementation manner, the method of obtaining multiple destination addresses to be tested on the dedicated line circuit of the user to be tested from a first-level aggregation point or an aggregation switch, and sending test requests to the terminal devices corresponding to the destination addresses to be tested respectively, so as to obtain circuit quality data corresponding to each destination address to be tested, includes: obtaining multiple destination addresses to be tested on the dedicated line circuit of the user to be tested from the first-level aggregation point or the aggregation switch; for each destination address to be tested, generating an ICMP echo request message corresponding to the target address to be tested, and sending the ICMP echo request message to the terminal device corresponding to the target address to be tested, so as to receive the ICMP echo reply message returned by the terminal device; obtaining the average delay and average jitter corresponding to each destination address to be tested according to the sending time of the ICMP echo request message and the receiving time of the ICMP echo reply message corresponding to each target address to be tested respectively; obtaining the packet loss rate corresponding to each destination address to be tested according to the number of ICMP echo request messages and the number of ICMP echo reply messages corresponding to each target address to be tested respectively.

[0011] In a second aspect, the present application provides a circuit quality testing device, comprising: a testing module, used to obtain multiple destination addresses to be tested on the dedicated line circuit of the user to be tested from a first-level aggregation point or an aggregation switch, and send test requests to the terminal devices corresponding to the destination addresses to be tested respectively to obtain circuit quality data corresponding to each destination address to be tested; a quantification module, used to obtain, for each destination address to be tested, a comprehensive circuit quality result corresponding to the destination address to be tested using a circuit quality quantification model according to the circuit quality data corresponding to the destination address to be tested; wherein the circuit quality quantification model includes weights, indicator intervals and quality intervals corresponding to each indicator in the circuit quality data; the quantification module is also used to obtain the total quality result of the dedicated line circuit of the user to be tested according to the comprehensive circuit quality result corresponding to each destination address to be tested; a processing module, used to optimize the dedicated line circuit of the user to be tested accordingly when it is determined that the dedicated line circuit of the user to be tested is a poor-quality circuit according to the total quality result of the dedicated line circuit of the user to be tested, and the acquired fault statistical data and bandwidth utilization data of the dedicated line circuit of the user to be tested within a preset statistical period.

[0012] In a specific implementation, the quantization module is specifically used to: for each destination address to be tested, use a circuit quality quantization model to respectively determine the indicator interval and quality interval corresponding to each indicator in the circuit quality data corresponding to the destination address to be tested; for each indicator, use the circuit quality quantization model to obtain the upper limit value and lower limit value of the indicator interval corresponding to the indicator, the upper limit value and lower limit value of the quality interval, and the weight, and use the formula in the circuit quality quantization model: Kn = (lower limit value of quality interval + difference between upper limit value and lower limit value in quality interval * (upper limit value of indicator interval - numerical value of indicator) / difference between upper limit value and lower limit value in indicator interval) * weight to obtain the indicator quality value Kn corresponding to the indicator; according to the indicator quality value corresponding to each indicator, obtain the comprehensive circuit quality result corresponding to the destination address to be tested.

[0013] In a specific implementation, the indicators include average delay, packet loss rate and average jitter.

[0014] In a specific implementation, the quantification module is specifically used to: obtain the comprehensive circuit quality result corresponding to each destination address to be tested on the dedicated line circuit of the user to be tested, take the average of multiple circuit comprehensive quality results, and obtain the total quality result of the dedicated line circuit of the user to be tested.

[0015] In a specific implementation manner, the processing module is specifically used to: obtain the fault duration, repeated fault number and bandwidth utilization peak value of the dedicated line circuit of the user to be tested within a preset statistical period, and use the formula: availability = (1-fault duration / 720)*100% to obtain the availability; respectively obtain the quality values ​​corresponding to the availability, fault duration, repeated fault number and bandwidth utilization peak value; add the quality value corresponding to the availability, the quality value corresponding to the fault duration, the quality value corresponding to the repeated fault number and the quality value corresponding to the bandwidth utilization peak value to the total quality result of the dedicated line circuit of the user to be tested to obtain the circuit comprehensive result of the dedicated line circuit of the user to be tested; when the circuit comprehensive result is less than the circuit comprehensive result threshold, it is determined that the dedicated line circuit of the user to be tested is a poor quality circuit, and the dedicated line circuit of the user to be tested is optimized accordingly.

[0016] In a specific implementation, the test module is specifically used to: obtain multiple destination addresses to be tested on the dedicated line circuit of the user to be tested from a first-level aggregation point or an aggregation switch; for each target address to be tested, generate an ICMP echo request message corresponding to the target address to be tested, and send the ICMP echo request message to the terminal device corresponding to the target address to be tested to receive the ICMP echo reply message returned by the terminal device; obtain the average delay and average jitter corresponding to each destination address to be tested according to the sending time of the ICMP echo request message and the receiving time of the ICMP echo reply message corresponding to each target address to be tested; obtain the packet loss rate corresponding to each destination address to be tested according to the number of ICMP echo request messages and the number of ICMP echo reply messages corresponding to each target address to be tested.

[0017] In a third aspect, the present application provides a server comprising: a processor, a memory, and a communication interface; the memory is used to store executable instructions of the processor; wherein the processor is configured to execute the circuit quality testing method described in the first aspect by executing the executable instructions.

[0018] In a fourth aspect, the present application provides a readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the circuit quality testing method described in the first aspect.

[0019] In a fifth aspect, the present application provides a circuit quality testing system, comprising: a circuit quality testing device, a first-level aggregation point, an aggregation switch, and a terminal device; wherein the circuit quality testing device is arranged on the first-level aggregation point or the aggregation switch; the first-level aggregation point is a broadband access server BRAS or a full-service router SR.

[0020] The present application provides a circuit quality testing method, device, server, medium and system, the circuit quality testing method comprising: obtaining multiple destination addresses to be tested on a dedicated line circuit of a user to be tested from a primary aggregation point or an aggregation switch, and sending test requests to terminal devices corresponding to the destination addresses to be tested respectively, so as to obtain circuit quality data corresponding to each destination address to be tested; for each destination address to be tested, according to the circuit quality data corresponding to the destination address to be tested, using a circuit quality quantification model, obtaining a comprehensive circuit quality result corresponding to the destination address to be tested; wherein the circuit quality quantification model includes weights, indicator intervals and quality intervals corresponding to each indicator in the circuit quality data; according to the comprehensive circuit quality result corresponding to each destination address to be tested, obtaining a total quality result of the dedicated line circuit of the user to be tested; according to the total quality result of the dedicated line circuit of the user to be tested, and the acquired fault statistical data and bandwidth utilization data of the dedicated line circuit of the user to be tested within a preset statistical period, when it is determined that the dedicated line circuit of the user to be tested is a poor-quality circuit, performing corresponding optimization processing on the dedicated line circuit of the user to be tested. Compared with the prior art, the present application initiates a test to the terminal device corresponding to the destination address to be tested, obtains the corresponding circuit quality data, quantifies the circuit quality data using a circuit quality quantification model, obtains the corresponding circuit comprehensive quality result, and integrates the circuit comprehensive quality results corresponding to each destination address to be tested to obtain the total quality result of the dedicated line circuit of the user to be tested, and then combines the fault statistics data and the bandwidth utilization data to determine whether the dedicated line circuit of the user to be tested is a poor quality circuit, thereby achieving a quantitative result that directly reflects the circuit quality by processing the circuit quality data obtained from the test, and then combining the fault data and the bandwidth utilization data to determine the circuit quality in multiple dimensions, which can accurately determine the poor quality circuit so as to optimize the poor quality circuit accordingly. This solves the problem of the lack of circuit quality testing for Internet dedicated line services in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0022] Figure 1 A circuit quality test system structure diagram provided in this application;

[0023] Figure 2 A schematic diagram of a flow chart of a first embodiment of a circuit quality testing method provided by the present application;

[0024] Figure 3 A schematic diagram of a flow chart of a second embodiment of a circuit quality testing method provided by the present application;

[0025] Figure 4 A schematic diagram of a flow chart of a third embodiment of a circuit quality testing method provided by the present application;

[0026] Figure 5 A schematic diagram of a flow chart of a fourth embodiment of a circuit quality testing method provided by the present application;

[0027] Figure 6 A schematic diagram of the structure of an embodiment of a circuit quality testing device provided by the present application;

[0028] Figure 7 A schematic diagram of the structure of a server provided for this application. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments made by ordinary technicians in this field under the enlightenment of the embodiments belong to the scope of protection of the present application.

[0030] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0031] First, the terms involved in this application are explained:

[0032] Level 1 aggregation point: access network equipment, including broadband access server (Broadband Remote Access Server, referred to as BRAS) and full-service router (Service Router, referred to as SR).

[0033] At present, with the continuous expansion of the scale of broadband services, users have higher and higher requirements for the circuit quality and service capabilities of broadband services, especially Internet dedicated line services.

[0034] However, the existing technology still lacks the circuit quality test of Internet dedicated line services. The existing network management system can only obtain circuit alarm information and on-off data through access equipment to learn about major circuit failures, but cannot test the circuit quality before major circuit failures occur and optimize the circuit with poor quality in advance.

[0035] Based on the above technical problems, the technical conception process of this application is as follows: how to implement the circuit quality test of Internet dedicated line services.

[0036] The circuit quality testing scheme of the present application is described in detail below.

[0037] Figure 1 A circuit quality test system structure diagram provided in this application, such as Figure 1 As shown, the system structure may include: a circuit quality test device 11, a first-level aggregation point or aggregation switch 12, and a terminal device 13. The circuit quality test device 11 may be arranged on the first-level aggregation point or aggregation switch 12. The first-level aggregation point is a broadband access server BRAS or a full-service router SR.

[0038] The circuit quality testing device 11 obtains multiple destination addresses to be tested on the dedicated line circuit of the tested user from the first-level aggregation point or aggregation switch 12, and sends test requests to the terminal devices 13 corresponding to the destination addresses to be tested respectively to obtain circuit quality data corresponding to each destination address to be tested.

[0039] The technical solution of the present application is described in detail below through specific embodiments. It should be noted that the following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0040] Figure 2 A schematic diagram of a flow chart of a first embodiment of a circuit quality testing method provided in the present application.

[0041] See also Figure 2 , the circuit quality testing method specifically includes the following steps:

[0042] Step S201: obtaining multiple destination addresses to be tested on the dedicated line circuit of the tested user from a primary aggregation point or aggregation switch, and sending test requests to the terminal devices corresponding to the destination addresses to be tested respectively to obtain circuit quality data corresponding to each destination address to be tested.

[0043] In this embodiment, the dedicated line circuit of the user to be tested includes multiple destination addresses to be tested. The first-level aggregation point or aggregation switch stores multiple destination addresses to be tested on the dedicated line circuit of the user to be tested. The circuit quality testing device obtains the destination addresses to be tested from the first-level aggregation point or aggregation switch, and sends test requests to the terminal devices corresponding to each destination address to be tested. Each terminal device responds to the test request, and the circuit quality testing device can obtain the circuit quality data corresponding to each destination address to be tested.

[0044] Step S202: For each destination address to be tested, according to the circuit quality data corresponding to the destination address to be tested, use the circuit quality quantization model to obtain the comprehensive circuit quality result corresponding to the destination address to be tested; wherein, the circuit quality quantization model includes the weights, index intervals, and quality intervals corresponding to each index in the circuit quality data.

[0045] In this embodiment, the circuit quality testing device uses the circuit quality quantization model to perform quantization processing on the circuit quality data corresponding to the destination address to be tested obtained, so as to obtain the comprehensive circuit quality result corresponding to the destination address to be tested. The circuit quality quantization model includes the weights, index intervals, and quality intervals corresponding to each index in the circuit quality data.

[0046] Exemplarily, the index "average delay" in the circuit quality data corresponding to the destination address to be tested obtained by the circuit quality testing device is 13 ms. Using the circuit quality quantization model, the weight corresponding to the average delay can be obtained as 40%, the corresponding index interval is 10 < X <= 30, and the corresponding weight is [80, 90]. Similarly, using the circuit quality quantization model, the weights, index intervals, and quality intervals corresponding to other indexes in the circuit quality data can be obtained, and the comprehensive circuit quality result corresponding to the destination address to be tested can be obtained.

[0047] Step S203: According to the comprehensive circuit quality result corresponding to each destination address to be tested, obtain the total quality result of the dedicated line circuit of the user to be tested.

[0048] In this embodiment, the circuit quality testing device synthesizes the comprehensive circuit quality results corresponding to each destination address to be tested on the dedicated line circuit of the user to be tested, and can obtain the total quality result of the dedicated line circuit of the user to be tested.

[0049] Step S204: According to the total quality result of the dedicated line circuit of the user to be tested, and the obtained fault statistics data and bandwidth utilization data within the preset statistical period of the dedicated line circuit of the user to be tested, when it is determined that the dedicated line circuit of the user to be tested is a poor-quality circuit, perform corresponding optimization processing on the dedicated line circuit of the user to be tested.

[0050] In this embodiment, the circuit quality testing device can obtain the fault statistical data of the dedicated line circuit of the user to be tested within a preset statistical period from the fault maintenance system, and obtain the bandwidth utilization data of the dedicated line circuit of the user to be tested within a preset statistical period from the dedicated line service direct needle system. According to the total quality result of the dedicated line circuit of the user to be tested, the fault statistical data and the bandwidth utilization data within the preset statistical period, it is determined whether the dedicated line circuit of the user to be tested is a poor quality circuit, and when it is determined that the dedicated line circuit of the user to be tested is a poor quality circuit, the dedicated line circuit of the user to be tested is optimized accordingly.

[0051] In this embodiment, the circuit quality testing device obtains multiple destination addresses to be tested on the dedicated line circuit of the user to be tested from a first-level aggregation point or an aggregation switch, and sends test requests to the terminal devices corresponding to the destination addresses to be tested respectively to obtain circuit quality data corresponding to each destination address to be tested; for each destination address to be tested, according to the circuit quality data corresponding to the destination address to be tested, a circuit quality quantification model is used to obtain a comprehensive quality result of the circuit corresponding to the destination address to be tested; wherein the circuit quality quantification model includes weights, indicator intervals and quality intervals corresponding to each indicator in the circuit quality data; according to the comprehensive quality result of the circuit corresponding to each destination address to be tested, the total quality result of the dedicated line circuit of the user to be tested is obtained; according to the total quality result of the dedicated line circuit of the user to be tested, and the fault statistical data and bandwidth utilization data of the dedicated line circuit of the user to be tested obtained within a preset statistical period, when it is determined that the dedicated line circuit of the user to be tested is a poor quality circuit, the dedicated line circuit of the user to be tested is optimized accordingly. Compared with the prior art, the present application initiates a test to the terminal device corresponding to the destination address to be tested, obtains the corresponding circuit quality data, quantifies the circuit quality data using a circuit quality quantification model, obtains the corresponding circuit comprehensive quality result, and integrates the circuit comprehensive quality results corresponding to each destination address to be tested to obtain the total quality result of the dedicated line circuit of the user to be tested, and then combines the fault statistics data and the bandwidth utilization data to determine whether the dedicated line circuit of the user to be tested is a poor quality circuit, and realizes processing the circuit quality data obtained by the test to obtain a quantitative result that intuitively reflects the circuit quality, and then combines the fault data and the bandwidth utilization data to determine the circuit quality in multiple dimensions, which can accurately determine the poor quality circuit, so as to optimize the poor quality circuit accordingly. This solves the problem of the lack of testing of the circuit quality of Internet dedicated line services in the prior art.

[0052] Figure 3 A schematic diagram of a flow chart of a circuit quality testing method embodiment 2 provided in the present application, in the above Figure 2 Based on the embodiment shown, see Figure 3, a specific implementation of step S202 and step S203 is as follows:

[0053] Step S301: For each destination address to be tested, use the circuit quality quantization model to respectively determine the index interval and quality interval corresponding to each index in the circuit quality data corresponding to the destination address to be tested.

[0054] The index includes average delay, packet loss rate, and average jitter.

[0055] In this embodiment, the circuit quality testing device obtains the circuit quality data corresponding to each destination address to be tested, and uses the circuit quality quantization model to respectively determine the index interval and quality interval corresponding to each index in the circuit quality data corresponding to the destination address to be tested. Exemplarily, the circuit quality quantization model is shown in Table 1 below. Wherein, X represents the index "average delay", Y represents the index "packet loss rate", and Z represents the index "average jitter".

[0056] Table 1 Circuit Quality Quantization Model

[0057]

[0058] Exemplarily, the circuit quality data obtained by the circuit quality testing device is: average delay 13ms, packet loss rate 0%, average jitter 15ms. Using the circuit quality quantization model, it is determined that the index interval corresponding to the average delay is 10 < X <= 30, and the corresponding quality interval is [80, 90]; it is determined that the index interval corresponding to the packet loss rate is 0 < Y <= 0.01, and the corresponding quality interval is [90, 100]; it is determined that the index interval corresponding to the average jitter is 10 < Z <= 30, and the corresponding quality interval is [80, 90].

[0059] Step S302: For each index, use the circuit quality quantization model to obtain the upper limit value and lower limit value of the index interval corresponding to the index, the upper limit value and lower limit value of the quality interval, and the weight, and use the formula in the circuit quality quantization model: Kn = (lower limit value of the quality interval + difference between the upper limit value and the lower limit value within the quality interval * (upper limit value of the index interval - value of the index) / difference between the upper limit value and the lower limit value within the index interval) * weight, to obtain the index quality value Kn corresponding to the index.

[0060] In this embodiment, for each metric, using the circuit quality quantization model, the upper limit value and the lower limit value of the metric interval corresponding to the metric, the upper limit value and the lower limit value of the quality interval, and the weight are obtained. As in the foregoing example, the metric interval corresponding to the average delay is 10 < X <= 30, the upper limit value of the metric interval is 30, the lower limit value is 10, the corresponding quality interval is [80, 90], the upper limit value of the quality interval is 90, and the lower limit value is 80. The metric interval corresponding to the packet loss rate is 0 < Y <= 0.01, the upper limit value of the metric interval is 0.01, the lower limit value is 0, the corresponding quality interval is [90, 100], the upper limit value of the quality interval is 100, and the lower limit value is 90. The metric interval corresponding to the average jitter is 10 < Z <= 30, the upper limit value of the metric interval is 30, the lower limit value is 10, the corresponding quality interval is [80, 90], the upper limit value of the quality interval is 90, and the lower limit value is 80. The weight corresponding to the average delay is 40%, the weight corresponding to the packet loss rate is 30%, and the weight corresponding to the average jitter is 30%.

[0061] In this embodiment, the circuit quality quantization model further includes the formula: Kn = (lower limit value of the quality interval + difference between the upper limit value and the lower limit value within the quality interval * (upper limit value of the metric interval - value of the metric) / difference between the upper limit value and the lower limit value within the metric interval) * weight. By using the formula for calculation, the metric quality value Kn corresponding to each metric can be obtained.

[0062] As in the foregoing example, using the formula in the circuit quality quantization model, the metric quality value Kn corresponding to the average delay can be obtained as Kn = (80 + (90 - 80) * (30 - 13) / (30 - 10)) * 40% = 35.4, the metric quality value Kn corresponding to the packet loss rate is Kn = (90 + (100 - 90) * (0.01 - 0) / (0.01 - 0)) * 30% = 30, and the metric quality value Kn corresponding to the average jitter is Kn = (80 + (90 - 80) * (30 - 15) / (30 - 10)) * 30% = 26.25.

[0063] Step S303: According to the metric quality value corresponding to each metric, obtain the circuit comprehensive quality result corresponding to the destination address to be tested.

[0064] In this embodiment, the metric quality values corresponding to each metric can be added together to obtain the circuit comprehensive quality result corresponding to the destination address to be tested. As in the foregoing example, the circuit comprehensive quality result Q corresponding to the destination address to be tested is Q = 35.4 + 30 + 26.25 = 91.65.

[0065] Step S304: Obtain the circuit comprehensive quality result corresponding to each destination address to be tested on the dedicated line circuit of the user to be tested, and take the average of the multiple circuit comprehensive quality results to obtain the total quality result of the dedicated line circuit of the user to be tested.

[0066] In this embodiment, the circuit comprehensive quality results Q1, Q2, ..., Q corresponding to each destination address to be tested on the dedicated line circuit of the tested user are obtained. n , take the average value of the comprehensive quality results of multiple circuits, and obtain the total quality result of the private line circuit of the user to be tested F = (Q1 + Q2 + .. + Q n ) / n.

[0067] In this embodiment, the user to be tested may use multiple dedicated line circuits, and the total quality results F1, F2, ..., F of each dedicated line circuit can be obtained respectively. m , take the average of the total quality results of multiple dedicated line circuits to obtain the network quality result of the user to be tested M = (F1 + F2 + .. + F m ) / m. The circuit quality testing device obtains the number of fault reports, complaints and thank-you letters within a preset statistical period of the user to be tested from the fault maintenance system, and uses the formula: perception comprehensive result = network quality result - 5*number of fault reports - 5*number of complaints + 5*number of thank-you letters to obtain the perception comprehensive result of the user to be tested. When the perception comprehensive result is less than the perception comprehensive result threshold, it is determined that the user to be tested is a poor perception user, and the dedicated line circuit of the user to be tested is optimized in a targeted manner. Exemplarily, the perception comprehensive result threshold can be 70.

[0068] In this embodiment, for each destination address to be tested, based on the circuit quality data corresponding to the destination address to be tested, a circuit quality quantization model is used to obtain the comprehensive circuit quality result corresponding to the destination address to be tested, and based on the comprehensive circuit quality result corresponding to each destination address to be tested, the total quality result of the dedicated line circuit of the user to be tested is obtained. The circuit quality data obtained by the test can be quantified to reflect the circuit quality more intuitively, making it possible to subsequently determine the poor quality circuit.

[0069] Figure 4 This is a flow chart of a third embodiment of a circuit quality testing method provided by the present application. Figure 2 or Figure 3 Based on the embodiment shown, see Figure 4 A specific implementation of step S204 is:

[0070] Step S401: Obtain the fault duration, number of repeated faults and bandwidth utilization peak value of the dedicated line circuit of the user to be tested within a preset statistical period, and use the formula: availability = (1-failure duration / 720)*100% to obtain the availability.

[0071] In this embodiment, the circuit quality testing device can obtain fault statistical data of the dedicated line circuit of the user to be tested within a preset statistical period from the fault maintenance system, including the fault duration and the number of repeated faults, and obtain bandwidth utilization data of the dedicated line circuit of the user to be tested within a preset statistical period from the dedicated line service direct needle system, including the bandwidth utilization peak.

[0072] Exemplarily, the preset statistical period can be 30 days. The fault duration of the dedicated line circuit of the tested user within the preset statistical period, that is, the total fault duration of the dedicated line circuit within 30 days, in hours; the number of repeated faults within the preset statistical period, that is, the number of faults of the dedicated line circuit within 30 days; the bandwidth utilization peak within the preset statistical period, that is, the maximum value of the bandwidth utilization peak of the dedicated line circuit within 30 days.

[0073] According to the fault duration in the preset statistical period, the availability rate can be obtained by using the formula: availability rate = (1-fault duration / 720)*100%.

[0074] Step S402: respectively obtaining the quality values ​​corresponding to the availability rate, fault duration, number of repeated faults, and bandwidth utilization peak value.

[0075] In this embodiment, the circuit quality test device can obtain the quality values ​​corresponding to the availability, fault duration, number of repeated faults, and bandwidth utilization peak value through the following Table 2. Among them, A represents the availability, B represents the fault duration, C represents the number of repeated faults, and D represents the bandwidth utilization peak value.

[0076] Table 2 Quality value table

[0077] Quality Value 0 -5 -10 -15 -20 Availability 100％ 99％<＝A<100％ 98％<＝A<99％ 97％<＝A<98％ A<97％ Fault duration (h) 0 0<B<＝4 4<B<＝8 8<B<＝24 24<B Repeated failure times 0 1 2 3 C>＝4 Peak bandwidth utilization D<＝60％ 60％<D<＝70％ 70％<D<＝80％ 80％<D<＝90％ 90％<D

[0078] Exemplarily, the fault duration obtained by the circuit quality testing device within a preset statistical period is 4 hours, the number of repeated faults is 2, and the bandwidth utilization peak is 65%. Using the formula availability = (1-fault duration / 720)*100%, the availability is 99.4%.

[0079] Using Table 2, we can obtain that the quality value corresponding to the availability is -5, the quality value corresponding to the fault duration is -5, the quality value corresponding to the number of repeated faults is -10, and the quality value corresponding to the bandwidth utilization peak is -5.

[0080] Step S403: Add the quality value corresponding to the availability rate, the quality value corresponding to the fault duration, the quality value corresponding to the number of repeated faults, and the quality value corresponding to the bandwidth utilization peak to the total quality result of the dedicated line circuit of the user to be tested to obtain the circuit comprehensive result of the dedicated line circuit of the user to be tested.

[0081] Exemplarily, the total quality result of the dedicated line circuit of the user to be tested is F=92, the quality value corresponding to the availability rate is -5, the quality value corresponding to the fault duration is -5, the quality value corresponding to the number of repeated faults is -10, and the quality value corresponding to the peak bandwidth utilization rate is -5. The quality value corresponding to the availability rate, the quality value corresponding to the fault duration, the quality value corresponding to the number of repeated faults, and the quality value corresponding to the peak bandwidth utilization rate are added to the total quality result of the dedicated line circuit of the user to be tested, and the comprehensive circuit result of the dedicated line circuit of the user to be tested is 92-5-5-10-5=67.

[0082] Step S404: when the circuit synthesis result is less than the circuit synthesis result threshold, it is determined that the dedicated line circuit of the user to be tested is a poor quality circuit, and the dedicated line circuit of the user to be tested is optimized accordingly.

[0083] Exemplarily, the circuit synthesis result threshold may be 70. When the circuit synthesis result is less than 70, it is determined that the dedicated line circuit of the user to be tested is a poor quality circuit, and the dedicated line circuit of the user to be tested is optimized accordingly.

[0084] In this embodiment, the circuit quality testing device determines the circuit quality from multiple dimensions based on the quantitative results of the circuit quality obtained, combined with the fault data and the bandwidth utilization data, and can more accurately determine the poor quality circuits, and then optimize the poor quality circuits accordingly.

[0085] Figure 5 This is a flow chart of a fourth embodiment of a circuit quality testing method provided by the present application. Figures 2 to 4 Based on any of the embodiments shown, see Figure 5 , the circuit quality testing method includes the following steps:

[0086] Step S501: obtaining multiple destination addresses to be tested on the dedicated line circuit of the user to be tested from a primary aggregation point or an aggregation switch.

[0087] Step S502: For each target address to be tested, an ICMP echo request message corresponding to the target address to be tested is generated, and the ICMP echo request message is sent to the terminal device corresponding to the target address to be tested, so as to receive an ICMP echo reply message returned by the terminal device.

[0088] Step S503: Obtain the average delay and average jitter corresponding to each destination address to be tested according to the sending time of the ICMP echo request message and the receiving time of the ICMP echo reply message corresponding to each destination address to be tested.

[0089] Step S504: Obtain the packet loss rate corresponding to each destination address to be tested according to the number of ICMP echo request messages and the number of ICMP echo reply messages corresponding to each destination address to be tested.

[0090] In this embodiment, the circuit quality testing device obtains multiple destination addresses to be tested on the dedicated line circuit of the user to be tested from the first-level aggregation point or aggregation switch. For each target address to be tested, the circuit quality testing device generates an ICMP echo request message corresponding to the target address to be tested, and sends the ICMP echo request message to the terminal device corresponding to the target address to be tested, so as to receive the ICMP echo reply message returned by the terminal device.

[0091] The circuit quality testing device obtains the average delay and average jitter corresponding to each target address to be tested according to the sending time of the ICMP echo request message and the receiving time of the ICMP echo reply message corresponding to each target address to be tested.

[0092] Specifically, the circuit quality test device sends N ICMP echo request messages to the terminal device corresponding to the target address to be tested, and obtains N round-trip delays T1, T2, ..., T according to the sending time of each ICMP echo request message and the receiving time of the ICMP echo reply message. N , thus, we can use the formula: average delay = (T1 + T2 + ... + T N ) / N, get the average delay; use the formula: average jitter = (|T2-T1|+..+|T N -T N-1 |) / (N-1) to obtain the average jitter.

[0093] The circuit quality test device obtains the packet loss rate corresponding to each destination address to be tested according to the number of ICMP echo request messages and the number of ICMP echo reply messages corresponding to each destination address to be tested. Specifically, the packet loss rate is obtained using the formula: packet loss rate = (number of packets sent - number of packets received) / number of packets sent.

[0094] Step S505: for each destination address to be tested, using the circuit quality quantification model, respectively determine the indicator interval and quality interval corresponding to each indicator in the circuit quality data corresponding to the destination address to be tested, the indicator including average delay, packet loss rate and average jitter.

[0095] Step S506: For each indicator, use the circuit quality quantification model to obtain the upper and lower limits of the indicator interval corresponding to the indicator, the upper and lower limits of the quality interval, and the weight, and use the formula in the circuit quality quantification model: Kn = (lower limit of the quality interval + difference between the upper and lower limits in the quality interval * (upper limit of the indicator interval - numerical value of the indicator) / difference between the upper and lower limits in the indicator interval) * weight to obtain the indicator quality value Kn corresponding to the indicator.

[0096] Step S507: according to the indicator quality value corresponding to each indicator, the circuit comprehensive quality result corresponding to the destination address to be tested is obtained.

[0097] Step S508: Obtain the circuit comprehensive quality result corresponding to each destination address to be tested on the dedicated line circuit of the user to be tested, average multiple circuit comprehensive quality results, and obtain the total quality result of the dedicated line circuit of the user to be tested.

[0098] Step S509: Obtain the fault duration, number of repeated faults and bandwidth utilization peak value of the dedicated line circuit of the user to be tested within a preset statistical period, and use the formula: availability = (1-failure duration / 720)*100% to obtain the availability.

[0099] Step S510: respectively obtaining the quality values ​​corresponding to the availability rate, fault duration, number of repeated faults and bandwidth utilization peak value.

[0100] Step S511: Add the quality value corresponding to the availability rate, the quality value corresponding to the fault duration, the quality value corresponding to the number of repeated faults, and the quality value corresponding to the bandwidth utilization peak to the total quality result of the dedicated line circuit of the user to be tested to obtain the circuit comprehensive result of the dedicated line circuit of the user to be tested.

[0101] Step S512: When the circuit synthesis result is less than the circuit synthesis result threshold, it is determined that the dedicated line circuit of the user to be tested is a poor quality circuit, and the dedicated line circuit of the user to be tested is optimized accordingly.

[0102] In this embodiment, the circuit quality testing device obtains multiple destination addresses to be tested on the dedicated line circuit of the user to be tested from the first-level aggregation point or aggregation switch, and initiates tests to the terminal devices corresponding to the destination addresses to be tested respectively, and obtains the circuit quality data corresponding to each destination address to be tested, which provides a prerequisite for subsequent quantification of the circuit quality data and further determination of poor quality circuits.

[0103] The following is an embodiment of the device of the present application, which can be used to execute the embodiment of the method of the present application. For details not disclosed in the embodiment of the device of the present application, please refer to the embodiment of the method of the present application.

[0104] Figure 6 A schematic diagram of a circuit quality testing device embodiment provided in the present application; Figure 6 As shown, the circuit quality testing device 60 includes: a testing module 61 , a quantification module 62 and a processing module 63 . Among them, the testing module 61 is used to obtain multiple destination addresses to be tested on the dedicated line circuit of the user to be tested from the first-level aggregation point or the aggregation switch, and send test requests to the terminal devices corresponding to the destination addresses to be tested respectively to obtain the circuit quality data corresponding to each destination address to be tested; the quantification module 62 is used to obtain the comprehensive quality result of the circuit corresponding to the destination address to be tested for each destination address to be tested using a circuit quality quantification model according to the circuit quality data corresponding to the destination address to be tested; wherein the circuit quality quantification model includes the weight, indicator interval and quality interval corresponding to each indicator in the circuit quality data; the quantification module 62 is also used to obtain the total quality result of the dedicated line circuit of the user to be tested according to the comprehensive quality result of the circuit corresponding to each destination address to be tested; the processing module 63 is used to optimize the dedicated line circuit of the user to be tested accordingly when it is determined that the dedicated line circuit of the user to be tested is a poor quality circuit according to the total quality result of the dedicated line circuit of the user to be tested, and the fault statistical data and bandwidth utilization data of the dedicated line circuit of the user to be tested obtained within a preset statistical period.

[0105] The circuit quality testing device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment, and its implementation principle and beneficial effects are similar, which will not be repeated here.

[0106] In a possible implementation scheme, the quantization module 62 is specifically used to determine, for each destination address to be tested, the indicator interval and quality interval corresponding to each indicator in the circuit quality data corresponding to the destination address to be tested using a circuit quality quantization model; for each indicator, using the circuit quality quantization model, obtain the upper limit and lower limit of the indicator interval corresponding to the indicator, the upper limit and lower limit of the quality interval, and the weight, and use the formula in the circuit quality quantization model: Kn = (lower limit of the quality interval + difference between the upper limit and lower limit in the quality interval * (upper limit of the indicator interval - numerical value of the indicator) / difference between the upper limit and lower limit in the indicator interval) * weight to obtain the indicator quality value Kn corresponding to the indicator; and according to the indicator quality value corresponding to each indicator, obtain the comprehensive circuit quality result corresponding to the destination address to be tested.

[0107] In a possible implementation, the indicator includes average delay, packet loss rate and average jitter.

[0108] The circuit quality testing device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment, and its implementation principle and beneficial effects are similar, which will not be repeated here.

[0109] In a possible implementation, the quantification module 62 is specifically used to obtain the comprehensive circuit quality result corresponding to each destination address to be tested on the dedicated line circuit of the user to be tested, take the average of multiple circuit comprehensive quality results, and obtain the total quality result of the dedicated line circuit of the user to be tested.

[0110] The circuit quality testing device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment, and its implementation principle and beneficial effects are similar, which will not be repeated here.

[0111] In a possible implementation scheme, the processing module 63 is specifically used to obtain the fault duration, repeated fault number and bandwidth utilization peak value of the dedicated line circuit of the user to be tested within a preset statistical period, and use the formula: availability = (1-fault duration / 720)*100% to obtain the availability; respectively obtain the quality values ​​corresponding to the availability, fault duration, repeated fault number and bandwidth utilization peak value; add the quality value corresponding to the availability, the quality value corresponding to the fault duration, the quality value corresponding to the repeated fault number and the quality value corresponding to the bandwidth utilization peak value to the total quality result of the dedicated line circuit of the user to be tested to obtain the circuit comprehensive result of the dedicated line circuit of the user to be tested; when the circuit comprehensive result is less than the circuit comprehensive result threshold, it is determined that the dedicated line circuit of the user to be tested is a poor quality circuit, and the dedicated line circuit of the user to be tested is optimized accordingly.

[0112] The circuit quality testing device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment, and its implementation principle and beneficial effects are similar, which will not be repeated here.

[0113] In a possible implementation scheme, the test module 61 is specifically used to obtain multiple destination addresses to be tested on the dedicated line circuit of the user to be tested from a first-level aggregation point or an aggregation switch; for each target address to be tested, an ICMP echo request message corresponding to the target address to be tested is generated, and the ICMP echo request message is sent to the terminal device corresponding to the target address to be tested to receive the ICMP echo reply message returned by the terminal device; the average delay and average jitter corresponding to each destination address to be tested are obtained according to the sending time of the ICMP echo request message and the receiving time of the ICMP echo reply message corresponding to each target address to be tested; the packet loss rate corresponding to each destination address to be tested is obtained according to the number of ICMP echo request messages and the number of ICMP echo reply messages corresponding to each target address to be tested.

[0114] The circuit quality testing device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment, and its implementation principle and beneficial effects are similar, which will not be repeated here.

[0115] Figure 7 A schematic diagram of the structure of a server provided in this application. Figure 7 As shown, the server 70 includes: a processor 71, a memory 72, and a communication interface 73; wherein the memory 72 is used to store executable instructions of the processor 71; the processor 71 is configured to execute the technical solution in any of the aforementioned method embodiments by executing the executable instructions.

[0116] Optionally, the memory 72 can be independent or integrated with the processor 71.

[0117] Optionally, when the memory 72 is a device independent of the processor 71, the server 70 may further include: a bus 74 for connecting the above devices.

[0118] The server is used to execute the technical solution in any of the aforementioned method embodiments, and its implementation principle and technical effect are similar and will not be repeated here.

[0119] An embodiment of the present application also provides a readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the technical solution provided by any of the aforementioned embodiments is implemented.

[0120] An embodiment of the present application also provides a computer program product, including a computer program, which is used to implement the technical solution provided by any of the aforementioned method embodiments when the computer program is executed by a processor.

[0121] Those skilled in the art can understand that all or part of the steps of implementing the above-mentioned method embodiments can be completed by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned storage medium includes: ROM, RAM, disk or optical disk and other media that can store program codes.

[0122] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for testing circuit quality, characterized in that: include: Acquire multiple destination addresses to be tested on the dedicated line circuit of the user to be tested from the first-level aggregation point or aggregation switch, and send test requests to the terminal devices corresponding to the destination addresses to be tested respectively to obtain circuit quality data corresponding to each destination address to be tested; For each destination address to be tested, according to the circuit quality data corresponding to the destination address to be tested, a circuit quality quantification model is used to obtain a comprehensive circuit quality result corresponding to the destination address to be tested; wherein the circuit quality quantification model includes a weight, an indicator interval and a quality interval corresponding to each indicator in the circuit quality data; According to the comprehensive quality result of the circuit corresponding to each destination address to be tested, the total quality result of the dedicated line circuit of the user to be tested is obtained; According to the total quality result of the dedicated line circuit of the user to be tested, and the fault statistical data and bandwidth utilization data of the dedicated line circuit of the user to be tested acquired within a preset statistical period, when it is determined that the dedicated line circuit of the user to be tested is a poor-quality circuit, the dedicated line circuit of the user to be tested is optimized accordingly; For each destination address to be tested, obtaining a comprehensive circuit quality result corresponding to the destination address to be tested by using a circuit quality quantification model according to circuit quality data corresponding to the destination address to be tested, including: For each destination address to be tested, using a circuit quality quantification model, respectively determining an indicator interval and a quality interval corresponding to each indicator in the circuit quality data corresponding to the destination address to be tested; For each indicator, the circuit quality quantification model is used to obtain the upper limit and lower limit of the indicator interval corresponding to the indicator, the upper limit and lower limit of the quality interval, and the weight, and the formula in the circuit quality quantification model is used: Kn = (lower limit of quality interval + difference between upper and lower limits in quality interval * (upper limit of index interval - index value) / difference between upper and lower limits in index interval) * weight Obtaining an indicator quality value Kn corresponding to the indicator; According to the indicator quality value corresponding to each indicator, the circuit comprehensive quality result corresponding to the destination address to be tested is obtained.

2. The circuit quality testing method according to claim 1, characterized in that: The indicators include average delay, packet loss rate and average jitter.

3. The circuit quality testing method according to claim 2, characterized in that: The step of obtaining the total quality result of the dedicated line circuit of the user to be tested according to the comprehensive quality result of the circuit corresponding to each destination address to be tested includes: The circuit comprehensive quality result corresponding to each destination address to be tested on the dedicated line circuit of the user to be tested is obtained, and the average value of multiple circuit comprehensive quality results is taken to obtain the total quality result of the dedicated line circuit of the user to be tested.

4. The circuit quality testing method according to claim 3, characterized in that: The method comprises: performing corresponding optimization processing on the dedicated line circuit of the user to be tested according to the total quality result of the dedicated line circuit of the user to be tested, and the acquired fault statistical data and bandwidth utilization data of the dedicated line circuit of the user to be tested within a preset statistical period, when it is determined that the dedicated line circuit of the user to be tested is a poor quality circuit, including: Obtain the fault duration, number of repeated faults and peak bandwidth utilization rate of the dedicated line circuit of the user to be tested within a preset statistical period, and use the formula: Availability = (1-failure duration / 720)*100%, Get availability rate; Respectively obtain the quality values ​​corresponding to the availability, fault duration, number of repeated faults, and bandwidth utilization peak; Add the quality value corresponding to the availability, the quality value corresponding to the fault duration, the quality value corresponding to the number of repeated faults, and the quality value corresponding to the bandwidth utilization peak value to the total quality result of the dedicated line circuit of the user to be tested, to obtain a circuit comprehensive result of the dedicated line circuit of the user to be tested; When the circuit synthesis result is less than the circuit synthesis result threshold, it is determined that the dedicated line circuit of the user to be tested is a poor quality circuit, and the dedicated line circuit of the user to be tested is optimized accordingly.

5. The circuit quality testing method according to claim 2, characterized in that: The method of obtaining multiple destination addresses to be tested on the dedicated line circuit of the user to be tested from the first-level aggregation point or the aggregation switch, and sending test requests to the terminal devices corresponding to the destination addresses to be tested respectively to obtain circuit quality data corresponding to each destination address to be tested, includes: Obtain multiple destination addresses to be tested on the dedicated line circuit of the user to be tested from the first-level aggregation point or aggregation switch; For each target address to be tested, generate an ICMP echo request message corresponding to the target address to be tested, and send the ICMP echo request message to the terminal device corresponding to the target address to be tested, so as to receive an ICMP echo reply message returned by the terminal device; Obtain the average delay and average jitter corresponding to each destination address to be tested according to the sending time of the ICMP echo request message and the receiving time of the ICMP echo reply message corresponding to each destination address to be tested; The packet loss rate corresponding to each destination address to be tested is obtained according to the number of ICMP echo request messages and the number of ICMP echo reply messages corresponding to each destination address to be tested.

6. A circuit quality testing device, characterized in that: include: The test module is used to obtain multiple destination addresses to be tested on the dedicated line circuit of the user to be tested from the first-level aggregation point or the aggregation switch, and send test requests to the terminal devices corresponding to the destination addresses to be tested respectively to obtain the circuit quality data corresponding to each destination address to be tested; A quantization module, for obtaining, for each destination address to be tested, a comprehensive circuit quality result corresponding to the destination address to be tested using a circuit quality quantization model according to the circuit quality data corresponding to the destination address to be tested; wherein the circuit quality quantization model includes a weight, an indicator interval, and a quality interval corresponding to each indicator in the circuit quality data; The quantification module is further used to obtain the total quality result of the private line circuit of the user to be tested according to the comprehensive quality result of the circuit corresponding to each destination address to be tested; A processing module, configured to optimize the dedicated line circuit of the user to be tested accordingly when it is determined that the dedicated line circuit of the user to be tested is a poor-quality circuit, based on the total quality result of the dedicated line circuit of the user to be tested, and the acquired fault statistical data and bandwidth utilization data of the dedicated line circuit of the user to be tested within a preset statistical period; The quantization module is specifically used for: For each destination address to be tested, using a circuit quality quantification model, respectively determining an indicator interval and a quality interval corresponding to each indicator in the circuit quality data corresponding to the destination address to be tested; For each indicator, the circuit quality quantification model is used to obtain the upper limit and lower limit of the indicator interval corresponding to the indicator, the upper limit and lower limit of the quality interval, and the weight, and the formula in the circuit quality quantification model is used: Kn = (lower limit of quality interval + difference between upper and lower limits in quality interval * (upper limit of index interval - index value) / difference between upper and lower limits in index interval) * weight Obtaining an indicator quality value Kn corresponding to the indicator; According to the indicator quality value corresponding to each indicator, the circuit comprehensive quality result corresponding to the destination address to be tested is obtained.

7. The circuit quality testing device according to claim 6, characterized in that: The indicators include average delay, packet loss rate and average jitter.

8. The circuit quality testing device according to claim 7, characterized in that: The quantization module is specifically used for: The circuit comprehensive quality result corresponding to each destination address to be tested on the dedicated line circuit of the user to be tested is obtained, and the average value of multiple circuit comprehensive quality results is taken to obtain the total quality result of the dedicated line circuit of the user to be tested.

9. The circuit quality testing device according to claim 8, characterized in that: The processing module is specifically used for: Obtain the fault duration, number of repeated faults and peak bandwidth utilization rate of the dedicated line circuit of the user to be tested within a preset statistical period, and use the formula: Availability = (1-failure duration / 720)*100%, Get availability rate; Respectively obtain the quality values ​​corresponding to the availability, fault duration, number of repeated faults, and bandwidth utilization peak; Add the quality value corresponding to the availability, the quality value corresponding to the fault duration, the quality value corresponding to the number of repeated faults, and the quality value corresponding to the bandwidth utilization peak value to the total quality result of the dedicated line circuit of the user to be tested, to obtain a circuit comprehensive result of the dedicated line circuit of the user to be tested; When the circuit synthesis result is less than the circuit synthesis result threshold, it is determined that the dedicated line circuit of the user to be tested is a poor quality circuit, and the dedicated line circuit of the user to be tested is optimized accordingly.

10. The circuit quality testing device according to claim 7, characterized in that: The test module is specifically used for: Obtain multiple destination addresses to be tested on the dedicated line circuit of the user to be tested from the first-level aggregation point or aggregation switch; For each target address to be tested, generate an ICMP echo request message corresponding to the target address to be tested, and send the ICMP echo request message to the terminal device corresponding to the target address to be tested, so as to receive an ICMP echo reply message returned by the terminal device; Obtain the average delay and average jitter corresponding to each destination address to be tested according to the sending time of the ICMP echo request message and the receiving time of the ICMP echo reply message corresponding to each destination address to be tested; The packet loss rate corresponding to each destination address to be tested is obtained according to the number of ICMP echo request messages and the number of ICMP echo reply messages corresponding to each destination address to be tested.

11. A server, characterized in that: include: Processor, memory, communication interface; The memory is used to store executable instructions of the processor; The processor is configured to perform the circuit quality testing method according to any one of claims 1 to 5 by executing the executable instructions.

12. A readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the circuit quality testing method according to any one of claims 1 to 5 is implemented.

13. A circuit quality testing system, characterized in that: include: A circuit quality testing device, a primary aggregation point, an aggregation switch, and a terminal device as claimed in any one of claims 6 to 10; The first-level aggregation point is a broadband access server BRAS or a full-service router SR.

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