High-reliability bit correction method and device for high-speed LVDS data of CMOS image sensor

Abstract

The application relates to the field of image correction, in particular to a high-reliability bit correction method and device for high-speed LVDS data of a CMOS image sensor, which comprises the following steps: the delay of a surrounding delay unit is adjusted by changing the tap delay value of a delay adjustment module to change the sampling position in a data eye diagram; under the premise of tap delay resolution determination, one complete data eye diagram period can be described by the number of tap delay values; tap delay value data is compared, and the current sampling position is determined to be in an eye diagram transition zone when the data changes before and after; after the eye diagram transition zone is found, a detection window is set to find the boundary from the transition zone to a stable zone; the tap delay value is adjusted to make the sampling position in the stable zone, and the boundary of the transition zone after the stable zone is continuously found; the center sampling position of the eye diagram stable zone is calculated, and correction is completed. The method can obtain accurate bit correction results in a relatively short bit correction time, and is high in reliability.

Description

Technical Field

[0001] This application relates to the field of image correction, and more specifically, to a high-reliability bit correction method and apparatus for high-speed LVDS data based on a CMOS image sensor. Background Technology

[0002] In recent years, CMOS (Complementary Metal-Oxide-Semiconductor) image sensor technology has advanced rapidly, and the sensitivity of CMOS image sensors has approached the level of scientific-grade CCD image sensors. In the field of scientific imaging, the application of CMOS image sensors is becoming increasingly widespread. Unlike CCD devices, in CMOS devices, the signal charge is transmitted to the corresponding analog signal processing unit under the action of the row and column control unit for signal amplification. Then, through an ADC directly connected to each pixel, analog-to-digital conversion is performed, converting the analog signal into a digital signal output within the chip. This structure determines that CMOS devices generally use a multi-channel parallel readout method, characterized by high data transmission rate and high frame rate. In recent years, mainstream CMOS devices have adopted multi-channel LVDS readout for image data readout, with single-channel serial rates reaching over 600 Mbit / s, significantly improving data output efficiency. However, due to the influence of detector channel mismatch, PCB distribution parameters, or external factors such as temperature and voltage, the phase relationship between the high-speed serial data and the clock at the receiving end can change unpredictably during multi-channel LVDS readout, resulting in data distortion. To ensure that the high-speed LVDS serial data transmitted by CMOS can be sampled correctly, the data eye diagram center needs to be aligned with the sampling clock at the receiving end, which is called bit correction.

[0003] Traditional bit correction methods utilize the delay unit of an FPGA to adjust delay parameters, increasing the number of samples to eliminate the influence of random jitter. This involves repeating sampling nearly ten thousand times at the same delay position and determining the stability of the sampled data to find the effective window boundary of the eye diagram. While this method achieves correction, it suffers from the following problems: 1) It does not consider the fixed jitter caused by periodic interference. Experiments show that there are transiently stable data states within the eye diagram transition region. In such cases, traditional bit correction methods will yield incorrect correction results, leading to noise in the output image; 2) It requires thousands or even tens of thousands of comparisons at each delay position, consuming a significant amount of correction time and causing slow startup of the imaging system.

[0004] Therefore, although traditional bit correction methods are simple to implement, they are not very reliable and are not suitable for high-reliability fields such as aerospace. There is an urgent need to design a more stable and reliable bit correction strategy for high-speed LVDS data of CMOS image sensors.

[0005] Therefore, existing technologies still have shortcomings and need further development. Summary of the Invention

[0006] This application provides a highly reliable bit correction method and apparatus for high-speed LVDS data from a CMOS image sensor. It obtains accurate bit correction results within a relatively short bit correction time and avoids the situation where the data eye diagram transition area is mistakenly identified as a stable area, resulting in image noise, thereby improving the reliability of the correction algorithm.

[0007] According to an embodiment of this application, a high-reliability bit correction method for high-speed LVDS data from a CMOS image sensor is provided, comprising the following steps:

[0008] The delay of the surrounding delay unit is adjusted by changing the tap delay value of the delay adjustment module, thereby changing the sampling position in the data eye diagram. Given a fixed tap delay resolution, a complete data eye diagram cycle can be equivalently described by the number of tap delay values.

[0009] By comparing the tap delay values, changes in the data can be identified as indicating that the current sampling position is in the eye diagram transition zone.

[0010] After locating the eye diagram transition region, the boundary between the transition region and the stable region is found by setting the detection window;

[0011] Adjust the tap delay value so that the sampling position is located after the stable region, and continue to find the boundary of the transition region after the stable region;

[0012] Calculate the center sampling position of the eye diagram's stable region and complete the correction.

[0013] Preferably, the specific steps for finding the boundary between the transition region and the stable region by setting a detection window after finding the eye diagram transition region are as follows:

[0014] A sampling detection window is formed by M tap delay values ​​to find the boundary between the transition region and the stable region.

[0015] Let the minimum time width of the stable region of the data eye diagram be equivalent to K tap delay values, and the maximum time width of the "bubble" quasi-stable region be equivalent to P tap delay values. If the detection window is set to sample M tap delay values, the equivalent time width of the detection window composed of M tap delay values ​​should satisfy the following:

[0016] (P+1)*tap<M*tap<(K-1)*tap;

[0017] In the above formula, 1 < P < K and (P+5) < K, where P and K are both integers;

[0018] Compare the data from M samplings. Only when the sampling data at M positions within the detection window are equal is it considered that the data eye diagram has entered a stable region. The actual tap delay value at the boundary between the transition region and the stable region is stored in the Tap_reg1 register, and the current tap delay value is reduced by M.

[0019] Preferably, the specific steps for adjusting the tap delay value to place the sampling position in the stable region, and then finding the boundary of the transition region after the stable region, are as follows:

[0020] Adjust the tap delay value so that the sampling position is in the stable region. Continue to find the boundary of the transition region after the stable region. When the current data is not equal to the temporary register data, it can be considered that the boundary of the transition region after the stable region has been found. The current tap delay value is stored in the Tap_reg2 register.

[0021] Preferably, the specific steps for calculating the sampling position of the center of the eye diagram stabilization region are as follows:

[0022] The sampling position at the center of the eye diagram stable region is Taps = (Tap_reg2 - Tap_reg1) / 2.

[0023] The calibration is now complete;

[0024] When the CMOS sensor fails or other factors cause the transmission of LVDS data to fail, it will be judged as a correction failure.

[0025] According to another embodiment of this application, a high-reliability bit correction device for high-speed LVDS data from a CMOS image sensor is provided, including a CMOS image sensor and an FPGA device. The output terminal of the CMOS image sensor is connected to the FPGA device through multiple channels. The FPGA device includes a bit correction control module, a delay adjustment module, and a serial-to-parallel conversion module. The output terminal of the CMOS image sensor is connected to the delay adjustment module, the output terminal of the bit correction control module is connected to the delay adjustment module, and the output terminal of the delay adjustment module is connected to the serial-to-parallel conversion module. By changing the tap delay value of the delay adjustment module, the delay of the surrounding delay unit is adjusted to change the sampling position in the data eye diagram. Under the premise that the tap delay resolution is determined, a complete data eye diagram cycle can be equivalently described by the number of tap delay values.

[0026] Preferably, the CMOS image sensor is a large-area, high-sensitivity back-illuminated sensor.

[0027] Preferably, the FPGA device should be a model with a clock frequency higher than that of the LVDS serial data rate of the CMOS image sensor.

[0028] Preferably, the delay adjustment module of the FPGA device has a surround delay unit with 64 or 32 tap delay values.

[0029] Preferably, the tap delay resolution of the surround delay unit of the delay adjustment module of the FPGA device is 78ps or 52ps.

[0030] The beneficial effects of this application are as follows: 1) The high-reliability bit correction method for high-speed LVDS data of CMOS image sensor described in this application can complete the bit alignment operation of high-speed LVDS data. This method can complete the bit correction independently by the receiving FPGA without relying on the LVDS accompanying clock output by the CMOS image sensor, thus avoiding cross-clock domain problems; 2) The method of this application can improve the reliability of bit correction. By setting a detection window to find the boundary between the transition region and the stable region, compared with the method of multiple sampling and comparison at the same time, the method of this application can avoid miscorrection caused by the "bubble" quasi-stable region inside the data eye diagram transition region, effectively solving the problem of random noise in the image; 3) The method of this application uses a detection window for sampling and comparison, avoiding a large number of repeated samplings at the same delay position, shortening the number of sampling and comparisons, and reducing the bit correction time; 4) The jump mechanism of the method of this application can be used for fault detection, avoiding the dead loop phenomenon caused by correction failure in traditional methods. Attached Figure Description

[0031] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0032] Figure 1 This is a schematic diagram of a high-reliability bit correction method for high-speed LVDS data of CMOS image sensors provided in this application;

[0033] Figure 2 This is a block diagram of the bit correction module inside the FPGA device of this application;

[0034] Figure 3 This is a schematic diagram of the data eye diagram and data delay sampling principle of this application;

[0035] Figure 4 This is a flowchart of the bit correction strategy for this application. Detailed Implementation

[0036] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0037] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0038] Example 1

[0039] This application relates to the field of image correction and mainly addresses the following existing technical problems: Traditional correction methods 1) do not consider the fixed jitter caused by periodic interference. Through experiments, it is not difficult to find that there is a situation where the data is transiently stable inside the eye diagram transition area. At this time, the traditional bit correction method will obtain incorrect correction results, resulting in noise in the output image; 2) It is necessary to compare thousands or even tens of thousands of times at each delay position, which consumes a lot of correction time and causes the imaging system to start up slowly.

[0040] Based on the existing technical problems, one embodiment of this application provides a high-reliability bit correction method for high-speed LVDS data of CMOS image sensors. The principle is to adjust the delay of LVDS serial data through a delay adjustment module (IDELAYE2 source code) so that the serial-to-parallel conversion module (ISERDES source code) obtains the correct sampling position during conversion.

[0041] The delay of the surround delay unit can be adjusted by changing the input parameter CNTVALUEIN of the delay adjustment module (IDELAYE2) to change... Figure 3The sampling positions in the eye diagram described herein are referred to as tap delay values, hereinafter referred to as CNTVALUEIN parameters. Given a fixed tap delay resolution, a complete data eye diagram cycle can be equivalently described by the number of tap delay values. For example, when the tap delay resolution is 78 ps, a data eye diagram with a cycle of 1.667 ns can be described as having a cycle of 21 taps. To avoid missed sampling, when selecting the tap delay resolution, it must be ensured that the product of the total number of surround delay cells and the delay resolution is greater than a complete data eye diagram cycle.

[0042] S100: By comparing the tap delay value data, the change in the data can be used to determine that the current sampling position is in the eye diagram transition area;

[0043] Specifically, upon power-on, the tap delay value of the surround delay unit is 0, corresponding to... Figure 3 The sampling position of the data eye diagram is random. Regardless of the sampling position, the first step is to find the transition zone of the data eye diagram. The specific strategy is to compare the data before and after the tap delay. If a change is found in the data, it can be determined that the current sampling position is in the transition zone.

[0044] S200: After finding the eye diagram transition region, the boundary between the transition region and the stable region is found by setting the detection window;

[0045] Specifically, after finding the eye diagram transition region, it is necessary to further locate the boundary between the transition region and the stable region, that is, to find... Figure 3 At time T1 in the waveform analysis, it can be seen that the data within the eye diagram transition region is not constantly changing randomly, but rather exhibits a temporary stable region shaped like a "bubble" (the "bubble" temporary stable region). Figure 3 The time interval from T5 to T6 in the data eye diagram is the "bubble" quasi-stable region. Multiple samplings of the same tap delay value within the "bubble" show no change in data, similar to the stable region. If the transition and stable regions are determined by comparing multiple samples of a single tap delay value, then the period from T5 to T6 would be considered the stable region, leading to the sampling position being set at the midpoint between T5 and T6, resulting in erroneous data and noise. This application uses a sampling detection window composed of M tap delays to find the boundary between the transition and stable regions, thus avoiding interference from the "bubble" quasi-stable region. Let the minimum time width of the stable region of the data eye diagram be equivalent to K tap delay values, and the maximum time width of the "bubble" quasi-stable region be equivalent to P tap delay values. The detection window is set to sample M tap delay values. The equivalent time width of the detection window composed of M tap delays should satisfy:

[0046] (P+1)*tap<M*tap<(K-1)*tap;

[0047] In the above formula, 1 < P < K and (P+5) < K. P and K are both integers.

[0048] According to CMOS datasheets, actual waveform measurements, and LVDS transmission theory, assuming no hardware design issues, at least (P+5) < K should be satisfied; otherwise, stable data reception cannot be guaranteed. This condition can also be considered the minimum requirement for stable LVDS data reception.

[0049] The tap delay value is increased M times to obtain Figure 3 The sampling window, marked TAPw, collects data 32 times at each sampling position within the window. The M samples are compared, and only when the sampled data at all M positions within the detection window are equal is the data considered to have entered the stable region of the data eye diagram. The actual tap delay value at the boundary between the transition region and the stable region is the current tap delay value stored in the Tap_reg1 register minus M, i.e. Figure 3 Position at time T1.

[0050] S300: Adjust the tap delay value so that the sampling position is after the stable region, and continue to find the boundary of the transition region after the stable region;

[0051] Specifically, after adjusting the tap delay value to place the sampling position in the stable region, it is necessary to find the boundary of the transition region after the stable region, that is... Figure 3 The position at time T2. The search strategy is that if the current data is not equal to the data in temporary register 3, the boundary of the transition region T2 after the stable region can be considered to have been found. The current tap delay value is stored in the Tap_reg2 register.

[0052] S400: Calculate the center sampling position of the eye diagram stable region and complete the correction.

[0053] Specifically, calculate the sampling position Tap at the center of the eye diagram stabilization region. s for:

[0054] Tap s = (Tap_reg2-Tap_reg1) / 2.

[0055] The character correction is now complete.

[0056] When the CMOS sensor fails or other factors cause the transmission of LVDS data to fail, it will be transmitted through... Figure 4 The loop exit mechanism in the code indicates that the correction has failed.

[0057] The specific implementation methods of this application are described in detail below.

[0058] To ensure the correct implementation of the bit correction method in this application, impedance matching and signal integrity of LVDS transmission lines must be considered during PCB design. LVDS transmission lines must be routed in a differential pair manner with equal lengths. Under reasonable hardware design conditions, the minimum transmission requirement of (P+5) < K can be achieved.

[0059] Taking an eye diagram with a stable region length greater than 10 tap delay values ​​and a known maximum "bubble" quasi-stable region of 4 tap delay values ​​as an example, the detection window can be set to sample at 8 tap delay values, requiring the tap delay value to increase 8 times to obtain... Figure 3 The sampling window marked TAPw collects 32 data points at each sampling position within the window. The data from the 8 samples are compared. Only when the sampled data at all 8 positions within the detection window are equal is it considered that the data eye diagram has entered the stable region. The actual tap delay value at the boundary between the transition region and the stable region is the current tap delay value stored in the Tap_reg1 register minus 8, which is the boundary position between the transition region and the stable region.

[0060] In some embodiments, when calculating the tap value at the center position of the stable region of the data eye diagram, the magnitude of the values ​​in the Tap_reg1 and Tap_reg2 registers needs to be considered. Since the tap value increments in a 0-31 cycle pattern, there may be a case where Tap_reg2 < Tap_reg1. In the design of the specific calculation method, it is possible to first determine whether the tap value increment crosses its own cycle by checking the value in Tap_reg2, and then use different methods to calculate the center position tap value according to the two different cases.

[0061] In some embodiments, when the calculated tap value at the center of the stable region of the data eye diagram is greater than 31, it should be corrected according to its periodicity so that it is within the effective data range of 0 to 31.

[0062] The beneficial effects of this application are as follows: 1) The high-reliability bit correction method for high-speed LVDS data of CMOS image sensor described in this application can complete the bit alignment operation of high-speed LVDS data. This method can complete the bit correction independently by the receiving FPGA without relying on the LVDS accompanying clock output by the CMOS image sensor, thus avoiding cross-clock domain problems; 2) The method of this application can improve the reliability of bit correction. By setting a detection window to find the boundary between the transition region and the stable region, compared with the method of multiple sampling and comparison at the same time, the method of this application can avoid miscorrection caused by the "bubble" quasi-stable region inside the data eye diagram transition region, effectively solving the problem of random noise in the image; 3) The method of this application uses a detection window for sampling and comparison, avoiding a large number of repeated samplings at the same delay position, shortening the number of sampling and comparisons, and reducing the bit correction time; 4) The jump mechanism of the method of this application can be used for fault detection, avoiding the dead loop phenomenon caused by correction failure in traditional methods.

[0063] Example 2

[0064] According to another embodiment of this application, a high-reliability bit correction device for high-speed LVDS data from a CMOS image sensor is provided, including a CMOS image sensor, an FPGA device, and an LVDS transmission line. The output terminal of the CMOS image sensor is connected to the FPGA device through multiple channels. The FPGA device includes a bit correction control module, a delay adjustment module, and a serial-to-parallel conversion module. The output terminal of the CMOS image sensor is connected to the delay adjustment module, the output terminal of the bit correction control module is connected to the delay adjustment module, and the output terminal of the delay adjustment module is connected to the serial-to-parallel conversion module. By changing the tap delay value of the delay adjustment module, the delay of the surrounding delay unit is adjusted to change the sampling position in the data eye diagram. Under the premise that the tap delay resolution is determined, a complete data eye diagram cycle can be equivalently described by the number of tap delay values.

[0065] In some embodiments, the CMOS image sensor is a large-area frame high-sensitivity back-illuminated sensor.

[0066] In some embodiments, the LVDS transmission lines are routed with equal lengths on the PCB and signal integrity analysis is performed according to the LVDS standard impedance matching parameters.

[0067] In some embodiments, the FPGA device needs to be a model with a clock frequency higher than the LVDS serial data rate of the CMOS image sensor.

[0068] In some embodiments, the delay adjustment module of the FPGA device has a surround delay unit with 64 tap delay values.

[0069] In some embodiments, the delay adjustment module of the FPGA device has a surround delay unit with 32 tap delay values.

[0070] In some embodiments, the tap delay resolution of the surround delay unit of the delay adjustment module of the FPGA device is 78ps.

[0071] In some embodiments, the tap delay resolution of the surround delay unit of the delay adjustment module of the FPGA device is 52ps.

[0072] The device of this application can obtain accurate bit correction results in a relatively short bit correction time and avoid the situation where the data eye diagram transition area is misjudged as a stable area, resulting in image noise, thereby improving the reliability of the bit correction algorithm.

[0073] The above description is only a preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A high-reliability bit correction method for high-speed LVDS data from a CMOS image sensor, characterized in that, Includes the following steps: The delay of the surrounding delay unit is adjusted by changing the tap delay value of the delay adjustment module, thereby changing the sampling position in the data eye diagram. Under the premise that the tap delay resolution is determined, a complete data eye diagram cycle is equivalent to the number of tap delay values. By comparing the tap delay values, changes in the data can be identified as indicating that the current sampling position is in the eye diagram transition zone. After locating the eye diagram transition region, the boundary between the transition region and the stable region is found by setting the detection window; Adjust the tap delay value so that the sampling position is located after the stable region, and continue to find the boundary of the transition region after the stable region; Calculate the center sampling position of the eye diagram stabilization region and complete the correction; After finding the eye diagram transition region, the specific steps for finding the boundary between the transition region and the stable region by setting a detection window are as follows: A sampling detection window is formed by M tap delay values ​​to find the boundary between the transition region and the stable region. Let the minimum time width of the stable region of the data eye diagram be equivalent to K tap delay values, and the maximum time width of the "bubble" quasi-stable region be equivalent to P tap delay values. If the detection window is set to sample M tap delay values, the equivalent time width of the detection window composed of M tap delay values ​​should satisfy: (P+1)*tap<M*tap<(K-1)*tap; In the above formula, 1 < P < K and (P+5) < K, where P and K are both integers; Compare the data from M samplings. When the sampling data at M positions within the detection window are equal, it is considered that the data eye diagram has entered a stable region. The actual tap delay value at the boundary between the transition region and the stable region is the current tap delay value stored in the Tap_reg1 register minus M. The "bubble" stabilization zone is the part of the eye diagram transition zone where the internal data is not constantly changing randomly, and the data of the same tap delay value remains unchanged when sampled multiple times.

2. The high-reliability bit correction method for high-speed LVDS data of CMOS image sensors according to claim 1, characterized in that, The specific steps for adjusting the tap delay value to ensure the sampling position is in the stable region, and then finding the boundary of the transition region after the stable region, are as follows: Adjust the tap delay value so that the sampling position is in the stable region. Continue to find the boundary of the transition region after the stable region. When the current data is not equal to the temporary register data, it can be considered that the boundary of the transition region after the stable region has been found. The current tap delay value is stored in the Tap_reg2 register.

3. The high-reliability bit correction method for high-speed LVDS data of CMOS image sensors according to claim 2, characterized in that, The specific steps for calculating the center sampling position of the eye diagram stable region are as follows: The sampling position at the center of the eye diagram stable region is Taps = (Tap_reg2 - Tap_reg1) / 2. The calibration is now complete; When the CMOS sensor fails or other factors cause the transmission of LVDS data to fail, it will be judged as a correction failure.

4. A high-reliability bit correction device for high-speed LVDS data from a CMOS image sensor, characterized in that, A high-reliability bit correction method for high-speed LVDS data from a CMOS image sensor, as described in any one of claims 1-3, is employed. The high-reliability bit correction device includes a CMOS image sensor and an FPGA device. The output of the CMOS image sensor is connected to the FPGA device via multiple channels. The FPGA device includes a bit correction control module, a delay adjustment module, and a serial-to-parallel conversion module. The output of the CMOS image sensor is connected to the delay adjustment module, the output of the bit correction control module is connected to the delay adjustment module, and the output of the delay adjustment module is connected to the serial-to-parallel conversion module. By changing the tap delay value of the delay adjustment module, the delay of the surrounding delay unit is adjusted to change the sampling position in the data eye diagram. Given a fixed tap delay resolution, a complete data eye diagram cycle is equivalent to the number of tap delay values.

5. The high-reliability bit correction device for high-speed LVDS data of CMOS image sensors according to claim 4, characterized in that, The CMOS image sensor is a large-area frame, high-sensitivity back-illuminated sensor.

6. The high-reliability bit correction device for high-speed LVDS data of CMOS image sensors according to claim 5, characterized in that, The FPGA device must be a model with a clock frequency higher than that of the LVDS serial data rate of the CMOS image sensor.

7. The high-reliability bit correction device for high-speed LVDS data of CMOS image sensors according to claim 6, characterized in that, The delay adjustment module of the FPGA device has a surround delay unit with 64 or 32 tap delay values.

8. The high-reliability bit correction device for high-speed LVDS data of CMOS image sensors according to claim 6, characterized in that, The delay adjustment module of the FPGA device has a tap delay resolution of 78ps or 52ps for its surround delay unit.

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