Clock signal generation circuit, driving and control circuit and method for liquid crystal display panel

Abstract

The present application discloses a clock signal generation circuit, a driving and control circuit and method for a liquid crystal display panel. The clock signal generation circuit includes: a switching circuit that receives a first control signal and outputs a first switching signal based on the first control signal; an input circuit connected to the switching circuit, receives a second level signal and a first level signal, and outputs the first level signal or the second level signal based on the first switching signal; an output circuit connected between the input circuit and a third level signal, and outputs a first output level signal or a third level signal based on a second control signal; wherein, the voltage value of the first level signal is less than the voltage value of the second level signal and greater than the voltage value of the third level signal. The present application realizes dynamic adjustment of the clock signal by the clock signal generation circuit successively outputting the third level signal, the second level signal, the first level signal and the third level signal based on the first control signal and the second control signal.

Description

Technical Field

[0001] The present application relates to the technical field of liquid crystal display, in particular to a clock signal generation circuit, a driving and controlling circuit and method for a liquid crystal display panel. Background Art

[0002] Liquid crystal display devices (LCDs, Liquid Crystal Displays) have gradually replaced traditional cathode ray tube (CRT) displays. In particular, taking a thin film transistor (TFT, Thin Film Transistor) liquid crystal display device as an example, it includes: a liquid crystal display panel and a driving circuit. The liquid crystal display panel includes a plurality of gate lines and a plurality of data lines, and an adjacent pair of gate lines and an adjacent pair of data lines intersect to form a pixel unit, and each pixel unit includes at least one thin film transistor; the driving circuit includes a gate driving circuit and a source driving circuit. Specifically, the gate driving circuit is electrically connected to the gate lines to send gate driving signals to the gate lines, sequentially turning on the TFTs on each row of scan lines, and then the source driving circuit simultaneously charges a whole row of pixel units to their respective required voltages to display different gray levels.

[0003] Among them, the gate driving circuit includes a plurality of TFT switching elements. The gate driving circuit applies a high-level signal or a low-level signal to the gates of the plurality of TFT switching elements by using a timing signal to control the on and off of the plurality of TFT switching elements, so as to output an ideal gate driving signal. In order to ensure normal display, the turn-on voltage supplied to the gate driving circuit needs to be greater than the turn-on voltage Vth of the TFT switching element. However, in practical applications, due to the existence of certain impedance in the gate lines and some parasitic capacitances with other coatings, there is an RC delay (resistance-capacitance delay), making it difficult for the high level of the actual waveform reaching the TFT switching element to reach the turn-on voltage Vth of the TFT switching element, resulting in the TFT switching element operating in the subthreshold region and being unable to output a correct gate driving signal, and further causing the liquid crystal display screen to be unable to be normally turned on.

[0004] The prior art usually increases the high level of the turn-on pulse (CK) input to the TFT switching element, that is, increases the VGH voltage, so that the high level of the actual waveform of the TFT switching element reaches the turn-on voltage Vth of the TFT switching element. However, simply increasing the VGH voltage will increase the power consumption of the liquid crystal display screen, and since the voltage increase will cause an increase in current, the temperature will increase due to the increased heat loss in the area of the array substrate of the liquid crystal display panel where the gate driving circuit is integrated, presenting certain potential safety hazards. Summary of the Invention

[0005] This application provides at least a clock signal generation circuit, a driving and control circuit, and a method for a liquid crystal display panel, which are used to solve the problems in the prior art that the turn-on voltage of the TFT switching element in the gate driving circuit is difficult to reach the conduction voltage, resulting in the liquid crystal display screen being unable to be normally turned on, and the power consumption of the liquid crystal display panel increases when increasing the VGH voltage and the heat loss increases.

[0006] In the first aspect of this application, a clock signal generation circuit is provided, and the clock signal generation circuit includes:

[0007] A switching circuit, connected between a first level signal and a ground level, receives a first control signal, and outputs a first switching signal based on the first control signal;

[0008] An input circuit, connected to the switching circuit, receives a second level signal and a first level signal, and outputs the first level signal or the second level signal based on the first switching signal to form a first output level signal output by the input circuit;

[0009] An output circuit, connected between the input circuit and a third level signal, receives a second control signal and the first output level signal, and outputs the first output level signal or the third level signal based on the second control signal; wherein, the voltage value of the second level signal is greater than the voltage value of the first level signal, and the voltage value of the first level signal is greater than the voltage value of the third level signal;

[0010] Wherein, the clock signal generation circuit sequentially outputs a third level signal, a second level signal, a first level signal, and a third level signal based on the first control signal and the second control signal.

[0011] Optionally, the input circuit includes a first switching transistor and a second switching transistor;

[0012] Wherein, the first path end of the first switching transistor receives the second level signal, the first path end of the second switching transistor receives the first level signal, the control end of the first switching transistor is connected to the control end of the second switching transistor and the output end of the switching circuit, and the second path end of the first switching transistor is connected to the second path end of the second switching transistor to form the output end of the input circuit.

[0013] Optionally, the output circuit includes a third switching transistor and a fourth switching transistor;

[0014] Wherein, the first path end of the third switching transistor is connected to the output end of the input circuit, the control end of the third switching transistor is connected to the control end of the fourth switching transistor to receive the second control signal, and the second path end of the fourth switching transistor receives the third level signal; the second path end of the third switching transistor is connected to the first path end of the fourth switching transistor to form the output end of the output circuit.

[0015] Optionally, the switching circuit includes a fifth switching transistor and a resistor;

[0016] One end of the resistor receives a first-level signal, and the other end of the resistor is connected to the first path end of the fifth switching tube to form an output end of the switching circuit; the second path end of the fifth switching tube is connected to the ground level, and the control end of the fifth switching tube receives a first control signal.

[0017] Optionally, the first switching tube, the third switching tube, and the fifth switching tube are NMOS transistors, and the second switching tube and the fourth switching tube are PMOS transistors.

[0018] The second aspect of the present application provides a driving control circuit for a liquid crystal display panel, and the driving control circuit includes:

[0019] A level conversion module for converting an input voltage into a plurality of control signals;

[0020] A clock signal generation module is connected to the level conversion module. The clock signal generation module includes a plurality of clock signal generation circuits as described above, and outputs corresponding level signals based on a plurality of control signals;

[0021] A gate driving module is connected to the clock signal generation module to be turned on based on the corresponding level signal to turn on the liquid crystal display panel.

[0022] Optionally, the clock signal generation module includes a first clock signal generation circuit and a second clock signal generation circuit, and the first control signal received by the switching circuit of the first clock signal generation circuit is the second control signal received by the output circuit of the second clock signal generation circuit.

[0023] Optionally, the first clock signal generation circuit and the second clock signal generation circuit are arranged adjacent to each other or are arranged with multiple clock signal generation circuits in between.

[0024] The third aspect of the present application provides a driving control method for a liquid crystal display panel, which is applied to the driving control circuit as described above, and the driving control method includes:

[0025] Receiving a first control signal and a second control signal;

[0026] Outputting a corresponding level signal based on the levels of the first control signal and the second control signal;

[0027] Controlling the gate driving module to be turned on based on the level signal to turn on the liquid crystal display panel.

[0028] Optionally, outputting a corresponding level signal based on the levels of the first control signal and the second control signal includes:

[0029] In the first time period of a driving cycle, output a third-level signal based on the first control signal being at a low level and the second control signal being at a low level;

[0030] In the second time period of the driving cycle, based on the first control signal being low level and the second control signal being high level, a second level signal is output;

[0031] In the third time period of the driving cycle, based on the first control signal being high level and the second control signal being high level, a first level signal is output;

[0032] In the fourth time period of the driving cycle, based on the first control signal being high level and the second control signal being low level, a third level signal is output.

[0033] The beneficial effects of this application are as follows: Different from the prior art, in this application, the clock signal generation circuit sequentially outputs a third level signal, a second level signal, a first level signal, and a third level signal to the gate driving module based on the first control signal and the second control signal. Since the voltage value of the second level signal is greater than that of the first level signal, and the voltage value of the first level signal is greater than that of the third level signal. That is, in this application, the clock signal generation circuit outputs a second level signal with a relatively large voltage value at the first time based on the first control signal and the second control signal, so that the turn-on voltage of the thin-film transistor of the gate driving module rapidly increases. When it increases to a certain extent, the driving voltage output by the clock signal generation circuit is called back, and a first level signal with a voltage value smaller than that of the second level signal is output, so that the turn-on voltage of the thin-film transistor of the gate driving module continues to increase. This application can achieve a rapid boost in the turn-on voltage of the thin-film transistor of the gate driving module to reach the conduction voltage of the thin-film transistor, enhance the driving ability of the gate driving module, avoid the abnormal startup of the liquid crystal display screen, and does not require long-term high-voltage driving, which can further reduce the power consumption caused by voltage increase and improve the problem of increased heat loss.

[0034] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, rather than limiting this application. Description of the Drawings

[0035] In order to more clearly illustrate the technical solutions in the embodiments of this application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0036] Figure 1 It is a schematic structural diagram of an embodiment of the clock signal generation circuit of this application;

[0037] Figure 2 It is a schematic structural diagram of another embodiment of the clock signal generation circuit of this application;

[0038] Figure 3 It is a schematic structural diagram of an embodiment of the drive control circuit of the liquid crystal display panel of the present application;

[0039] Figure 4 It is another schematic structural diagram of an embodiment of the drive control circuit of the liquid crystal display panel of the present application;

[0040] Figure 5 It is a schematic working principle diagram of the drive control circuit of the liquid crystal display panel of the present application;

[0041] Figure 6 It is a schematic flow diagram of an embodiment of the drive control method of the liquid crystal display panel of the present application;

[0042] Figure 7 is Figure 6 A specific schematic flow diagram of an embodiment of step S12 in

[0043] Reference numerals: clock signal generation circuit - 10, switch circuit - 11, input circuit - 12, output circuit - 13, first switching transistor - T1, second switching transistor - T2, third switching transistor - T3, fourth switching transistor - T4, fifth switching transistor - T5, resistor R, drive control circuit - 20, level conversion module - 21, clock signal generation module 22, gate drive module - 23. Detailed implementation manners

[0044] To enable those skilled in the art to better understand the technical solutions of the present application, the clock signal generation circuit and the drive control circuit and method of the liquid crystal display panel provided by the present application will be further described in detail below with reference to the drawings and specific implementation manners. It can be understood that the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the scope of protection of the present application.

[0045] The terms "first", "second", etc. in the present application are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed, or optionally further includes other steps or units inherent to these processes, methods, products or devices.

[0046] The present application provides a clock signal generation circuit, which is connected to the gate driving module of a liquid crystal panel and is used to provide a driving voltage for the thin film transistors of the gate driving module when the liquid crystal panel needs to be turned on, so as to solve the problems in the prior art that the turn-on voltage of the TFT transistors in the gate driving circuit is difficult to reach the conduction voltage, resulting in the liquid crystal display screen being unable to be turned on normally, and the power consumption of the liquid crystal display panel increases and the heat loss is aggravated when the VGH voltage is increased.

[0047] Please refer to Figure 1 , Figure 1 which is a schematic structural diagram of an embodiment of the clock signal generation circuit of the present application. As Figure 1 shown, the clock signal generation circuit 10 includes a switch circuit 11, an input circuit 12, and an output circuit 13. Among them, the switch circuit 11 is connected to the input circuit 12, the input circuit 12 is connected to the output circuit 13, and the output circuit 13 outputs a driving voltage to the gate driving module.

[0048] Specifically, the switch circuit 11 is connected between the first level signal VGH1 and the ground level, and receives the first control signal CK1 to output a first switch signal based on the first control signal CK1.

[0049] The input circuit 12 receives the second level signal VGH2 and the first level signal VGH1, and outputs the first level signal VGH1 or the second level signal VGH2 based on the first switch signal output by the switch circuit 11 to form the first output level signal output by the input circuit 12.

[0050] The output circuit 13 receives the second control signal CK2, the first output level signal output by the input circuit 12, and the third level signal VGL, and outputs the first output level signal or the third level signal VGL based on the second control signal CK2, that is, the first level signal VGH1, the second level signal VGH2, or the third level signal VGL.

[0051] Among them, the voltage value of the second level signal VGH2 is greater than the voltage value of the first level signal VGH1, and the voltage value of the first level signal VGH1 is greater than the voltage value of the third level signal VGL. Optionally, the first level signal VGH1 is the normal turn-on voltage of the TFT transistors in a conventional gate driving circuit.

[0052] Combined with Figure 1 and further referring to Figure 2 , Figure 2 which is a schematic structural diagram of another embodiment of the clock signal generation circuit of the present application. As Figure 2 shown, the input circuit 12 includes a first switching transistor T1 and a second switching transistor T2, the output circuit 13 includes a third switching transistor T3 and a fourth switching transistor T4, and the switch circuit 11 includes a fifth switching transistor T5 and a resistor R.

[0053] Specifically, one end of the resistor R receives the first level signal VGH1, and the other end of the resistor R is connected to the first path end of the fifth switching transistor T5 to form the output end of the switching circuit 11; the second path end of the fifth switching transistor T5 is connected to the ground level, and the control end of the fifth switching transistor T5 receives the first control signal CK1.

[0054] The first path end of the first switching transistor T1 receives the second level signal VGH2, the first path end of the second switching transistor T2 receives the first level signal VGH1, and the control end of the first switching transistor T1 is connected to the control end of the second switching transistor T2 and the output end of the switching circuit 11, that is, connected to the other end of the resistor R, the first path end of the fifth switching transistor T5, and the control end of the second switching transistor T2. The second path end of the first switching transistor T1 is connected to the second path end of the second switching transistor T2 to form the output end of the input circuit 12.

[0055] The first path end of the third switching transistor T3 is connected to the output end of the input circuit 12, that is, connected to the second path end of the first switching transistor T1 and the second path end of the second switching transistor T2. The control end of the third switching transistor T3 is connected to the control end of the fourth switching transistor T4 to receive the second control signal CK2, and the second path end of the fourth switching transistor T4 receives the third level signal VGL; the second path end of the third switching transistor T3 is connected to the first path end of the fourth switching transistor T4 to form the output end of the output circuit 13 to output the driving voltage CK1_F.

[0056] Optionally, in this embodiment, the first switching transistor T1, the third switching transistor T3, and the fifth switching transistor T5 are NMOS transistors, and the second switching transistor T2 and the fourth switching transistor T4 are PMOS transistors. Specifically, the NMOS transistor is turned on by a high level, and the PMOS transistor is turned on by a low level.

[0057] Among them, the circuit working principle of the clock signal generation circuit 10 in this embodiment is specifically as follows:

[0058] When both the first control signal CK1 and the second control signal CK2 are at a low level, the fifth switching transistor T5 and the third switching transistor T3 are turned off, and the fourth switching transistor T4 is turned on. At this time, the output circuit 13 receives the third level signal VGL through the fourth switching transistor T4, and the driving voltage CK1_F output by the clock signal generation circuit 10 is specifically the third level signal VGL.

[0059] When the first control signal CK1 is at a low level and the second control signal CK2 is at a high level, the fourth switching transistor T4 and the fifth switching transistor T5 are turned off, and the third switching transistor T3 is turned on. At this time, the control terminals of the first switching transistor T1 and the second switching transistor T2 receive the first level signal VGH1 through the resistor R. Since the first level signal VGH1 is at a high level, the first switching transistor T1 is turned on and the second switching transistor T2 is turned off. That is, when the first switching transistor T1 and the third switching transistor T3 are turned on, the second level signal VGH2 is transmitted to the output circuit 13 through the first switching transistor T1 of the input circuit 12, so that the driving voltage CK1_F output by the clock signal generation circuit 10 is specifically the second level signal VGH2.

[0060] When both the first control signal CK1 and the second control signal CK2 are at a high level, the fourth switching transistor T4 is turned off, and the fifth switching transistor T5 and the third switching transistor T3 are turned on. At this time, the control terminals of the first switching transistor T1 and the second switching transistor T2 are connected to the ground level through the fifth switching transistor T5, so the first switching transistor T1 is turned off and the second switching transistor T2 is turned on. That is, when the second switching transistor T2 and the third switching transistor T3 are turned on, the first level signal VGH1 is transmitted to the output circuit 13 through the second switching transistor T2 of the input circuit 12, so that the driving voltage CK1_F output by the clock signal generation circuit 10 is specifically the first level signal VGH1.

[0061] When the first control signal CK1 is at a high level and the second control signal CK2 is at a low level, the third switching transistor T3 is turned off, and the fifth switching transistor T5 and the fourth switching transistor T4 are turned on. At this time, the output circuit 13 receives the third level signal VGL through the fourth switching transistor T4, so that the driving voltage CK1_F output by the clock signal generation circuit 10 is specifically the third level signal VGL.

[0062] The clock signal generation circuit 10 of the present application outputs the third-level signal VGL, the second-level signal VGH2, the first-level signal VGH1, and the third-level signal VGL to the gate driving module in sequence based on the first control signal CK1 and the second control signal CK2, in a certain timing relationship. Specifically, a second-level signal VGH2 with a relatively large voltage value is output at the first time, so that the turn-on voltage of the thin-film transistor of the gate driving module is rapidly increased. When it is increased to a certain extent, the driving voltage CK1_F output by the clock signal generation circuit 10 is called back, and the first-level signal VGH1 with a voltage value smaller than the second-level signal VGH2 is output, so that the turn-on voltage of the thin-film transistor of the gate driving module continues to increase, enabling the rapid boost of the turn-on voltage of the thin-film transistor of the gate driving module to reach the conduction voltage of the thin-film transistor, enhancing the driving ability of the gate driving module, and avoiding the abnormal startup of the liquid crystal display screen. At the same time, the output of the second-level signal VGH2 only occupies a part of the driving cycle, so that the clock signal generation circuit 10 does not need to maintain a high-voltage drive for a long time, which can further reduce the power consumption of the liquid crystal panel applying the clock signal generation circuit 10 and improve the problem of increased heat loss.

[0063] The present application also provides a driving control circuit for a liquid crystal display panel. Please refer to Figure 3 and Figure 4 , Figure 3 is a schematic structural diagram of an embodiment of the driving control circuit of the liquid crystal display panel of the present application, Figure 4 is another schematic structural diagram of an embodiment of the driving control circuit of the liquid crystal display panel of the present application.

[0064] As Figure 3 and Figure 4 shown, the driving control circuit 20 includes a level conversion module 21, a clock signal generation module 22, and a gate driving module 23. Among them, the clock signal generation module 22 includes a plurality of clock signal generation circuits 10 as described above, which will not be elaborated here.

[0065] Specifically, the level conversion module 21 is used to convert the input voltage CK_In of the liquid crystal display panel into a plurality of control signals CK_O, such as CK1_O, CK2_O, CKn_O, etc., which is specifically related to the number of thin-film transistors included in the gate driving module 23.

[0066] The clock signal generation module 22 is connected to the level conversion module 21 and outputs the corresponding level signal CK_F based on the plurality of control signals CK_O output by the level conversion module 21.

[0067] The gate driving module 23 is connected to the clock signal generation module 22, specifically connected to the corresponding clock signal generation circuit 10 in the clock signal generation module 22 respectively, so as to turn on the corresponding thin film transistor based on the corresponding level signal CK_F and generate a gate driving signal to turn on the liquid crystal display panel.

[0068] Optionally, in this embodiment, the clock signal generation module 22 includes a first clock signal generation circuit and a second clock signal generation circuit. The first control signal CK1 received by the switching circuit of the first clock signal generation circuit is the second control signal CK2 received by the output circuit of the second clock signal generation circuit.

[0069] Specifically, reference can be made to Figure 4 , such as Figure 4 shown. The first control signal CK1 and the second control signal CK2 received by the first clock signal generation circuit 10 are specifically CK2_O and CK1_O, and the first control signal CK1 and the second control signal CK2 received by the second clock signal generation circuit 10 are specifically CK3_O and CK2_O. Then, the first clock signal generation circuit 10 and the second clock signal generation circuit 10 are a set of the first clock signal generation circuit and the second clock signal generation circuit. Similarly, the second clock signal generation circuit 10 and the third clock signal generation circuit 10,......, the nth clock signal generation circuit 10 and the (n + 1)th clock signal generation circuit 10 can each be a set of the first clock signal generation circuit and the second clock signal generation circuit.

[0070] Among them, the first clock signal generation circuit and the second clock signal generation circuit in this embodiment can be arranged adjacent to each other or with multiple clock signal generation circuits 10 in between. As Figure 4 shown, when the first clock signal generation circuit and the second clock signal generation circuit in this embodiment are the first clock signal generation circuit 10 and the second clock signal generation circuit 10, the first clock signal generation circuit and the second clock signal generation circuit are arranged adjacent to each other; when the first clock signal generation circuit and the second clock signal generation circuit in this embodiment are the first clock signal generation circuit 10 and the last clock signal generation circuit 10, the first clock signal generation circuit and the second clock signal generation circuit are arranged with multiple clock signal generation circuits 10 in between.

[0071] Among them, the circuit working principle of the driving control circuit 20 in this embodiment can also be referred to Figure 5 , Figure 5 is the working principle diagram of the driving control circuit of the liquid crystal display panel of this application. As Figure 5As shown, the drive control circuit 20 receives multiple input voltages CK_In (clock signals) at equal time intervals. The level conversion module 21 performs level conversion on the multiple input voltages CK_In received to increase the amplitude of the high and low levels of the waveform of the input voltage CK_In, so as to obtain multiple control signals CK_O at equal time intervals, and outputs them to the clock signal generation module 22. At this time, the high level of the control signal CK_O is the first level signal VGH1, and the low level of the control signal CK_O is the third level signal VGL.

[0072] The clock signal generation module 22 further pulls up the first half of the high level of the control signal CK_O to the second level signal VGH2, and reduces the level in the second half of the high level to restore it to the original high level, so as to obtain the level signal CK_F corresponding to the multiple control signals CK_O, and outputs the level signal CK_F to the gate drive module 23 to control the corresponding thin film transistor in the gate drive module 23 to turn on.

[0073] Optionally, the time for the clock signal generation module 22 in this embodiment to pull up the high level can account for half of the entire high level. Optionally, in other embodiments, the voltage value of the second level signal VGH2 and the duty cycle of the entire high level period can be set according to the voltage value or the boost speed of the turn-on voltage of the thin film transistor.

[0074] This application also provides a drive control method for a liquid crystal display panel, specifically as follows Figure 6 shown Figure 6 is a schematic flowchart of an embodiment of the drive control method for the liquid crystal display panel of this application. Among them, the execution subject of the drive control method of this application can be the above drive control circuit 20.

[0075] Specifically, as Figure 6 shown, the drive control method for the liquid crystal display panel in the embodiments of the present disclosure may include the following steps:

[0076] Step S11: Receive a first control signal and a second control signal.

[0077] Among them, in this embodiment, the drive control circuit 20 performs level conversion on the input voltage CK_In through the level conversion module 21 to obtain multiple control signals CK_O, and combines the multiple control signals CK_O in pairs to form multiple groups of first control signals CK1 and second control signals CK2, and outputs them correspondingly to the clock signal generation module 22.

[0078] Step S12: Output corresponding level signals based on the levels of the first control signal and the second control signal.

[0079] Among them, the clock signal generation module 22 in this embodiment outputs corresponding level signals based on different changes in the levels of the received first control signal CK1 and second control signal CK2. The specific working principle is as that of the clock signal generation circuit 10, which will not be elaborated here.

[0080] Optionally, the step of specifically outputting corresponding level signals based on the levels of the first control signal CK1 and second control signal CK2 can also be as Figure 7 shown Figure 7 is Figure 6 a specific flowchart of an embodiment of step S12 in

[0081] Step S121: In the first time period of a driving cycle, based on the first control signal being at a low level and the second control signal being at a low level, output a third level signal.

[0082] Among them, since the control signal CK_O is a clock signal and Figure 5 it can be known that the control signal CK_O is a clock signal that lasts for multiple cycles. Therefore, one cycle of the clock signal is defined as a driving cycle, and the driving cycle is divided into four consecutive time periods. The first time period is the time period that continuously remains at a low level until the control signal CK_O changes to a high level. In the first time period, when both the first control signal CK1 and the second control signal CK2 received by the clock signal generation circuit 10 are at a low level, at this time, the clock signal generation circuit 10 outputs a third level signal VGL.

[0083] Step S122: In the second time period of the driving cycle, based on the first control signal being at a low level and the second control signal being at a high level, output a second level signal.

[0084] Among them, the second time period is the time period of the first half of the control signal CK_O changing to a high level. In the second time period, when the first control signal CK1 received by the clock signal generation circuit 10 is at a low level and the second control signal CK2 is at a high level, at this time, the clock signal generation circuit 10 outputs a second level signal VGH2.

[0085] Step S123: In the third time period of the driving cycle, based on the first control signal being at a high level and the second control signal being at a high level, output a first level signal.

[0086] Among them, the third time period is the time period of the second half of the control signal CK_O changing to a high level. In the third time period, when both the first control signal CK1 and the second control signal CK2 received by the clock signal generation circuit 10 are at a high level, at this time, the clock signal generation circuit 10 outputs a first level signal VGH1.

[0087] Step S124: In the fourth time period of the driving cycle, based on the first control signal being at a high level and the second control signal being at a low level, output a third-level signal.

[0088] Among them, the fourth time period is the time period when the control signal CK_O changes from a high level to a low level and continuously remains at a low level. In the fourth time period, when the first control signal CK1 received by the clock signal generation circuit 10 is at a high level and the second control signal CK2 is at a low level, at this time, the clock signal generation circuit 10 outputs a third-level signal VGL.

[0089] Furthermore, the clock signal generation circuit 10 cyclically executes step S121-step S124 according to the received control signal CK_O that changes continuously in a cycle.

[0090] Step S13: Control the gate driving module to conduct based on the level signal to turn on the liquid crystal display panel.

[0091] Among them, in this embodiment, the clock signal generation module 22 outputs a corresponding level signal to the thin film transistors connected to the corresponding clock signal generation circuits 10 according to step S12, so that the turn-on voltage of the thin film transistors reaches the conduction voltage of the thin film transistors, enabling the thin film transistors to conduct, and thus realizing turning on the liquid crystal display panel.

[0092] The above are only embodiments of the present application, and do not limit the patent scope of the present application. Any equivalent structural or equivalent process transformation made by using the content of the specification and drawings of the present application, or directly or indirectly applied in other related technical fields, are equally included in the patent protection scope of the present application.

Claims

1. A clock signal generation circuit, characterized in that, Comprising: A switching circuit, connected between a first level signal and a ground level, receiving a first control signal, and outputting a first switching signal based on the first control signal; An input circuit, connected to the switching circuit, receiving a second level signal and the first level signal, and outputting the first level signal or the second level signal based on the first switching signal to form a first output level signal output by the input circuit; An output circuit, connected between the input circuit and a third level signal, receiving a second control signal and the first output level signal, and outputting the first output level signal or the third level signal based on the second control signal; wherein, the voltage value of the second level signal is greater than the voltage value of the first level signal, and the voltage value of the first level signal is greater than the voltage value of the third level signal; Wherein, the clock signal generation circuit sequentially outputs the third level signal, the second level signal, the first level signal, and the third level signal based on the first control signal and the second control signal.

2. The clock signal generation circuit according to claim 1, wherein The input circuit includes a first switching transistor and a second switching transistor; Wherein, a first path end of the first switching transistor receives the second level signal, a first path end of the second switching transistor receives the first level signal, a control end of the first switching transistor is connected to a control end of the second switching transistor and an output end of the switching circuit, and a second path end of the first switching transistor is connected to a second path end of the second switching transistor to form an output end of the input circuit.

3. The clock signal generating circuit according to claim 2, wherein The output circuit includes a third switching transistor and a fourth switching transistor; Wherein, a first path end of the third switching transistor is connected to an output end of the input circuit, a control end of the third switching transistor is connected to a control end of the fourth switching transistor to receive the second control signal, and a second path end of the fourth switching transistor receives the third level signal; a second path end of the third switching transistor is connected to a first path end of the fourth switching transistor to form an output end of the output circuit.

4. The clock signal generation circuit according to claim 3, wherein The switching circuit includes a fifth switching transistor and a resistor; Wherein, one end of the resistor receives the first level signal, the other end of the resistor is connected to a first path end of the fifth switching transistor to form an output end of the switching circuit; a second path end of the fifth switching transistor is connected to the ground level, and a control end of the fifth switching transistor receives the first control signal.

5. The clock signal generation circuit according to claim 4, wherein The first switching transistor, the third switching transistor, and the fifth switching transistor are NMOS transistors, and the second switching transistor and the fourth switching transistor are PMOS transistors.

6. A driving and controlling circuit for a liquid crystal display panel, characterized in that, Comprising: A level conversion module for converting an input voltage into a plurality of control signals; A clock signal generation module, connected to the level conversion module, the clock signal generation module includes a plurality of clock signal generation circuits as described in any one of claims 1-5, and outputs corresponding level signals based on the plurality of control signals; A gate driving module, connected to the clock signal generation module, and conducting based on the corresponding level signals to turn on the liquid crystal display panel.

7. The drive control circuit according to claim 6, characterized in that, The clock signal generation module includes a first clock signal generation circuit and a second clock signal generation circuit, and a first control signal received by a switching circuit of the first clock signal generation circuit is a second control signal received by an output circuit of the second clock signal generation circuit.

8. The drive control circuit according to claim 7, characterized in that The first clock signal generation circuit and the second clock signal generation circuit are arranged adjacent to each other or are arranged with multiple clock signal generation circuits therebetween.

9. A driving control method for a liquid crystal display panel, applied to the driving control circuit according to any one of claims 6-8, characterized in that, It includes: Receiving a first control signal and a second control signal; Outputting a corresponding level signal based on levels of the first control signal and the second control signal; Controlling a gate driving module to turn on based on the level signal to turn on the liquid crystal display panel.

10. The drive control method according to claim 9, wherein, The outputting a corresponding level signal based on levels of the first control signal and the second control signal includes: In a first time period of a driving cycle, outputting a third level signal based on the first control signal being at a low level and the second control signal being at a low level; In a second time period of the driving cycle, outputting a second level signal based on the first control signal being at a low level and the second control signal being at a high level; In a third time period of the driving cycle, outputting a first level signal based on the first control signal being at a high level and the second control signal being at a high level; In a fourth time period of the driving cycle, outputting the third level signal based on the first control signal being at a high level and the second control signal being at a low level.

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