Semiconductor device

Abstract

A semiconductor device includes a memory bank and a column line selection circuit, the memory bank including a first memory block, a second memory block, and a redundant memory block; the column line selection circuit configured to replace a first column line of the first memory block with a first redundant line of the redundant memory block and to replace a second column line of the second memory block with a second redundant line of the redundant memory block when a failure occurs in the first column line of the first memory block.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0080445, filed on June 21, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of this disclosure relate to semiconductor devices, and more specifically, to semiconductor devices associated with performing test operations before or after a repair operation. Background Technology

[0004] Semiconductor devices perform repair operations that replace defective memory cells (hereinafter referred to as "faulty cells") with redundant cells. The repair operations of semiconductor devices include row repair operations and column repair operations. Row repair operations are performed such that when a faulty cell exists in a memory cell connected to a row line (e.g., a word line) selected based on row address, a redundant row line is used to replace the row line connected to the faulty cell. Column repair operations are performed such that when a faulty cell exists in a memory cell connected to a column line (e.g., a bit line) selected based on column address, a redundant column line is used to replace the column line connected to the faulty cell. Summary of the Invention

[0005] According to embodiments of this disclosure, a semiconductor device is provided. The semiconductor device may include: a memory bank comprising a first memory block, a second memory block, and a redundant memory block; and a column line selection circuit configured to, when a fault occurs in a first column line of the first memory block, replace the first column line of the first memory block with a first redundant line of the redundant memory block, and replace the second column line of the second memory block with a second redundant line of the redundant memory block.

[0006] Additionally, according to another embodiment of this disclosure, a semiconductor device is provided. The semiconductor device may include: a test column address generator configured to generate a first test column address and a second test column address based on column addresses; and core circuitry configured to control a first repair operation for a first memory block array and a second repair operation for a second memory block array to be performed together based on block array addresses, block addresses, and column addresses; selecting one of the column lines included in each memory block in the first memory block array based on the first test column address to output first memory block data; and selecting one of the column lines included in each memory block in the second memory block array based on the second test column address to output second memory block data.

[0007] Additionally, according to another embodiment of this disclosure, a semiconductor device is provided. The semiconductor device may include: a core circuit configured to: control a first repair operation on a first memory block array and a second repair operation on a second memory block array to be performed together based on a block array address, a block address, and a column address; select, based on a first test column address, one of the column lines included in each memory block of the first memory block array to output first memory block data; select, based on a second test column address, one of the column lines included in each memory block of the second memory block array to output second memory block data; and output redundant memory block data when a repair operation is performed on the first memory block array based on the first test column address or on the second memory block array based on the second test column address; an input / output control circuit configured to generate first driving data and second driving data from the first memory block data, the second memory block data, and the redundant memory block data based on a first shift signal and a second shift signal; and a test data generator configured to compare the first driving data with first reference data to generate a first comparison signal, compare the second driving data with second reference data to generate a second comparison signal, and compress the first comparison signal and the second comparison signal to generate test data. Attached Figure Description

[0008] Figure 1 This is a block diagram illustrating the configuration of a semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 2 The illustration is based on the included Figure 1 Block diagrams showing an example configuration of a memory cell in a semiconductor device and an example configuration of a column line selection circuit.

[0010] Figure 3 The illustration is based on the included Figure 2 A block diagram illustrating the configuration of an example storage block in the shown storage unit.

[0011] Figure 4 The illustration is based on the included Figure 2 A block diagram illustrating an example configuration of redundant storage blocks in the shown storage unit.

[0012] Figure 5 The illustration is based on the included Figure 1 A block diagram illustrating an example configuration of a fuse latch circuit in a semiconductor device.

[0013] Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 and Figure 11 It is used to illustrate based on Figure 1A diagram showing the repair operation performed on redundant fuse data in a semiconductor device.

[0014] Figure 12 , Figure 13 and Figure 14 It is used to explain in Figure 1 The diagram shows the repair operation performed on a semiconductor device based on normal fuse data.

[0015] Figure 15 This diagram illustrates the repair operations performed based on redundant fuse data and normal fuse data.

[0016] Figure 16 The illustration is based on the included Figure 1 A block diagram illustrating the configuration of an example test column address generator in a semiconductor device.

[0017] Figure 17 and Figure 18 This is a diagram used to illustrate the pre-test operations performed before the repair operation.

[0018] Figure 19 and Figure 20 This is a diagram used to illustrate the post-test operations performed after the repair operation.

[0019] Figure 21 The illustration is based on the included Figure 1 A block diagram illustrating an example configuration of a shift control circuit in a semiconductor device.

[0020] Figure 22 It is based on the inclusion of Figure 21 The circuit diagram shows an example of a shift signal generator in the shift control circuit.

[0021] Figure 23 It is used for explanation Figure 21 and Figure 22 The table shows the operation of the shift control circuit.

[0022] Figure 24 The illustration is based on the included Figure 1 A block diagram illustrating an example configuration of an input / output control circuit in a semiconductor device.

[0023] Figure 25 The diagram is based on Figure 24 A diagram showing an example configuration of the first input / output shift circuit and the first drive circuit.

[0024] Figure 26 and Figure 27 It is used to explain based on Figure 25 The diagram shows the shift operation performed by the first shift signal in the diagram.

[0025] Figure 28 The diagram is based on Figure 24 A diagram showing the configuration of an example of the second input / output shift circuit and the second drive circuit.

[0026] Figure 29 and Figure 30 It is used to explain based on Figure 28 The diagram shows the shift operation performed by the second shift signal in the diagram.

[0027] Figure 31 The illustration is based on the included Figure 1 A block diagram illustrating the configuration of an example test data generator in a semiconductor device.

[0028] Figure 32 It is based on the inclusion of Figure 31 The circuit diagram shows an example of the first comparator in the test data generator.

[0029] Figure 33 It is based on the inclusion of Figure 31 The circuit diagram shows an example of the second comparator in the test data generator.

[0030] Figure 34 It is based on the inclusion of Figure 31 The circuit diagram shows an example of the compression circuit in the test data generator.

[0031] Figure 35 and Figure 36 It is used for explanation Figure 34 The diagram shows the operation of the compression circuit. Detailed Implementation

[0032] In the description of the following embodiments, when a parameter is referred to as “predetermined,” it may be intended to mean that the value of the parameter is predetermined when it is used in a process or algorithm. The value of the parameter may be set at the start of the process or algorithm, or it may be set during the execution of the process or algorithm.

[0033] It should be understood that although the terms "first," "second," "third," etc., are used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another and are not intended to imply the order or number of elements. Therefore, without departing from the teachings of this disclosure, a first element in some embodiments may be referred to as a second element in other embodiments.

[0034] Furthermore, it should be understood that when a component is referred to as "connected" or "coupled" to another component, it can be directly connected or coupled to the other component, or there may be intermediate components. Conversely, when a component is referred to as "directly connected" or "directly coupled" to another component, there are no intermediate components.

[0035] Logic "high" and logic "low" levels can be used to describe the logic levels of electrical signals. Signals with a logic "high" level can be distinguished from signals with a logic "low" level. For example, when a signal with a first voltage corresponds to a signal with a logic "high" level, a signal with a second voltage corresponds to a signal with a logic "low" level. In one embodiment, a logic "high" level can be set to a voltage level higher than that of a logic "low" level. Furthermore, according to embodiments, the logic levels of signals can be set to different or opposite levels. For example, a signal with a logic "high" level in one embodiment can be set to a logic "low" level in another embodiment.

[0036] In the following description, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. However, the embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the present disclosure.

[0037] Figure 1 This is a block diagram illustrating the configuration of a semiconductor device 1 according to an embodiment of the present disclosure. Figure 1 As shown, the semiconductor device 1 may include: an address decoder 10, a core circuit 11, a test column address generator 13, a shift control circuit 15, an input / output (I / O) control circuit 17, a reference data (REFD) register 18, and a test data generator 19.

[0038] Address decoder 10 can receive address ADD from an external device (not shown) of semiconductor device 1. The external device of semiconductor device 1 can be one of a semiconductor controller, a host, and a test device. Address decoder 10 can decode address ADD to generate block array address BRADD, block address BADD, and column address CADD. Block array address BRADD can be configured to have options for selecting entries included in memory (…). Figure 2 The first storage block array in (101) Figure 2 121) and the second storage block array ( Figure 2 The block address BADD can be set to have a logical bit (123) used to select the memory block to be included in the selected memory block array. Figure 2The block address BADD can include a set of logical bits of one of the memory blocks (MBs) included in the first memory block array 121 and the second memory block array 123. The number of bits included in the block address BADD can be set according to the number of memory blocks (MBs) included in each of the first memory block array 121 and the second memory block array 123. For example, when the number of memory blocks (MBs) included in each of the first memory block array 121 and the second memory block array 123 is 16, the block address BADD can be implemented as including 4 bits. The column address CADD can include bits of a set of logical bits having one of the column lines (YL) for selecting the memory block (MB) selected by the block address BADD. The number of bits included in the column address CADD can be set according to the number of column lines (YL) included in the memory blocks (MBs). For example, when the number of column lines (YL) included in the memory blocks (MBs) is 64, the column address CADD can be implemented as including 6 bits.

[0039] The core circuit 11 can receive the block array address BRADD, the block address BADD, and the column address CADD from the address decoder 10. The core circuit 11 can receive the first test column address TCAD1 and the second test column address TCAD2 from the test column address generator 13. The first test column address TCAD1 and the second test column address TCAD2 can be generated based on the column address CADD to perform a pre-test for checking for faults requiring repair and a post-test for checking whether the repair operation was performed correctly. The core circuit 11 can receive a first test mode signal TM1 for performing the pre-test and a second test mode signal TM2 for performing the post-test. The first test mode signal TM1 and the second test mode signal TM2 can be generated by decoding commands (not shown) inside the semiconductor device 1, or can be received from an external device (not shown) of the semiconductor device 1. The core circuit 11 may include: a memory bank 101, a column line selection circuit 103, and a fuse latch circuit 105. In this embodiment, for ease of explanation, the core circuit 11 is implemented as including one memory bank 101, but according to embodiments, it may also be implemented as including multiple memory banks.

[0040] The memory bank 101 can be connected to multiple column lines YL and multiple redundant column lines RYL. For example... Figure 2 As shown, the storage bank 101 may include a first storage block array 121 and a second storage block array 123, which includes storage blocks MB connected to multiple column lines YL. The storage bank 101 may also include redundant storage blocks (RED MB) connected to multiple redundant column lines RYL. Figure 2 (125).

[0041] The column line selection circuit 103 can select one of the first memory block array 121 and the second memory block array 123 based on the block array address BRADD, and can select one memory block MB based on the block address BADD. The column line selection circuit 103 can also select one column line YL of the memory block MB based on the column address CADD. The column line selection circuit 103 can control at least one memory cell (not shown) connected to the column line YL of the memory block selected based on the block array address BRADD, block address BADD, and column address CADD. Hereinafter, it is assumed and explained that a fault in the column line YL of the memory block MB selected based on the block array address BRADD, block address BADD, and column address CADD means that a faulty cell is among the memory cells connected to the column line YL of the memory block MB selected based on the block array address BRADD, block address BADD, and column address CADD.

[0042] The column line selection circuit 103 can receive redundant fuse data RFD and normal fuse data NFD from the fuse latch circuit 105. The column line selection circuit 103 can control the memory bank 101 to simultaneously perform repair operations on column lines YL of multiple memory blocks MB based on the redundant fuse data RFD. The column line YL of each of the multiple memory blocks MB to which the repair operation is performed simultaneously can be selected based on the block array address BRADD, block address BADD, and column address CADD. The column line selection circuit 103 can control the memory bank 101 to perform repair operations on the column lines YL of the memory blocks MB selected by the block array address BRADD, block address BADD, and column address CADD based on the normal fuse data NFD. As used herein, the terms "simultaneous" and "at the same time" regarding a process or operation mean that the process or operation occurs over overlapping time intervals. For example, if a first process or operation occurs within a first time interval and a second process or operation occurs simultaneously within a second time interval, then the first and second time intervals at least partially overlap, resulting in a time when the first and second processes or operations occur simultaneously.

[0043] When the column line selection circuit 103 receives the first test mode signal TM1, it outputs the data of a memory cell selected by the first test column address TCAD1 and connected to one of the column lines YL of the memory block MB included in the first memory block array 121 as first memory block data via the first local line LIO1, thereby performing a pre-test to check for faulty cells that need repair. Furthermore, when the column line selection circuit 103 receives the first test mode signal TM1, it outputs the data of a memory cell selected by the second test column address TCAD2 and connected to another of the column lines YL of the memory block MB included in the second memory block array 123 via the second local line LIO2 as second memory block data MBD2. During the pre-test, the first test column address TCAD1 and the second test column address TCAD2 can be set to have different sets of logic bits to select column lines YL to be repaired together.

[0044] When the column line selection circuit 103 receives the second test mode signal TM2, it outputs the data of a memory cell connected to a column line YL of a memory block MB included in the first memory block array 121, selected by the first test column address TCAD1, as first memory block data MBD1 via the first local line LIO1, thereby performing a post-test to check whether the repair operation has been performed correctly. Furthermore, when the column line selection circuit 103 receives the second test mode signal TM2, it outputs the data of a memory cell connected to a column line YL of a memory block MB included in the second memory block array 123, selected by the second test column address TCAD2, as second memory block data MBD2 via the second local line LIO2. In the post-test, the first test column address TCAD1 and the second test column address TCAD2 can be set to have the same set of logic bits to select the same column line YL. When the second test mode signal TM2 is received and one of the redundant column lines RYL is used to replace one of the column lines YL of the memory block MB included in the first memory block array 121 selected by the first test column address TCAD1, the column line selection circuit 103 can output the data of the redundant memory cell connected to one of the redundant column lines RYL as redundant memory block data RMBD via the redundant local line RLIO. On the other hand, when the second test mode signal TM2 is received and another redundant column line RYL is used to replace one of the column lines YL of the memory block MB included in the second memory block array 123 selected by the second test column address TCAD2, the column line selection circuit 103 can output the data of the redundant memory cell connected to the other redundant column line RYL as redundant memory block data RMBD via the redundant local line RLIO.

[0045] Fuse latch circuit 105 can store redundant fuse data RFD for controlling the simultaneous execution of repair operations on column lines YL of each of a plurality of memory blocks MB selected based on block array address BRADD, block address BADD, and column address CADD. Fuse latch circuit 105 can also store normal fuse data NFD for controlling the repair operations, wherein another column line YL is used to replace one of the column lines YL included in one of the memory blocks MB selected based on block array address BRADD, block address BADD, and column address CADD. Fuse latch circuit 105 can then apply the redundant fuse data RFD and normal fuse data NFD stored therein to column line selection circuit 103.

[0046] The test column address generator 13 can receive column address CAD from address decoder 10, and can also receive a first test mode signal TM1 and a second test mode signal TM2. The test column address generator 13 can generate a first test column address TCAD1 and a second test column address TCAD2 from the column address CAD based on the first test mode signal TM1 and the second test mode signal TM2. When the first test mode signal TM1 is received to perform a pre-test, the test column address generator 13 can buffer the column address CAD to generate the first test column address TCAD1, and can also generate the second test column address TCAD2 by buffering the column address CAD (wherein at least one bit included in the bits of the column address CAD is buffered by inversion). One of the column lines YL selected by the first test column address TCAD1 and the other of the column lines YL selected by the second test column address TCAD2 generated during the pre-test can be set to be repaired together after the pre-test. When the second test mode signal TM2 is received to perform a post-test, the test column address generator 13 can buffer the column address CAD to generate the first test column address TCAD1 and the second test column address TCAD2.

[0047] The shift control circuit 15 can receive redundant fuse data RFD from the fuse latch circuit 105. The shift control circuit 15 can generate a first shift signal SFT1 and a second shift signal SFT2 based on the redundant fuse data RFD. When no repair operation is performed, the shift control circuit 15 can generate a first shift signal SFT1 and a second shift signal SFT2, both of which are deactivated, based on the redundant fuse data RFD. When a memory block MB included in the first memory block array 121 contains a faulty cell and the faulty cell is repaired, the shift control circuit 15 can generate an activated first shift signal SFT1 and a deactivated second shift signal SFT2 based on the redundant fuse data RFD. When a memory block MB included in the second memory block array 123 contains a faulty cell and the faulty cell is repaired, the shift control circuit 15 can generate a deactivated first shift signal SFT1 and an activated second shift signal SFT2 based on the redundant fuse data RFD.

[0048] The input / output control circuit 17 can receive first memory block data MBD1, second memory block data MBD2, and redundant memory block data RMBD from the core circuit 11. The input / output control circuit 17 can receive a first shift signal SFT1 and a second shift signal SFT2 from the shift control circuit 15. When the deactivated first shift signal SFT1 is received, the input / output control circuit 17 can drive first drive data DRD1 from the first memory block data MBD1 received via the first local line LIO1, and output the first drive data DRD1 via the first global line GIL1. When the deactivated second shift signal SFT2 is received, the input / output control circuit 17 can drive second drive data DRD2 from the second memory block data MBD2 received via the second local line LIO2, and output the second drive data DRD2 via the second global line GIL2. When a memory block MB included in the first memory block array 121 includes a faulty cell and receives an activated first shift signal SFT1, the input / output control circuit 17 can sequentially shift a portion of the first memory block data MBD1 received via the first local line LIO1 and the redundant memory block data RMBD received via the redundant local line RLIO, drive the first drive data DRD1 from the shifted redundant memory block data RMBD and the portion of the first memory block data MBD1, and output the first drive data DRD1 via the first global line GIO1. When a memory block MB included in the second memory block array 123 includes a faulty cell and receives an activated second shift signal SFT2, the input / output control circuit 17 can sequentially move the redundant memory block data RMBD received via the redundant local line RLIO and a portion of the second memory block data MBD2 received via the second local line LIO2, drive the second drive data DRD2 from the shifted redundant memory block data RMBD and the portion of the second memory block data MBD2, and output the second drive data DRD2 via the second global line GIO2.

[0049] Reference data register 18 can store first reference data REFD1 and second reference data REFD2 based on the first test mode signal TM1 and the second test mode signal TM2, and apply the stored first reference data REFD1 and second reference data REFD2 to test data generator 19. When the first test mode signal TM1 for pre-test activation is received, reference data register 18 can store first reference data REFD1, which is set to have the same set of logical bits as the first drive data DRD1 generated when no fault cell is present in the first memory block array 121, and apply the stored first reference data REFD1 to test data generator 19. Furthermore, when the first test mode signal TM1 for pre-test activation is received, reference data register 18 can store second reference data REFD2, which is set to have the same set of logical bits as the second drive data DRD2 generated when no fault cell is present in the second memory block array 123, and apply the stored second reference data REFD2 to test data generator 19. On the other hand, when the second test mode activation signal TM2 for post-testing is received, the reference data register 18 can store first reference data REFD1, which is set to have the same set of logical bits as the first drive data DRD1 generated when the first memory block array 121 does not contain a faulty cell or when a faulty cell included in the first memory block array 121 is repaired, and the stored first reference data REFD1 is applied to the test data generator 19. Furthermore, when the second test mode activation signal TM2 for post-testing is received, the reference data register 18 can store second reference data REFD2, which is set to have the same set of logical bits as the second drive data DRD2 generated when the second memory block array 123 does not contain a faulty cell or when a faulty cell included in the second memory block array 123 is repaired, and the stored second reference data REFD2 is applied to the test data generator 19. The first reference data REFD1 and the second reference data REFD2 can be stored in the reference data register 18 through a mode register group. First reference data REFD1 and second reference data REFD2, which have different sets of logical bits, can be stored in reference data register 18 before performing pre-test or post-test.

[0050] Test data generator 19 can receive first drive data DRD1 and second drive data DRD2 from input / output control circuit 17. Test data generator 19 can receive first reference data REFD1 and second reference data REFD2 from reference data register 18. Test data generator 19 can generate test data TDQ from first drive data DRD1, second drive data DRD2, first reference data REFD1, and second reference data REFD2. When performing pre-test or post-test, test data generator 19 can compare first drive data DRD1 with first reference data REFD1, compare second drive data DRD2 with second reference data REFD2, and compress the comparison results to generate test data TDQ. Test data TDQ can be set with a set of logical bits set according to information from memory block MB including faulty cells. Because test data TDQ is generated by compressing the comparison results between first drive data DRD1 and first reference data REFD1 and the comparison results between second drive data DRD2 and second reference data REFD2, the test time required to perform pre-test and post-test can be reduced. The test data TDQ can be applied to external devices of semiconductor device 1.

[0051] Figure 2 The illustration includes Figure 1 A block diagram showing the configuration of the memory bank 101 and the line selection circuit 103 in the semiconductor device 1.

[0052] like Figure 2As shown, memory bank 101 may include a first memory block array 121, a second memory block array 123, and redundant memory blocks 125. One of the first memory block array 121 and the second memory block array 123 can be selected based on the block array address BRADD. As an example, the first memory block array 121 can be selected when the block array address BRADD is set to a logic "low" level bit, and the second memory block array 123 can be selected when the block array address BRADD is selected to a logic "high" level bit. Each of the first memory block array 121 and the second memory block array 123 may include multiple memory blocks MB. One of the memory blocks MB included in the first memory block array 121 and the second memory block array 123 can be selected based on the block address BADD. As an example, when the block address BADD is set to the Kth logic bit set, the Kth memory block MB included in each of the first memory block array 121 and the second memory block array 123 can be selected. One of the column lines YL of each memory block MB can be selected based on the column address CADD. When the column address CADD is set to the Lth logical bit set, the Lth column line YL of the storage block MB can be selected. Here, each of "K" and "L" can be set to a natural number. Each storage block MB may include multiple storage cells connected to each column line YL. When a column line YL is selected based on the block array address BRADD, the block address BADD, and the column address CADD, at least one storage cell connected to the column line YL can be accessed. Redundant storage block 125 may include multiple redundant column lines RYL. Redundant storage block 125 may include multiple redundant cells (not shown) respectively connected to the multiple redundant column lines RYL. At least one of the redundant cells included in redundant storage block 125 can be connected to and accessed from one of the redundant column lines RYL selected when a repair operation is performed based on the redundant fuse data RFD. In order to access a storage cell included in storage block MB or a redundant cell included in redundant storage block 125, a row line (e.g., a word line) should be selected based on the row address (not shown) before selecting a column line YL, but for convenience, a detailed description of the row line selection operation will be omitted. In the following text, it is assumed and explained that when a column line YL is selected and a memory cell is accessed, the row line selection operation is performed first.

[0053] like Figure 2As shown, the column line selection circuit 103 can receive block array address BRADD, block address BADD, column address CADD, redundant fuse data RFD, and normal fuse data NFD. The column line selection circuit 103 can include multiple column decoders CDEC. Each of the multiple column decoders CDEC can correspond to each of the memory block MB and redundant memory block 125 included in the first memory block array 121 and the second memory block array 123. When a repair operation is performed based on the redundant fuse data RFD, the multiple column decoders CDEC can decode the block array address BRADD, block address BADD, and column address CADD to replace at least one of the column lines YL of the selected memory block MB with at least one of the redundant column lines RYL of the redundant memory block 125. When a repair operation is performed based on the normal fuse data NFD, the multiple column decoders CDEC can decode the block array address BRADD, block address BADD, and column address CADD to replace at least one of the column lines YL of the selected memory block MB with another redundant column line RYL of the redundant memory block 125.

[0054] Figure 3 The diagram is based on Figure 2 The diagram shows a block diagram of the configuration of an example storage block MB, and Figure 4 The diagram is based on Figure 2 A block diagram illustrating the configuration of an example of redundant storage block 125.

[0055] like Figure 3 and Figure 4 As shown, each memory block MB included in the first memory block array 121 and the second memory block array 123 may include a first column line set (1st YL SET) YL<1:32> and a second column line set (2nd YL SET) YL<33:64>, and the redundant memory block 125 may include a first redundant column line set (first RYL SET) RYL<1:32> and a second redundant column line set (second RYL SET) RYL<33:64>. The first column line set YL<1:32> may include the first column line YL <1> Up to the thirty-second line YL <32> Furthermore, the second column line set YL<33:64> may include the thirty-third column line YL <33> Up to line YL (sixty-fourth column) <64> The first redundant column line set RYL<1:32> can include the first redundant column line RYL <1> Up to the thirty-second redundant column line RYL <32> Furthermore, the second redundant column line set RYL<33:64> may include the thirty-third redundant column line RYL. <33> Up to the sixty-fourth redundant column line RYL <64> .

[0056] Figure 5 The illustration is based on the included Figure 1A block diagram illustrating the configuration of an example fuse latch circuit 105A in a semiconductor device. (See diagram for reference.) Figure 5 As shown, the fuse latch circuit 105A may include a redundant fuse latch circuit 131 and a normal fuse latch circuit 133. In the following, assumptions and explanations are made. Figure 2 Each of the first memory block array 121 and the second memory block array 123 shown includes 16 memory blocks MB, and each memory block MB includes a first column line set YL<1:32> and a second column line set YL<33:64>, as shown. Figure 3 and Figure 4 As shown, the redundant storage block 125 includes a first redundant column line set RYL<1:32> and a second redundant column line set RYL<33:64>.

[0057] The redundant fuse latch circuit 131 may include multiple redundant fuse latches 131_1 to 131_32 to output redundant fuse data RFD. As used herein, the tilde “~” indicates a component range. For example, “131_1 to 131_32” represents Figure 5 The redundant fuse latches 131_1, 131_2, ..., 131_32 are shown. Each of the redundant fuse latches 131_1 to 131_32 can correspond to a column line YL of each memory block MB included in the first memory block array 121 and a column line YL of each memory block MB included in the second memory block array 123. Each of the redundant fuse latches 131_1 to 131_32 included in the redundant fuse latch circuit 131 can store information about the column line YL and information about the memory block MB that has failed therein for repair operations, and output the stored information as redundant fuse data RFD. For example, when the first column line YL of the first memory block MB included in the first memory block array 121... <1> When a fault occurs, the first redundant fuse latch 131_1 can store information about the first memory block MB and the first column line YL included in the first memory block array 121. <1> Information. As another example, when the third column line YL of the second storage block MB included in the second storage block array 123... <3> In the event of a fault, the third redundant fuse latch 131_3 can store information about the second memory block MB and the third column line YL included in the second memory block array 123. <3> The information is as follows. Each of the redundant fuse latches 131_1 to 131_32 may include multiple redundant fuses (not shown), and the set of logical bits of the redundant fuse data RFD output from the redundant fuse latch circuit 131 can be set according to whether the multiple redundant fuses are tripped. Based on the set of logical bits of the redundant fuse data RFD, information about the faulty memory block MB and column line YL can be extracted for repair operations.

[0058] like Figure 5 and Figure 6 As shown, the first redundant fuse latch 131_1 included in the fuse latch circuit 105 can correspond to the first column line YL of each memory block MB included in the first memory block array 121. <1> and the thirty-third column line YL included in each memory block MB in the second memory block array 123 <33> The second redundant fuse latch 131_2 included in the fuse latch circuit 105 can correspond to the second column line YL included in each memory block MB in the first memory block array 121. <2> and the thirty-fourth column line YL included in each memory block MB in the second memory block array 123 <34> The thirty-second redundant fuse latches 131-32 included in the fuse latch circuit 105 can correspond to the thirty-second column line YL included in each memory block MB in the first memory block array 121. <32> and the sixty-fourth column line YL included in each memory block MB in the second memory block array 123 <64> Because each of the redundant fuse latches 131_1 to 131_32 included in the redundant fuse latch circuit 131 corresponds to the plurality of column lines, the number of redundant fuse latches 131_1 to 131_32 required for repair operations can be reduced, thereby reducing the layout area of ​​the redundant fuse latch circuit 131.

[0059] The description will be based on... Figure 5The repair operation performed by the redundant fuse data RFD output by the redundant fuse latch circuit 131 shown is an example. For instance, when a fault occurs in a column line of the first column line set YL<1:32> of the memory block MB included in the first memory block array 121, the following repair operation is performed based on the redundant fuse data RFD: a column line of the first redundant column line set RYL<1:32> of the redundant memory block 125 is used to replace a column line of the first column line set YL<1:32> of the memory block MB included in the first memory block array 121; a column line of the second redundant column line set RYL<33:64> of the redundant memory block 125 is used to replace a column line of the second column line set YL<33:64> of the memory block MB included in the second memory block array 123. As another example, when a fault occurs in a column line of the second column line set YL<33:64> of the storage block MB included in the first storage block array 121, the following repair operations are performed based on the redundant fuse data RFD: a column line of the first redundant column line set RYL<1:32> of the redundant storage block 125 is used to replace a column line of the second column line set YL<33:64> of the storage block MB included in the first storage block array 121; a column line of the second redundant column line set RYL<33:64> of the redundant storage block 125 is used to replace a column line of the first column line set YL<1:32> of the storage block MB included in the second storage block array 123. As another example, when a fault occurs in a column line of the first column line set YL<1:32> of the storage block MB included in the second storage block array 123, the following repair operation is performed based on the redundant fuse data RFD: a column line of the second redundant column line set RYL<33:64> of the redundant storage block 125 is used to replace a column line of the first column line set YL<1:32> of the storage block MB included in the second storage block array 123; a column line of the first redundant column line set RYL<1:32> of the redundant storage block 125 is used to replace a column line of the second column line set YL<33:64> of the storage block MB included in the first storage block array 121. As another example, when a fault occurs in a column line of the second column line set YL<33:64> of the memory block MB included in the second memory block array 123, the following repair operation is performed based on the redundant fuse data RFD: a column line of the second column line set RYL<33:64> of the redundant memory block 125 is used to replace a column line of the second column line set YL<33:64> of the memory block MB included in the second memory block array 123; a column line of the first column line set RYL<1:32> of the redundant memory block 125 is used to replace a column line of the first column line set YL<1:32> of the memory block MB included in the first memory block array 121. In the following text, reference will be made to... Figures 6 to 11This describes the repair operations performed based on redundant fuse data RFD.

[0060] like Figure 6 and Figure 7 As shown, based on the redundant fuse data RFD output from the first redundant fuse latch 131_1, the following repair operation is performed: utilizing the first redundant column line RYL of the redundant storage block 125. <1> To replace the first column line YL of the memory block (MB IN 121) included in the first memory block array that failed. <1> ;Utilizing the thirty-third redundant column line RYL of redundant storage block 125 <33> To replace the thirty-third column line YL included in the second memory block array (MB IN 123). <33> Furthermore, based on the redundant fuse data RFD output from the second redundant fuse latch 131_2, the following repair operation is performed: utilizing the second redundant column line RYL of the redundant storage block 125. <2> To replace the second column line YL included in the first memory block array that failed (MB IN 121). <2> ;Utilizing the thirty-fourth redundant column line RYL of redundant storage block 125 <34> To replace the 34th column line YL included in the second memory block array (MB IN 123). <34> .

[0061] like Figure 6 and Figure 8 As shown, based on the redundant fuse data RFD output from the thirty-two redundant fuse latches 131_32, the following repair operation is performed: utilizing the thirty-second redundant column line RYL of the redundant storage block 125. <32> To replace the thirty-second column line YL included in the first memory block array that failed (MB IN 121). <32> ;Utilizing the sixty-fourth redundant column line RYL of redundant storage block 125 <64> To replace the 64th column line YL included in the second memory block array (MB IN 123). <64> .

[0062] like Figure 5 and Figure 9As shown, the first redundant fuse latch 131_1 included in the fuse latch circuit 105 can correspond to the thirty-third column line YL included in each memory block MB in the first memory block array 121. <33> and the first column line YL included in each memory block MB in the second memory block array 123 <1> The second redundant fuse latch 131_2 included in the fuse latch circuit 105 can correspond to the thirty-fourth column line YL included in each memory block MB in the first memory block array 121. <34> and the second column line YL included in each memory block MB in the second memory block array 123 <2> The thirty-second redundant fuse latch 131-32 included in the fuse latch circuit 105 can correspond to the sixty-fourth column line YL included in each memory block MB in the first memory block array 121. <64> and the thirty-second column line YL included in each memory block MB in the second memory block array 123 <32> .

[0063] like Figure 9 and Figure 10 As shown, based on the redundant fuse data RFD output from the first redundant fuse latch 131_1, the following repair operation is performed: utilizing the first redundant column line RYL of the redundant storage block 125. <1> To replace the thirty-third column line YL included in the first memory block array that failed (MB IN 121). <33> ;Utilizing the thirty-third redundant column line RYL of redundant storage block 125 <33> To replace the first column line YL of the memory block (MB IN 123) included in the second memory block array <1> Furthermore, based on the redundant fuse data RFD output from the second redundant fuse latch 131_2, the following repair operation is performed: utilizing the second redundant column line RYL of the redundant storage block 125. <2> To replace the thirty-fourth column line YL included in the first memory block array that failed (MB IN 121). <34> ;Utilizing the thirty-fourth redundant column line RYL of redundant storage block 125 <34> To replace the second column line YL of the memory block (MB IN 123) included in the second memory block array. <2> .

[0064] like Figure 9 and Figure 11 As shown, based on the redundant fuse data RFD output from the thirty-two redundant fuse latches 131_32, the following repair operation is performed: utilizing the thirty-second redundant column line RYL of the redundant storage block 125. <32> To replace the sixty-fourth column line YL included in the first memory block array that failed (MB IN 121). <64> ;Utilizing the sixty-fourth redundant column line RYL of redundant storage block 125 <64> To replace the 32nd column line YL included in the second memory block array (MB IN123) <32> .

[0065] like Figure 5 As shown, the normal fuse latch circuit 133 may include a plurality of normal fuse latches 133_1 to 133_32 to output normal fuse data (NFD). Each of the normal fuse latches 133_1 to 133_32 included in the normal fuse latch circuit 133 may correspond to each memory block MB included in the first memory block array 121 and the second memory block array 123. For example, when each of the first memory block array 121 and the second memory block array 123 includes sixteen memory blocks MB, the normal fuse latch circuit 133 may include thirty-two normal fuse latches. Here, the first to sixteenth storage blocks MB of the first storage block array 121 can correspond to the first to sixteenth normal fuse latches 133_1 to 133_16, respectively, and the first to sixteenth storage blocks MB of the second storage block array 123 can correspond to the seventeenth to thirty-second normal fuse latches 133_17 to 133_32, respectively. Information for replacing one of the faulty column lines YL in the storage blocks MB corresponding to the normal fuse latches 133_1 to 133_32 with another column line YL can be stored, and the stored information can be output as normal fuse data NFD.

[0066] like Figure 12As shown, when each memory block MB included in the first memory block array 121 and the second memory block array 123 includes a first column line set (1st YL SET) YL<1:32> and a second column line set (2nd YL SET) YL<33:64>, the first column line set (1st YL SET) YL<1:32> is divided into a first sub-column line set (1st SUB YL SET) YL<1:16> and a second sub-column line set (2nd SUB YL SET) YL<17:32>, and the second column line set (2nd YL SET) YL<33:64> is divided into a third sub-column line set (3rd SUB YL SET) YL<33:48> and a fourth sub-column line set (4th SUB YL SET) YL<49:64>. The repair operation performed based on the normal fuse data NFD output from the redundant fuse latch circuit 131 is described as an example. For example, when a fault occurs in a column of the first sub-column set YL<1:16> of storage block MB, a repair operation can be performed based on the normal fuse data NFD, replacing a column of the first sub-column set YL<1:16> with a column of the second sub-column set YL<17:32>. As another example, when a fault occurs in a column of the second sub-column set YL<17:32> of storage block MB, a repair operation can be performed based on the normal fuse data NFD, replacing a column of the second sub-column set YL<17:32> with a column of the first sub-column set YL<1:16>. As yet another example, when a fault occurs in a column of the third sub-column set YL<33:48> of storage block MB, a repair operation can be performed based on the normal fuse data NFD, replacing a column of the third sub-column set YL<49:64> with a column of the fourth sub-column set YL<33:48>. As another example, when a fault occurs in a column line of the fourth sub-column line set YL<49:64> of storage block MB, a repair operation can be performed based on normal fuse data NFD, replacing a column line of the fourth sub-column line set YL<49:64> with a column line of the third sub-column line set YL<33:48>. This will be referred to below. Figure 13 and Figure 14 This describes the repair operations performed based on normal fuse data NFD.

[0067] like Figure 13As shown, when in the first column line YL of storage block MB <1> When a fault occurs, NFD can be performed using the seventeenth column line YL of the memory block MB, based on the normal fuse data corresponding to the memory block MB. <17> To replace the first column line YL of the storage block MB <1> Repair operation. When in the second column line YL of storage block MB. <2> When a fault occurs, NFD can be performed using the eighteenth column line YL of the memory block MB, based on the normal fuse data corresponding to the memory block MB. <18> To replace the second column line YL of the storage block MB <2> Repair operation. When in the sixteenth column line YL of storage block MB. <16> When a fault occurs, NFD can be performed using the 32nd column line YL of the storage block MB, based on the normal fuse data corresponding to the storage block MB. <32> To replace the sixteenth column line YL of the storage block MB <16> Repair operation. When in the seventeenth column line YL of storage block MB. <17> When a fault occurs, NFD can be performed using the first column line YL of the memory block MB based on the normal fuse data corresponding to the memory block MB. <1> To replace the seventeenth column line YL of the storage block MB <17> Repair operation. When in the thirty-second column line YL of storage block MB. <32> When a fault occurs, NFD can be performed using the sixteenth column line YL of the memory block MB, based on the normal fuse data corresponding to the memory block MB. <16> To replace the 32nd column line YL of the storage block MB <32> Repair operations.

[0068] like Figure 14As shown, when in the thirty-third column line YL of storage block MB <33> When a fault occurs, NFD can be performed using the 49th column line YL of the storage block MB, based on the normal fuse data corresponding to the storage block MB. <49> To replace the 33rd column line YL of the storage block MB <33> Repair operation. When in the 34th column line YL of storage block MB. <34> When a fault occurs, NFD can be performed using the fiftieth column line YL of the memory block MB based on the normal fuse data corresponding to the memory block MB. <50> To replace the 34th column line YL of the storage block MB <34> Repair operation. When in storage block MB, line 48, YL... <48> When a fault occurs, NFD can be performed using the 64th column line YL of the memory block MB based on the normal fuse data corresponding to the memory block MB. <64> To replace the 48th column line YL of the storage block MB <48> Repair operation. When in the 49th column line YL of storage block MB. <49> When a fault occurs, NFD can be performed using the 33rd column line YL of the storage block MB, based on the normal fuse data corresponding to the storage block MB. <33> To replace the 49th column line YL of the storage block MB <49> Repair operation. When in the storage block MB, line 64, YL... <64> When a fault occurs, NFD can be performed using the 48th column line YL of the storage block MB, based on the normal fuse data corresponding to the storage block MB. <48> To replace the 64th column line YL of the storage block MB <64> Repair operations.

[0069] Figure 15 This diagram illustrates the repair operations performed based on redundant fuse data (RFD) and normal fuse data (NFD). Figure 15 As shown, when in the first column line YL of the first storage block (1st MB IN 121) included in the first storage block array <1> When a fault occurs, the following repair operation can be performed based on the redundant fuse data RFD: using the first redundant column line RYL of redundant storage block 125. <1> To replace the first column line YL <1> ;Utilizing the thirty-third redundant column line RYL of redundant storage block 125 <33> To replace the 33rd column line YL included in the first memory block (1st MB IN 123) in the second memory block array. <33> Furthermore, when in the first column line YL of the second storage block (2nd MB IN 121) including the first storage block array... <1> When a fault occurs, NFD can be executed using the seventeenth column line based on normal fuse data. <YL <17> To replace the first column line YL <1> Repair operations.

[0070] Figure 16 The illustration is based on the included Figure 1 A block diagram showing the configuration of an example test column address generator 13A in semiconductor device 1. Figure 16As shown, the test column address generator 13A can generate a first test column address TCAD1<6:1> and a second test column address TCAD2<6:1> for performing pre-tests or post-tests from the column address CADD<6:1>. The test column address generator 13A may include inverters 141_1 to 141_7. Inverters 141_1 and 141_2 can buffer the first to fifth bits of the column address CADD<5:1> to generate the first to fifth bits of the first test column address TCAD1<5:1> and the first to fifth bits of the second test column address TCAD2<5:1>. Inverters 141_3 and 141_4 can buffer the sixth bit of the column address CADD. <6> To generate the sixth bit of the first test column address, TCAD1 <6> Inverter 141_5 can invert the buffered first test mode signal TM1 to generate an inverted buffered signal of the first test mode signal TM1. When the first test mode signal TM1 is received at a logic "high" level, inverter 141_6 can invert the sixth bit of the buffered column address CADD. <6> The sixth bit of the TCAD2 used to generate the second column address <6> This allows for the execution of a pre-test. Inverter 141_7 can invert the buffered second test mode signal TM2 to generate an inverted buffered signal of the second test mode signal TM2. When the second test mode signal TM2 is received at a logic "high" level, inverters 141_8 and 141_9 can buffer the sixth bit of the column address CADD. <6> The sixth bit of the TCAD2 used to generate the second column address <6> This allows for the execution of post-tests. In the pre-test, the test column address generator 13A can generate a first test column address TCAD1<6:1> to select one of the column lines YL included in each memory block MB in the first memory block array 121, and can generate a second test column address TCAD2<6:1> to select the other of the column lines YL included in each memory block MB in the second memory block array 123. As an example, in the pre-test, the test column address generator 13A can generate a first test column address TCAD1<6:1> to select the first column line YL included in each memory block MB in the first memory block array 121. <1> Furthermore, a second test column address TCAD2<6:1> can be generated to select the thirty-third column line YL of each memory block MB included in the second memory block array 123. <33> Since the test column address generator 13A generates the first test column address TCAD1<6:1> and the second test column address TCAD2<6:1>, the column lines selected to perform repair operations together in the pre-test can be checked for defective column lines that need to be repaired through the pre-test.In the post-test, the test column address generator 13A can generate a first test column address TCAD1<6:1> to select one of the column lines YL included in each memory block MB in the first memory block array 121, and can generate a second test column address TCAD2<6:1> to select the same column line among the column lines YL included in each memory block MB in the second memory block array 123. As an example, in the post-test, the test column address generator 13A can generate a first test column address TCAD1<6:1> to select the first column line YL included in each memory block MB in the first memory block array 121. <1> Furthermore, a second test column address TCAD2<6:1> can be generated to select the first column line YL of each memory block MB included in the second memory block array 123. <1> Since the test column address generator 13A generates the first test column address TCAD1<6:1> and the second test column address TCAD2<6:1>, the column lines that were not repaired together are selected in the subsequent test. Therefore, it can prevent or reduce the selection of multiple redundant column lines RYL that are repaired together at the same time, and check whether the repair operation is performed correctly through the subsequent test.

[0071] Figure 17 and Figure 18 This is a diagram used to illustrate the pre-test operation.

[0072] like Figure 17 As shown, the storage bank 101 may include: a first storage block array 121, a second storage block array 123, and redundant storage blocks 125. Each of the first storage block array 121 and the second storage block array 123 may include multiple storage blocks MB.

[0073] like Figure 17 As shown, the column line selection circuit 103A can receive a first test mode signal TM1, a first test column address TCAD1, and a second test column address TCAD2. The column line selection circuit 103A may include multiple column decoders (CDECs). When performing a pre-test and receiving the first test mode signal TM1, based on the first test column address TCAD1 and the second test column address TCAD2 generated from the column address CAD, the column line selection circuit 103A can select one of the column lines YL included in each memory block MB in the first memory block array 121, and can select another column line YL included in each memory block MB in the second memory block array 123.

[0074] like Figure 18As shown, when inputting YL to select the first column line in the pre-test... <1> When generating the column address CADD, the first column line YL of the storage block MB included in the first storage block array 121 can be obtained from the first test column address TCAD1 generated from the column address CADD. <1> Output the first memory block data MBD1. Additionally, when the input is used to select the first column line YL... <1> When the column address CADD is obtained, the 33rd column line YL of the storage block MB included in the second storage block array 123 can be obtained from the second test column address TCAD2 generated from the column address CADD. <33> Output the second memory block data MBD2. Then, sequentially input the data for selecting the second column line YL. <2> The column address CADD is used to select the sixty-fourth column line YL. <64> The column address CADD is used, and based on the first test column address TCAD1 and the second test column address TCAD2 generated according to each column address CADD, the first storage block data MBD1 and the second test column address TCAD2 can be generated and output sequentially.

[0075] Figure 19 and 20 This is a diagram showing the test operation after the illustration.

[0076] like Figure 19 As shown, the storage bank 101 may include a first storage block array 121, a second storage block array 123, and redundant storage blocks 125. Each of the first storage block array 121 and the second storage block array 123 may include multiple storage blocks MB.

[0077] like Figure 19As shown, the column line selection circuit 103B can receive a second test mode signal TM2, a first test column address TCAD1, a second test column address TCAD2, redundant fuse data RFD, and normal fuse data NFD. The column line selection circuit 103B can include multiple column decoders CDEC. When a post-test is performed and the second test mode signal TM2 is received, based on the first test column address TCAD1 and the second test column address TCAD2 generated from the column address CADD, the column line selection circuit 103B can select one of the column lines YL included in each memory block MB in the first memory block array 121 and can also select the same column line YL included in each memory block MB in the second memory block array 123. The column line selection circuit 103B can also select one of the column lines YL included in each memory block MB in the defective first memory block array 121 by using one of the redundant column lines RYL of the redundant memory block RED MB to replace the column line, based on the redundant fuse data RFD. The column line selection circuit 103B can select one column line YL of each memory block MB included in the defective second memory block array 123 by replacing a column line with one of the redundant column lines RYL of the redundant memory block RED MB, based on the redundant fuse data RFD. The column line selection circuit 103B can also select one column line YL of each memory block MB included in the defective first memory block array 121 by replacing a column line with another column line from the column lines YL of the memory block MB, based on the normal fuse data NFD. The column line selection circuit 103B can also select one column line YL of the memory block MB included in the defective second memory block array 123 by replacing a column line with another alternative column line from the column lines YL of the memory block MB, based on the normal fuse data NFD.

[0078] like Figure 20As shown, in the post-test, when the input is used to select the first column line YL <1> When generating the column address CADD, the first column line YL of the storage block MB included in the first storage block array 121 can be obtained from the first test column address TCAD1 generated from the column address CADD. <1> Output the first storage block data MBD1. Simultaneously, the first column line YL of the storage block MB included in the first storage block array 121... <1> If a fault occurs in one of the redundant storage lines 125, and one of the redundant column lines RYL in the redundant storage block 125 is used to replace the faulty column line, the redundant storage block data RMBD can be output from the redundant storage block 125. Additionally, when the input is used to select the first column line YL... <1> When the column address CADD is obtained, the first column line YL of the storage block MB included in the second storage block array 123 can be obtained from the second test column address TCAD2 generated from the column address CADD. <1> Output the second storage block data MBD2. Additionally, the first column line YL of the storage block MB included in the second storage block array 123... <1> If a fault occurs in one of the redundant storage blocks 125, and the redundant column line RYL of the redundant storage block 125 is used to replace the faulty column line, the redundant storage block data RMBD can be output from the redundant storage block 125. Afterwards, sequential inputs are used to select the second column line YL. <2> The column address CADD is used to select the sixty-fourth column line YL. <64> The column address CADD is used, and based on the first test column address TCAD1 and the second test column address TCAD2 generated according to each column address CADD, the first storage block data MBD1, the second storage block data MBD2 and the redundant storage block data RMBD can be generated and output sequentially.

[0079] Figure 21 The diagram is based on Figure 1 The block diagram shows an example of the configuration of shift control circuit 15A. (See attached diagram.) Figure 21 As shown, the shift control circuit 15A may include a fuse data decoder 151 and a shift signal generator 153.

[0080] The fuse data decoder 151 can generate a fuse flag FFLAG, fuse column data FCAD, and fuse latch signal FLAT based on redundant fuse data RFD. The fuse flag FFLAG can be activated depending on whether a fault has occurred. For example, when a fault occurs in at least one of the memory blocks MB included in the first memory block array 121 or in at least one of the memory blocks MB included in the second memory block array 123, the fuse flag FFLAG can be activated to a logic "high" level. The fuse column data FCAD can include information about the set of column lines of the memory block MB in which the fault occurred. For example, when a fault occurs in the first set of column lines (1st YLSET) of the memory block MB, the fuse column data FCAD can be set to a logic "low" level, and when a fault occurs in the second set of column lines (2nd YLSET) of the memory block MB, the fuse column data FCAD can be set to a logic "high" level. The fuse latch signal FLAT can include information about the memory blocks MB that are being repaired together. As an example, when the first column line set (1st YL SET) of the memory block MB included in the first memory block array 121 and the second column line set (2nd YL SET) of the memory block MB included in the second memory block array 123 are repaired together, the fuse latch signal FLAT can be set to a logic "low" level, and when the second column line set (2nd YL SET) of the memory block MB included in the first memory block array 121 and the first column line set (1st YL SET) of the memory block MB included in the second memory block array 123 are repaired together, the fuse latch signal FLAT can be set to a logic "high" level.

[0081] The shift signal generator 153 can generate a first shift signal SFT1 and a second shift signal SFT2 based on the fuse flag FFLAG, the fuse column data FCAD, and the fuse latch signal FLAT. When a fault in a memory block MB included in the first memory block array 121 is repaired, the shift signal generator 153 can generate the first shift signal SFT1, which is activated at a logic "high" level. For example, when a fault occurs in the first column line set (1st YL SET) of the memory block MB included in the first memory block array 121, and the first column line set (1st YL SET) of the memory block MB included in the first memory block array 121 and the second column line set (2nd YL SET) of the memory block MB included in the second memory block array 123 are repaired together, the shift signal generator 153 can receive the fuse flag FFLAG activated at a logic "high" level, the fuse column data FCAD at a logic "low" level, and the fuse latch signal FLAT at a logic "low" level to generate a first shift signal SFT1 activated at a logic "high" level. As another example, when a fault occurs in the second column line set (2nd YL SET) of the memory block MB included in the first memory block array 121, and the second column line set (2nd YL SET) of the memory block MB included in the first memory block and the first column line set (1st YL SET) of the memory block MB included in the second memory block array 123 are repaired together, the shift signal generator 153 can receive the fuse flag FFLAG activated at a logic "high" level, the fuse column data FCAD at a logic "high" level, and the fuse latch signal FLAT at a logic "high" level to generate a first shift signal SFT1 activated at a logic "high" level.

[0082] When a fault in a memory block MB included in the second memory block array 123 is repaired, the shift signal generator 153 can generate a second shift signal SFT2 activated at a logic "high" level. As an example, when a fault occurs in the first column line set (1st YL SET) of a memory block MB included in the second memory block array 123, and both the first column line set (1st YL SET) of the memory block MB included in the second memory block array 123 and the second column line set (2nd YL SET) of the memory block MB included in the first memory block array 121 are repaired, the shift signal generator 153 can receive a fuse flag FFLAG activated at a logic "high" level, fuse column data FCAD at a logic "low" level, and a fuse latch signal FLAT at a logic "high" level to generate the second shift signal SFT2 activated at a logic "high" level. As another example, when a fault occurs in the second column line set (2nd YL SET) of the memory block MB included in the second memory block array 123, and the second column line set (2nd YL SET) of the memory block MB included in the second memory block array 123 and the first column line set (1st YL SET) of the memory block MB included in the first memory block array 121 are repaired together, the shift signal generator 153 can receive the fuse flag FFLAG activated at a logic "high" level, the fuse column data FCAD at a logic "high" level, and the fuse latch signal FLAT at a logic "low" level to generate a second shift signal SFT2 activated at a logic "high" level.

[0083] Figure 22 The diagram is based on Figure 21 The circuit diagram shows an example of the configuration of shift signal generator 153A.

[0084] like Figure 22As shown, the shift signal generator 153A may include: inverters 154_1 to 154_5, transmission gates 155_1 and 155_2, NAND gates 156_1 and 156_2, NOR gates 157_1 and 157_2, PMOS transistors 158_1 and 158_2, and NMOS transistors 159_1 and 159_2. Inverter 154_1 can invert the buffered fuse latch signal FLAT to output an inverted buffered signal of the fuse latch signal FLAT. When the fuse latch signal FLAT is at a logic "low" level, inverter 154_2 can invert the buffered fuse column data FCAD to output an inverted buffered signal of the fuse column data FCAD to node n154_1. Inverter 154_3 can invert the buffered fuse flag FFLAG to output an inverted buffered signal of the fuse flag FFLAG. When the fuse latch signal FLAT is at a logic "high" level, inverter 154_4 can invert the buffered fuse column data FCAD to output the inverted buffered signal of the fuse column data FCAD to node n154_2. Inverter 154_5 can invert the buffered fuse flag FFLAG to output the inverted buffered signal of the fuse flag FFLAG. When the fuse latch signal FLAT is at a logic "high" level, transmission gate 155_1 can output the fuse column data FCAD to node n154_1. When the fuse latch signal FLAT is at a logic "low" level, transmission gate 155_2 can output the fuse column data FCAD to node n154_2. NAND gate 156_1 can perform a logical NAND operation on the signal of node n154_1 and the fuse flag FFLAG to generate the first pull-up signal PU1. NAND gate 156_2 performs a logical NAND operation on the signal at node n154_2 and the fuse flag FFLAG to generate a second pull-up signal PU2. NOR gate 157_1 performs a logical NOR operation on the signal at node n154_1 and the output signal of inverter 154_3 to generate a first pull-down signal PD1. NOR gate 157_2 performs a logical NOR operation on the signal at node n154_2 and the output signal of inverter 154_5 to generate a second pull-down signal PD2. PMOS transistor 158_1 can receive the first pull-up signal PU1 activated at a logic "high" level to drive the first shift signal SFT1 to a logic "high" level. PMOS transistor 158_2 can receive the second pull-up signal PU2 activated at a logic "low" level to drive the second shift signal SFT2 to a logic "high" level. NMOS transistor 159_1 can receive a first pull-down signal PD1 activated at a logic "high" level to drive the first shift signal SFT1 to a logic "low" level. NMOS transistor 159_2 can receive a second pull-down signal PD2 activated at a logic "high" level to drive the second shift signal SFT2 to a logic "low" level.

[0085] Reference Figure 22 and Figure 23 Describe the operation of the shift signal generator 153A.

[0086] When a fault occurs in the first column line set (1st YL SET) of the memory block MB included in the first memory block array 121, and the first column line set (1st YL SET) of the memory block MB included in the first memory block array 121 and the second column line set (2nd YL SET) of the memory block MB included in the second memory block array 123 are repaired together, a fuse flag FFLAG activated at a logic "high" level and fuse latch signals FLAT and fuse column data FCAD both set to a logic "low" level are generated. When both fuse latch signals FLAT and fuse column data FCAD are set to a logic "low" level, inverter 154_2 sets node n154_1 to a logic "high" level, and transmission gate 155_2 sets node n154_2 to a logic "low" level. Based on node n154_1 set to logic "high", NAND gate 156_1 generates a first pull-up signal PU1 activated to logic "low", and NOR gate 157_1 generates a first pull-down signal PD1 deactivated to logic "low". A first shift signal SFT1 activated to logic "high" is generated by PMOS transistor 158_1, which is turned on by the first pull-up signal PU1 activated to logic "low".

[0087] When the second column line set (2nd YL SET) of the memory block MB included in the second memory block array 123 fails, and the second column line set (2nd YL SET) of the memory block MB included in the second memory block array 123 and the first column line set (1st YL SET) of the memory block MB included in the first memory block array 121 are repaired together, a fuse flag FFLAG activated at a logic "high" level, a fuse latch signal FLAT at a logic "low" level, and fuse column data FCAD at a logic "high" level are generated. When the fuse latch signal FLAT is set to a logic "low" level and the fuse column data FCAD is set to a logic "low" level, inverter 154_2 sets node n154_1 to a logic "low" level, and transmission gate 155_2 sets node n154_2 to a logic "high" level. Based on node n154_2 set to logic "high", NAND gate 156_2 generates a second pull-up signal PU2 activated to logic "low", and NOR gate 157_2 generates a second pull-down signal PD2 deactivated to logic "low". A second shift signal SFT2 activated to logic "high" is generated by PMOS transistor 158_2, which is turned on by the second pull-up signal PU2 activated to logic "low".

[0088] When the second column line set (2nd YL SET) of the memory block MB included in the first memory block array 121 fails, and the second column line set (2nd YL SET) of the memory block MB included in the first memory block array 121 and the first column line set (1st YL SET) of the memory block MB included in the second memory block array 123 are repaired together, a fuse flag FFLAG activated to a logic "high" level and fuse latch signals FLAT and fuse column data FCAD both set to a logic "high" level are generated. When both the fuse latch signal FLAT and the fuse column data FCAD are set to a logic "high" level, transmission gate 155_1 sets node n154_1 to a logic "high" level, and inverter 154_4 sets node n154_2 to a logic "high" level. Based on node n154_1 set to logic "high", NAND gate 156_1 generates a first pull-up signal PU1 activated to logic "low", and NOR gate 157_1 generates a first pull-down signal PD1 deactivated to logic "low". A first shift signal SFT1 activated to logic "high" is generated by PMOS transistor 158_1, which is turned on by the first pull-up signal PU1 activated to logic "low".

[0089] When a fault occurs in the first column line set (1st YL SET) of the memory block MB included in the second memory block array 123, and the first column line set (1st YL SET) of the memory block MB included in the second memory block array 123 and the second column line set (2nd YL SET) of the memory block MB included in the first memory block array 121 are repaired together, a fuse flag FFLAG activated at a logic "high" level, a fuse latch signal FLAT at a logic "high" level, and fuse column data FCAD at a logic "low" level are generated. When the fuse latch signal FLAT is set to a logic "high" level and the fuse column data FCAD is set to a logic "low" level, transmission gate 155_1 sets node n154_1 to a logic "low" level, and inverter 154_4 sets node n154_2 to a logic "high" level. Based on node n154_2 set to logic "high", NAND gate 156_2 generates a second pull-up signal PU2 activated to logic "low", and NOR gate 157_2 generates a second pull-down signal PD2 deactivated to logic "low". A second shift signal SFT2 activated to logic "high" is generated by PMOS transistor 158_2, which is turned on by the second pull-up signal PU2 activated to logic "low".

[0090] Figure 24 The diagram is based on Figure 1 The block diagram shows an example of the configuration of the input / output control circuit 17A. (See attached image.) Figure 24 As shown, the input / output control circuit 17A may include: a first input / output shift circuit 161, a first drive circuit 163, a second input / output shift circuit 165, and a second drive circuit 167.

[0091] The first input / output shift circuit 161 can output the first memory block data MBD1 received via the first local line LIO1 to the first driver circuit 163 based on the first shift signal SFT1, or it can shift a portion of the redundant memory block data RMBD and the first memory block data MBD1 received via the redundant local line RLIO to output the shifted data to the first driver circuit 163. For example, when a fault in the memory block MB included in the first memory block 121 is repaired, the first input / output shift circuit 161 receives the first shift signal SFT1 activated at a logic "high" level, and the first input / output shift circuit 161 can sequentially shift the redundant memory block data RMBD and a portion of the first memory block data MBD1 to output the shifted data to the first driver circuit 163. As another example, when the memory block MB included in the first memory block array 121 does not contain a fault, the first input / output shift circuit 161 receives a deactivated first shift signal SFT1, and the first input / output shift circuit 161 can output the first memory block data MBD1 to the first drive circuit 163.

[0092] The first driving circuit 163 can drive the first driving data DRD1 based on the signal received from the first input / output shift circuit 161. For example, when a fault in a memory block MB included in the first memory block array 121 is repaired, causing a sequentially shifted portion of the first memory block data MBD1 and the redundant memory block data RMBD to be output from the first input / output shift circuit 161, the first driving circuit 163 can drive the first driving data DRD1 based on the shifted and received portions of the first memory block data MBD1 and the redundant memory block data RMBD. As another example, when the memory block MB included in the first memory block array 121 does not contain a fault and the first memory block data MBD1 is output from the first input / output shift circuit 161, the first driving circuit 163 can drive the first driving data DRD1 based on the received first memory block data MBD1.

[0093] The second input / output shift circuit 165 can output the second memory block data MBD2 received via the second local line LIO2 to the second drive circuit 167 based on the second shift signal SFT2, or it can shift a portion of the redundant memory block data RMBD and the second memory block data MBD2 received via the redundant local line RLIO to output the shifted data to the second drive circuit 167. As an example, when a fault in the memory block MB included in the second memory block 123 is repaired, the second input / output shift circuit 165, which receives the second shift signal SFT2 activated at a logic "high" level, can sequentially shift the redundant memory block data RMBD and a portion of the second memory block data MBD2 to output the shifted data to the second drive circuit 167. As another example, when the memory block MB included in the second memory block array 123 does not contain a fault, the second input / output shift circuit 165, which receives the deactivated second shift signal SFT2, can output the second memory block data MBD2 to the second drive circuit 167.

[0094] The second driving circuit 167 can drive the second driving data DRD2 based on the signal received from the second input / output shift circuit 165. As an example, when a fault in a memory block MB included in the second memory block array 123 is repaired, causing a sequentially shifted portion of the second memory block data MBD2 and redundant memory block data RMBD to be output from the second input / output shift circuit 165, the second driving circuit 167 can drive the second driving data DRD2 based on the shifted and received portions of the second memory block data MBD2 and redundant memory block data RMBD. As another example, when a fault is not present in the memory block MB included in the second memory block array 123, causing the second memory block data MBD2 to be output from the second input / output shift circuit 165, the second driving circuit 167 can drive the second driving data DRD2 based on the received second memory block data MBD2.

[0095] Figure 25 The diagrams are based on... Figure 24 A diagram showing the configuration of the first input / output shift circuit 161A and the first drive circuit 163A, as illustrated in the example of the first input / output shift circuit 161 and the first drive circuit 163A.

[0096] like Figure 25As shown, the first input / output shift circuit 161A may include an inverter 160 and MOS transistors 163_1 to 163_5. The inverter 160 can invert the buffered first shift signal SFT1 to generate a first inverted shift signal SFT1B. NMOS transistors 163_1, 163_3, and 163_4 can be turned on by receiving the first inverted shift signal SFT1B, which is set to a logic "high" level, when the first shift signal SFT1 is deactivated to a logic "low" level. When NMOS transistor 163_1 is turned on, the first line LIO1 via the first local line... <1> The first bit of the received first storage block data, MBD1 <1> The first driver DRV can be output to the first driver circuit 163A. When the NMOS transistor 163_3 is turned on, the second line LIO1 via the first local line... <2> The second bit MBD1 of the received first storage block data <2> The output can be sent to the second driver DRV of the first drive circuit 163A. When the NMOS transistor 163_4 is turned on, the output is sent via the sixteenth line LIO1 of the first local line. <16> The sixteenth bit of the first block of memory received (MBD1) <16> It can output to the sixteenth driver DRV of the first drive circuit 163A. When the first shift signal SFT1 is activated, NMOS transistors 163_2 and 163_5 can be turned on. When NMOS transistor 163_2 is turned on, the second line LIO1 via the first local line... <2> The second bit MBD1 of the received first storage block data <2> The first driver DRV of the first driving circuit 163A can be output. When NMOS transistor 163_5 is turned on, the redundant memory block data RMBD received via the redundant local line RLIO can be output to the sixteenth driver DRV of the first driving circuit 163A. The first input / output shift circuit 161A can shift the second to sixteenth bits MBD1<2:16> of the first memory block data and the redundant memory block data RMBD, so that the shifted bits and data can be output to the first driving circuit 163A via NMOS transistors 163_2 and 163_5, which are turned on when the first shift signal SFT1 is activated. The first input / output shift circuit 161A can output the first to sixteenth bits MBD1<1:16> of the first memory block data to the first driving circuit 163A via NMOS transistors 163_1, 163_3 and 163_4, which are turned on when the first shift signal SFT1 is deactivated.

[0097] like Figure 25As shown, the first driving circuit 163A may include multiple driver DRVs. Based on the signal received from the first input / output shift circuit 161A, each of the multiple driver DRVs in the first driving circuit 163A can drive the first to sixteenth bits of the first driving data, DRD1<1:16>. Based on the shift and reception of the second to sixteenth bits of the first memory block data, MBD1<2:16>, and redundant memory block data, RMBD, when the first shift signal SFT1 is activated, the first driving circuit 163A can drive the first to sixteenth bits of the first driving data, DRD1<1:16>. Based on the first to sixteenth bits of the first memory block data, MBD1<1:16>, received when the first shift signal SFT1 is deactivated, the first driving circuit 163A can drive the first to sixteenth bits of the first driving data, DRD1<1:16>.

[0098] Figure 26 and Figure 27 The diagram is drawn by Figure 25 The diagram shows the shift operation performed by the first shift signal SFT1.

[0099] like Figure 26 As shown, when the first shift signal SFT1 is deactivated to a logic "low" level, NMOS transistors 163_1, 163_3, and 163_4 are turned on, while NMOS transistors 163_2 and 163_5 are turned off. This allows the first input / output shift circuit 161A to output the first to sixteenth bits MBD1<1:16> of the first memory block data to the first driver circuit 163A. The first driver circuit 163A can then drive the first to sixteenth bits DRD1<1:16> of the first driver data based on the received first to sixteenth bits MBD1<1:16> of the first memory block data.

[0100] like Figure 27 As shown, when the first shift signal SFT1 is activated to a logic "high" level, NMOS transistors 163_1, 163_3, and 163_4 are turned off, and NMOS transistors 163_2 and 163_5 are turned on. This allows the first input / output shift circuit 161A to shift the first to sixteenth bits (MBD1<1:16>) of the first memory block data and the redundant memory block data RMBD, and output the shifted bits and data to the first driver circuit 163A. The first driver circuit 163A can drive the first to sixteenth bits (DRD1<1:16>) of the first driver data based on the shifted and received first to sixteenth bits (MBD1<1:16>) of the first memory block data and the redundant memory block data RMBD.

[0101] Figure 28 The diagrams are based on... Figure 24The diagram shows the configuration of the second input / output shift circuit 165A and the second drive circuit 167A, which are examples of the second input / output shift circuit 165 and the second drive circuit 167A.

[0102] like Figure 28As shown, the second input / output shift circuit 165A may include an inverter 171 and NMOS transistors 173_1 to 173_5. Inverter 171 can invert the buffered second shift signal SFT2 to generate a second inverted shift signal SFT2B. NMOS transistors 173_1, 173_3, and 173_4 can receive the second inverted shift signal SFT2B, which is set to a logic "high" level, when the second shift signal SFT2 is deactivated to a logic "low" level to be turned on. When NMOS transistor 173_1 is turned on, the second input / output shift circuit 165A can transmit the first line LIO2 via the second local line. <1> The first MBD2 of the received second storage block data <1> The first driver DRV is output to the second driver circuit 167A. When the NMOS transistor 173_3 is turned on, the second input / output shift circuit 165A can shift the second line LIO2 via the second local line. <2> The second bit (MBD2) of the received second storage block data <2> The output is to the second driver DRV of the second drive circuit 167A. When the NMOS transistor 173_4 is turned on, the second input / output shift circuit 165A can shift the output via the sixteenth line LIO2 of the second local line. <16> The sixteenth bit of the received second storage block data (MBD2) <16> The output is to the sixteenth driver DRV of the second drive circuit 167A. When the second shift signal SFT2 is activated, NMOS transistors 173_2 and 173_5 can be turned on. When NMOS transistor 173_2 is turned on, the second input / output shift circuit 165A can shift the second line LIO2 via the second local line. <2> The second bit (MBD2) of the received second storage block data <2> The first driver DRV of the second driver circuit 167A is output. When NMOS transistor 173_5 is turned on, the second input / output shift circuit 165A can output the redundant memory block data RMBD received via the redundant local line RLIO to the sixteenth driver DRV of the second driver circuit 167A. The second input / output shift circuit 165A can shift the second to sixteenth bits MBD2<2:16> of the second memory block data and the redundant memory block data RMBD, so as to output the shifted bits and data to the second driver circuit 167A via NMOS transistors 173_2 and 173_5, which are turned on when the second shift signal SFT2 is activated. The second input / output shift circuit 165A can output the first to sixteenth bits MBD2<1:16> of the second memory block data to the second driver circuit 167A via NMOS transistors 173_1, 173_3 and 173_4, which are turned on when the second shift signal SFT2 is deactivated.

[0103] like Figure 28As shown, the second drive circuit 167A may include multiple driver DRVs. Based on the signal received from the second input / output shift circuit 165A, each of the multiple driver DRVs included in the second drive circuit 167A can drive the first to sixteenth bits of the second drive data, DRD2<1:16>. When the second shift signal SFT2 is activated, the second drive circuit 167A can drive the first to sixteenth bits of the second drive data, DRD2<1:16>, based on the shifted and received second memory block data, second to sixteenth bits, MBD2<2:16>, and redundant memory block data, RMBD. When the second shift signal SFT2 is deactivated, the second drive circuit 167A can drive the first to sixteenth bits of the second drive data, DRD2<1:16>, based on the received second memory block data, MBD2<1:16>.

[0104] Figure 29 and Figure 30 The diagram is drawn by Figure 28 The diagram shows the shift operation performed by the second shift signal SFT2 in the diagram.

[0105] like Figure 29 As shown, when the second shift signal SFT2 is deactivated to a logic "low" level, NMOS transistors 173_1, 173_3, and 173_4 are turned on, while NMOS transistors 173_2 and 173_5 are turned off. This allows the second input / output shift circuit 165A to output the first to sixteenth bits (MBD2<1:16>) of the second memory block data to the second driver circuit 167A. The second driver circuit 167A can then drive the first to sixteenth bits (DRD2<1:16>) of the second driver data based on the received first to sixteenth bits (MBD2<1:16>) of the second memory block data.

[0106] like Figure 30 As shown, when the second shift signal SFT2 is activated to a logic "high" level, NMOS transistors 173_1, 173_3, and 173_4 are turned off, and NMOS transistors 173_2 and 173_5 are turned on. This allows the second input / output shift circuit 165A to shift the second to sixteenth bits (MBD2<2:16>) of the second memory block data and the redundant memory block data RMBD, outputting the shifted bits and data to the second driver circuit 167A. The second driver circuit 167A can drive the first to sixteenth bits (DRD2<1:16>) of the second driver data based on the shifted and received second to sixteenth bits (MBD2<2:16>) of the second memory block data and the redundant memory block data RMBD.

[0107] Figure 31 The diagram is based on Figure 1The block diagram showing the configuration of test data generator 19A is an example of test data generator 19. (See also...) Figure 31 As shown, the test data generator 19A may include: a first comparator 181, a second comparator 183, and a compression circuit 185.

[0108] The first comparator 181 can compare the first drive data DRD1 with the first reference data REFD1 to generate a first comparison signal COM1. When performing a pre-test or post-test, the first comparator 181 can compare the first drive data DRD1 with the first reference data REFD1 to generate a first comparison signal COM1 having a set of logic bits set according to the comparison result. As an example, when the set of logic bits of the first drive data DRD1 is the same as the set of logic bits of the first reference data REFD1, the first comparator 181 can generate a first comparison signal COM1 including a set of logic bits set to a logic "low" level. As another example, when the set of logic bits of the first drive data DRD1 is different from the set of logic bits of the first reference data REFD1, the first comparator 181 can generate a first comparison signal COM1 set to have a set of logic bits, which includes at least one set of bits set to a logic "high" level.

[0109] The second comparator 183 can compare the second driving data DRD2 with the second reference data REFD2 to generate a second comparison signal COM2. When performing a pre-test or post-test, the second comparator 183 can compare the second driving data DRD2 with the second reference data REFD2 to generate a second comparison signal COM2 having a set of logic bits set according to the comparison result. For example, when the set of logic bits of the second driving data DRD2 is the same as the set of logic bits of the second reference data REFD2, the second comparator 183 can generate a second comparison signal COM2 including a set of logic bits set to a logic "low" level. As another example, when the set of logic bits of the second driving data DRD2 is different from the set of logic bits of the second reference data REFD2, the second comparator 183 can generate a second comparison signal COM2 set to have a set of logic bits including at least one set of bits set to a logic "high" level.

[0110] Compression circuit 185 can receive a first comparison signal COM1 from a first comparator 181 and a second comparison signal COM2 from a second comparator 183. Compression circuit 185 can compress the first comparison signal COM1 and the second comparison signal COM2 to generate test data TDQ. In one example, compression circuit 185 can compress one bit included in the first comparison signal COM1 and one bit included in the second comparison signal COM2 to generate test data TDQ. In another example, compression circuit 185 can compress multiple bits included in the first comparison signal COM1 and multiple bits included in the second comparison signal COM2 to generate test data TDQ.

[0111] Figure 32 It is based on Figure 31 The circuit diagram of the first comparator 181A is shown as an example of the first comparator 181. Figure 32As shown, the first comparator 181A may include multiple XOR operators 191_1 to 191_16. XOR operator 191_1 can be used to compare the first bit DRD1 of the first driving data. <1> And the first REFD1 of the first reference data <1> Perform a logical XOR operation to generate the first bit COM1 of the first comparison data. <1> The XOR operator 191_1 can be used as the first bit of the first driving data DRD1. <1> And the first REFD1 of the first reference data <1> When they have the same logic level, the first bit COM1 of the first comparison data, which is set to logic "low", is generated. <1> And it can be the first bit of the first drive data DRD1 <1> And the first REFD1 of the first reference data <1> When different logic levels are present, the first bit COM1 of the first comparison data, set to logic "high", is generated. <1> The XOR operator 191_2 can be used to select the second bit of the first driving data, DRD1. <2> And the second REFD1 of the first reference data <2> Perform a logical XOR operation to generate the second bit COM1 of the first comparison data. <2> The XOR operator 191_2 can be used as the second bit of the first driving data, DRD1. <2> And the second REFD1 of the first reference data <2> When they have the same logic level, generate the second bit COM1 of the first comparison data set to logic "low". <2> And it can be the second bit of the first drive data, DRD1. <2> And the second REFD1 of the first reference data <2> When different logic levels are present, the second bit COM1 of the first comparison data, set to logic "high", is generated. <2> The XOR operator 191_16 can be used on the sixteenth bit of the first driving data, DRD1. <16> And the sixteenth REFD1 of the first reference data <16> Perform a logical XOR operation to generate the sixteenth bit COM1 of the first comparison data. <16> The XOR operator 191_16 can be used as the sixteenth bit of the first driving data, DRD1. <16> REFD1 of the sixteenth bit of the first reference data <16> When they have the same logic level, generate the sixteenth bit COM1 of the first comparison data set to logic "low". <16> And it can be the sixteenth bit of the first drive data, DRD1. <16> REFD1 of the sixteenth bit of the first reference data <16> When different logic levels are present, the sixteenth bit COM1 of the first comparison data, set to logic "high", is generated. <16> .

[0112] Figure 33 It is based on Figure 31 The circuit diagram of the second comparator 183A, as shown in the example of the second comparator 183. Figure 33As shown, the second comparator 183A may include multiple XOR operators 193_1 to 193_16. XOR operator 193_1 can be used to compare the first bit of the second driving data, DRD2. <1> The first REFD2 of the second reference data <1> Perform a logical XOR operation to generate the first bit COM2 of the second comparison signal. <1> The XOR operator 193_2 can be used to select the second bit of the second driving data, DRD2. <2> The second REFD2 of the second reference data <2> Perform a logical XOR operation to generate the second bit COM2 of the second comparison signal. <2> The XOR operator 193_16 can be used on the sixteenth bit of the second driving data, DRD2. <16> The sixteenth bit of the second reference data REFD2 <16> Perform a logical XOR operation to generate the sixteenth bit COM2 of the second comparison signal. <16> .

[0113] Figure 34 It is based on Figure 31 The circuit diagram of an example compression circuit 185A is shown. Figure 34 As shown, the compression circuit 185A may include multiple XOR operators 195_1 to 195_16. XOR operator 195_1 can be used to compare the first bit of the first comparison signal COM1. <1> The first bit of the second comparison signal COM2 <1> Perform a logical XOR operation to generate the first TD1 bit of the first test data. <1> The XOR operator 195_2 can be used to compare the second bit of the first comparison signal COM1. <2> The second bit of the second comparison signal COM2 <2> Perform a logical XOR operation to generate the second bit TD1 of the test data. <2> The XOR operator 195_16 can be used to compare the sixteenth bit of the first comparison signal COM1. <16> The sixteenth bit of the second comparison signal COM2 <16> Perform a logical XOR operation to generate the sixteenth bit TD1 of the test data. <16> .

[0114] Figure 35 and Figure 36 It is a diagram. Figure 34 The diagram shows the operation of the compression circuit 185A.

[0115] like Figure 35As shown, when the first to sixteenth bits of the first comparison signal COM1<1:16> are all set to logic "low" and the first to sixteenth bits of the second comparison signal COM2<1:16> are all set to logic "low", the first to sixteenth bits of the test data TDQ<1:16> are all generated as logic "low". Based on the first to sixteenth bits of the test data TDQ<1:16> all generated as logic "low", it can be confirmed that there are no faults in the memory blocks MB included in the first memory block array 121 and the memory blocks MB included in the second memory block array 123. More specifically, based on the first to sixteenth bits of the test data TDQ<1:16> generated in the pre-test being all set to logic "low", it can be confirmed that there are no faults in the memory blocks MB included in the first memory block array 121 and the memory blocks MB included in the second memory block array 123. Furthermore, based on the fact that the first to sixteenth bits of TDQ<1:16> in the test data generated in the subsequent test were all set to logic "low", it can be confirmed that the faults in the memory block MB included in the first memory block array 121 and the memory block MB included in the second memory block array 123 have been properly repaired.

[0116] like Figure 36 As shown, when the first bit of the first comparison signal COM1 <1> When set to logic "high", bits 2 to 16 of the first comparison signal (COM1<2:16>) are all set to logic "low", and bits 1 to 16 of the second comparison signal (COM2<1:16>) are all set to logic "low". The first bit of the test data (TDQ) is... <1> The first TDQ bit of the test data is generated as a logic "high" level, and the second to sixteenth bits of TDQ<2:16> are all generated as logic "low" levels. <1> The generation of a logic "high" level can confirm a fault in both the first memory block MB in the first memory block array 121 and the first memory block MB in the second memory block array 123. More specifically, this is based on the first TDQ bit of the test data that generates a logic "high" level during pre-testing. <1> This confirms that a fault has occurred in both the first memory block MB included in the first memory block array 121 and the first memory block MB included in the second memory block array 123. Additionally, based on the first TDQ bit of the test data that generates a logic "high" level in subsequent tests... <1> It can be confirmed that the faults included in the first storage block MB of the first storage block array 121 and the first storage block MB included in the second storage block array 123 have not been properly repaired.

[0117] As described above, the semiconductor device of this disclosure reduces the number of redundant fuses required for repair operations by implementing redundant fuses corresponding to multiple column lines, thereby reducing the layout area required for implementing redundant fuses. Furthermore, before performing a repair operation, the semiconductor device of this disclosure compresses the data output from the memory block from which the repair operation will be performed and confirms the presence of faulty cells, thereby reducing the time required to perform pre-tests to check for faulty cells requiring repair. Moreover, after performing a repair operation, the semiconductor device of this invention compresses the data output from the same column line of multiple memory blocks to confirm the presence of faulty cells, thereby reducing the time required to perform post-tests to confirm whether the repair operation for the faulty cells has been correctly performed.

[0118] The concept has been disclosed in conjunction with some embodiments described above. Those skilled in the art will understand that various modifications, additions, and substitutions are possible without departing from the scope and spirit of this disclosure. Therefore, the embodiments disclosed in this specification should not be considered in a limiting but illustrative manner. The scope of the concept is not limited to the foregoing description but is defined by the appended claims, and all distinctive features within the equivalent scope should be interpreted as included within the concept.

Claims

1. A semiconductor device, comprising: The storage unit includes a first storage block, a second storage block, and a redundant storage block; as well as A column line selection circuit is configured to: when a fault occurs in the first column line of the first memory block, control a first repair operation and a second repair operation to be performed simultaneously, wherein the first repair operation uses a first redundant line of the redundant memory block to replace the first column line of the first memory block, and the second repair operation uses a second redundant line of the redundant memory block to replace the second column line of the second memory block. When the first repair operation and the second repair operation are executed simultaneously, the first repair operation is performed within a first time interval, the second repair operation is performed within a second time interval, and the first time interval and the second time interval at least partially overlap with each other.

2. The semiconductor device according to claim 1, in, The storage medium includes a first storage block array and a second storage block array, and The first storage block is included in the first storage block array, and the second storage block is included in the second storage block array.

3. The semiconductor device according to claim 2, wherein, The column line selection circuit selects at least one of the first memory block array and the second memory block array based on the block array address.

4. The semiconductor device according to claim 1, wherein, The column line selection circuit selects at least one of the first memory block and the second memory block based on the block address.

5. The semiconductor device according to claim 1, in, The column line selection circuit selects one of the first column line and the second column line based on the column address. Specifically, the first column line is selected when the column address has a first set of logical bits, and the second column line is selected when the column address has a second set of logical bits. The second logical bit set is configured by inverting at least one bit in the first logical bit set.

6. The semiconductor device according to claim 1, in, The column line selection circuit selects one of the first column line and the second column line based on the column address. Specifically, the first column line is selected when the column address has a first set of logical bits, and the second column line is selected when the column address has a second set of logical bits. The second logical bit set is configured by inverting the most significant bit in the bits included in the first logical bit set.

7. The semiconductor device according to claim 1, in, The first storage block includes a first set of column lines and a second set of column lines, and the second storage block includes a third set of column lines and a fourth set of column lines. Specifically, when the most significant bit of the column address is at the first logic level, the first column line set and the third column line set are selected, and when the most significant bit of the column address is at the second logic level, the second column line set and the fourth column line set are selected.

8. The semiconductor device according to claim 7, wherein, When the first column line is included in the first column line set, the second column line is included in the fourth column line set.

9. The semiconductor device according to claim 7, wherein, When the first column line is included in the second column line set, the second column line is included in the third column line set.

10. The semiconductor device of claim 1, further comprising redundant fuse latches corresponding to the first column lines and the second column lines. in, The redundant fuse latch stores redundant fuse data including information about the first memory block and information about the first column line, and applies the redundant fuse data to the column line selection circuit.

11. The semiconductor device according to claim 1, wherein, When a fault occurs in the second column line of the first memory block, the column line selection circuit uses the first redundant line of the redundant memory block to replace the second column line of the first memory block, and uses the second redundant line of the redundant memory block to replace the first column line of the second memory block.

12. A semiconductor device, comprising: A test column address generator is configured to generate a first test column address and a second test column address based on the column address; as well as The core circuitry is configured to control the simultaneous execution of a first repair operation for a first memory block array and a second repair operation for a second memory block array based on the block array address, block address, and column address. It selects one of the column lines of each memory block in the first memory block array based on the first test column address to output first memory block data, and selects one of the column lines of each memory block in the second memory block array based on the second test column address to output second memory block data. When the first repair operation and the second repair operation are executed simultaneously, the first repair operation is performed within a first time interval, the second repair operation is performed within a second time interval, and the first time interval and the second time interval at least partially overlap with each other.

13. The semiconductor device according to claim 12, wherein, In the pre-test performed before the first repair operation and the second repair operation, the test column address generator generates the first test column address and the second test column address, which are configured to have different sets of logical bits.

14. The semiconductor device according to claim 13, wherein, The test column address generator generates the first test column address based on the column address, and transforms at least one of the bits included in the column address to generate the second test column address.

15. The semiconductor device according to claim 12, wherein, In the post-test performed after the first repair operation and the second repair operation, the test column address generator generates the first test column address and the second test column address, which are set to have the same set of logical bits.

16. The semiconductor device according to claim 12, in, The core circuit includes a memory bank, and The storage unit includes: a first storage block included in the first storage block array, a second storage block included in the second storage block array, and a redundant storage block.

17. The semiconductor device according to claim 12, in, The core circuit includes a column line selection circuit, and When a fault occurs in the first column line of the first memory block included in the first memory block array, the column line selection circuit controls a first repair operation and a second repair operation to be performed together. The first repair operation uses a first redundant line of a redundant memory block to replace the first column line of the first memory block, and the second repair operation uses a second redundant line of the redundant memory block to replace the second column line of the second memory block included in the second memory block array.

18. The semiconductor device according to claim 17, in, The column line selection circuit selects one of the first column line and the second column line based on the column address. Specifically, the first column line is selected when the column address has a first set of logical bits, and the second column line is selected when the column address has a second set of logical bits. The second logical bit set is configured by inverting at least one bit in the first logical bit set.

19. The semiconductor device according to claim 17, in, The first storage block includes a first set of column lines and a second set of column lines, and the second storage block includes a third set of column lines and a fourth set of column lines. Specifically, when the most significant bit of the column address is at a first logic level, the first column line set and the third column line set are selected; and when the most significant bit of the column address is at a second logic level, the second column line set and the fourth column line set are selected.

20. The semiconductor device according to claim 19, wherein, When the first column line is included in the first column line set, the second column line is included in the fourth column line set.

21. The semiconductor device of claim 19, wherein, When the first column line is included in the second column line set, the second column line is included in the third column line set.

22. The semiconductor device according to claim 17, wherein, The core circuit further includes redundant fuse latches, and The redundant fuse latch corresponds to the first column line and the second column line, stores redundant fuse data including information about the first memory block and information about the first column line, and applies the redundant fuse data to the column line selection circuit.

23. The semiconductor device according to claim 17, wherein, When a fault occurs in the second column line of the first storage block, the column line selection circuit controls a third repair operation and a fourth repair operation to be performed together. The third repair operation uses the first redundant line of the redundant storage block to replace the second column line of the first storage block, and the fourth repair operation uses the second redundant line of the redundant storage block to replace the first column line of the second storage block.

24. The semiconductor device according to claim 12, wherein, The core circuit repairs at least one memory block and outputs redundant memory block data, in which a fault has occurred in a column line selected based on the first test column address included in the first memory block array.

25. The semiconductor device of claim 24, further comprising a shift control circuit. in, The shift control circuit generates a first shift signal, which is activated when at least one memory block included in the first memory block array contains a faulty cell and the faulty cell is repaired based on the first test column address.

26. The semiconductor device of claim 25, further comprising input / output control circuitry. in, The input / output control circuit includes a first input / output shift circuit, which outputs the first storage block data based on the first shift signal, or shifts and outputs the redundant storage block data and a portion of the first storage block data.

27. The semiconductor device according to claim 26, wherein, When the first shift signal is deactivated, the input / output control circuit outputs the first memory block data, and when the first shift signal is activated, the input / output control circuit shifts and outputs the redundant memory block data and a portion of the first memory block data.

28. The semiconductor device according to claim 26, wherein, The input / output control circuit further includes a first drive circuit. The first driving circuit generates a first driving signal based on the first memory block data received when the first shift signal is deactivated, and generates the first driving signal based on a portion of the redundant memory block data and the first memory block data that are shifted and received when the first shift signal is activated.

29. The semiconductor device according to claim 22, in, The core circuit is configured as follows: In the memory blocks included in the first memory block array, repair at least one memory block that has a fault in the column line selected based on the first test column address; or In the memory blocks included in the second memory block array, when repairing at least one memory block that has failed in a column line selected based on the second test column address, redundant memory block data is output.

30. The semiconductor device of claim 29, further comprising a shift control circuit. in, The shift control circuit includes: A fuse data decoder generates fuse flags, fuse column data, and fuse latch signals based on the redundant fuse data; and A shift signal generator generates a first shift signal and a second shift signal based on the fuse flag, the fuse column data, and the fuse latch signal.

31. The semiconductor device of claim 30, further comprising input / output control circuitry. in, The input / output control circuit generates first drive data and second drive data from the first storage block data, the second storage block data, and the redundant storage block data based on the first shift signal and the second shift signal.

32. The semiconductor device of claim 31, further comprising a test data generator. in, The test data generator compares the first driving data with the first reference data to generate a first comparison signal, compares the second driving data with the second reference data to generate a second comparison signal, and compresses the first comparison signal and the second comparison signal to generate test data.

33. A semiconductor device, comprising: The core circuit is configured as follows: Based on the block array address, block address, and column address, control the simultaneous execution of the first repair operation on the first storage block array and the second repair operation on the second storage block array; Based on the first test column address, select one of the column lines of each storage block included in the first storage block array to output the first storage block data; Based on the second test column address, select one of the column lines of each storage block included in the second storage block array to output the second storage block data; as well as When performing the repair operation on the first storage block array based on the first test column address or on the second storage block array based on the second test column address, redundant storage block data is output. An input / output control circuit is configured to generate first drive data and second drive data from the first memory block data, the second memory block data, and the redundant memory block data based on a first shift signal and a second shift signal. as well as A test data generator is configured to compare the first driving data with first reference data to generate a first comparison signal, compare the second driving data with second reference data to generate a second comparison signal, and compress the first comparison signal and the second comparison signal to generate test data. When the first repair operation and the second repair operation are executed simultaneously, the first repair operation is performed within a first time interval, the second repair operation is performed within a second time interval, and the first time interval and the second time interval at least partially overlap with each other.

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