A method of manufacturing a semiconductor integrated circuit

Abstract

The application discloses a semiconductor integrated circuit manufacturing method, comprising the following steps: growing a hard mask medium layer on a semiconductor substrate, the semiconductor substrate comprising a heavily doped semiconductor substrate and a lightly doped epitaxial layer, the hard mask medium layer comprising a first silicon oxide, silicon nitride and a second silicon oxide; using the hard mask medium layer as a barrier layer, forming a first groove and a second groove on the semiconductor substrate by adopting a photolithography and etching process; depositing a third silicon oxide; removing the second silicon oxide and the third silicon oxide which are higher than the upper surface of the silicon nitride by adopting a chemical mechanical polishing process, and then removing the silicon nitride; the semiconductor integrated circuit manufacturing method has the advantages of completely eliminating the high step problem existing in the traditional manufacturing method and the like.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit manufacturing, and in particular to a manufacturing method of a semiconductor integrated circuit. BACKGROUND

[0002] With the development of semiconductor integrated circuit technology, people have higher requirements for the performance of semiconductor devices. However, the electrostatic discharge phenomenon occurs in various links such as packaging, packaging, transportation and use of semiconductor integrated circuits, causing the device to be electrostatically broken down and fail, so it is important for semiconductor devices to have electrostatic protection function.

[0003] For trench type semiconductor devices such as trench type MOSFET, SGT, IGBT, a typical manufacturing method with electrostatic protection function is to make a back-to-back diode in the trench type semiconductor device. Taking the trench type MOSFET as an example, a relatively thick dielectric layer is usually made outside the cell area of the MOSFET, and then a polysilicon diode is made above the dielectric layer. The characteristics of this method are that the process structure is relatively simple, and the disadvantages are that there is a large height difference between the cell area and the polysilicon diode area, that is, there is a high step, which increases the difficulty of planarization process and contact hole process, and reduces the integration of the device.

[0004] Because of the above problems, a new manufacturing method has emerged, that is, the polysilicon diode is made in the trench, and the top of the polysilicon diode is basically flat with the silicon plane, which solves the problem of height difference and greatly improves the integration of the device, but this method also faces many technical difficulties, the main problem is the isolation between the polysilicon diode and the cell area. Around these problems, the industry has proposed various methods, but there are still some deficiencies in practical application. Here, taking the granted invention patent 201310347156.2 as an example, at least the following problems exist:

[0005] (1) The patent claim 1 described "depositing silicon dioxide in the trench and etching back, forming a thick gate oxide at the bottom of the trench as an insulating layer between the subsequent formed electrostatic discharge protection circuit and the trench type power device, so that the electrostatic discharge protection circuit can be placed in the trench, the thickness of the thick gate oxide is 3000-4000 angstroms", corresponding to the schematic Figure 3 B, this step cannot be realized in practical process, because the area of the electrostatic discharge protection circuit is usually more than 100*100 microns, that is, the size of the trench where the electrostatic discharge protection circuit is located is greater than 100*100 microns, after the deposition of silicon dioxide, the thickness of silicon dioxide in the area outside the trench and the area at the bottom of the trench is the same, according to the step of etching back, it is impossible to selectively remove all the silicon dioxide outside the trench while retaining 3000-4000 angstroms of silicon dioxide in the trench.

[0006] (2) The patent claim 1 described "depositing undoped polysilicon, first polysilicon implantation, applying photoresist in the area where the electrostatic discharge protection circuit is to be formed, second polysilicon implantation, etching back to remove polysilicon above the trench, forming gate polysilicon and electrostatic discharge protection circuit polysilicon respectively", corresponding to the schematic Figure 3 C~3F, this step has structural problems in the practical process, because the boron ions in the second polysilicon implantation are only distributed in the surface layer of the polysilicon, and in the step of etching back to remove the polysilicon above the trench, the polysilicon above the trench in the area not covered by the photoresist is all etched off (corresponding to the schematic Figure 3 F), that is, the boron ion-doped surface layer of the polysilicon is etched off, so the doping purpose of the gate polysilicon cannot be achieved, that is, the gate polysilicon remaining in the trench is actually not doped, and the MOSFET cannot work normally.

[0007] (3) After the process step described in the patent claim 1 "etching back to remove polysilicon above the trench, forming gate polysilicon and electrostatic discharge protection circuit polysilicon respectively", corresponding to the schematic Figure 3 F, the electrostatic protection circuit polysilicon forms a very high step in the trench, that is, there is a large height difference between the surface of the polysilicon in the trench and the surface of the insulating layer, that is, this manufacturing method does not fundamentally solve the height difference problem, but only transfers the step from outside the trench to inside the trench, and there is still a great difficulty in the subsequent planarization process, and there is still a risk of metal residue at the step position.

[0008] In summary, the invention patent 201310347156.2 has no practical significance in production, and similarly, other published technical materials and patent information also have some problems, and the high step problem in the manufacturing method of the trench-type semiconductor device with electrostatic protection function has not been fundamentally solved.

[0009] The present application is directed to the above problems, and a new manufacturing method is proposed. SUMMARY

[0010] The present application provides a semiconductor integrated circuit manufacturing method, which has the advantages of completely eliminating the high step problem existing in the traditional manufacturing method, and solving the high step problem existing in the original manufacturing method of the trench-type semiconductor device.

[0011] According to the semiconductor integrated circuit manufacturing method provided by the embodiment of the present application, the following steps are included:

[0012] Growth of a hard mask medium layer on a semiconductor substrate, the semiconductor substrate comprising a heavily doped semiconductor substrate and a lightly doped epitaxial layer, the hard mask medium layer comprising a first silicon oxide, a silicon nitride, a second silicon oxide;

[0013] Formation of a first trench and a second trench on the semiconductor substrate using a photolithography and etching process with the hard mask medium layer as a barrier layer;

[0014] Deposition of a third silicon oxide;

[0015] Removal of the second silicon oxide and the third silicon oxide above the upper surface of the silicon nitride using a chemical mechanical polishing process, followed by removal of the silicon nitride;

[0016] Removal of the third silicon oxide and the first silicon oxide in areas other than the first trench using a photolithography and etching process with photoresist as a barrier layer, leaving the third silicon oxide at the bottom and sidewalls of the first trench, followed by removal of the photoresist;

[0017] Growth of a fourth silicon oxide using a thermal oxidation process, followed by removal of the fourth silicon oxide using an etching method;

[0018] Growth of a fifth silicon oxide (i.e. gate oxide) using a thermal oxidation process, deposition of polysilicon, first ion implantation doping of the polysilicon to form a first doped polysilicon;

[0019] Second ion implantation doping of the polysilicon in partial areas using a photolithography and ion implantation process with photoresist as a barrier layer to form a second doped polysilicon;

[0020] Removal of the photoresil and high-temperature annealing to diffuse the dopants of the first ion implantation doping and the second ion implantation doping to the bottom of the polysilicon, and to extend the polysilicon;

[0021] Removal of the first doped polysilicon and the second doped polysilicon above the upper surface of the fifth silicon oxide using a chemical mechanical polishing process, leaving the polysilicon (first doped polysilicon) in the first trench and leaving the polysilicon (second doped polysilicon) in the second trench;

[0022] Ion implantation followed by annealing to form a body region;

[0023] Formation of a source region using a photolithography, ion implantation and annealing process, and simultaneous formation of a third doped polysilicon in a designated area of the first doped polysilicon.

[0024] Preferably, before high-temperature annealing, the first doped polysilicon and the second doped polysilicon are only distributed on the surface of the polysilicon layer, and after high-temperature annealing, the dopants are distributed in the entire longitudinal region from the surface to the bottom of the polysilicon; the first doped polysilicon is the polysilicon diode region, i.e. the static protection circuit region, and the second doped polysilicon is the polysilicon gate of the MOSFET.

[0025] Preferably, the thickness of the first silicon oxide and the silicon nitride is 200-800 angstroms, and the thickness of the second silicon oxide is 1000-4000 angstroms.

[0026] Preferably, the depth of the first and second trenches is 0.8-1.6 microns, the width of the first trench is 100-400 microns, and the width of the second trench is 0.1-0.5 microns.

[0027] Preferably, the thickness of the third silicon oxide is 2000-5000 angstroms, and in this deposition process, the second trench is filled with the third silicon oxide due to its small width, and the third silicon oxide uniformly covers the bottom and sidewall of the first trench due to its large width.

[0028] Preferably, the chemical mechanical polishing is from top to bottom, and finally stops on the upper surface of the silicon nitride. Because the chemical mechanical polishing is selective, the third silicon oxide on the bottom and sidewall of the first trench is retained, and the upper surface of the third silicon oxide on the sidewall of the first trench is higher than the silicon surface, and the height of the upper surface is equal to the sum of the thicknesses of the first silicon oxide and the silicon nitride.

[0029] Preferably, the thickness of the fourth silicon oxide is 200-1300 angstroms, and the thickness of the fourth silicon oxide is less than the sum of the thicknesses of the first silicon oxide and the silicon nitride.

[0030] Preferably, the first and second ion implantation doping of the polysilicon are of opposite types, and the dose of the second ion implantation doping is larger.

[0031] The first ion implantation doping of the polysilicon is boron, and the dose is 1E14-5E14 per CM 2 The second ion implantation doping of the polysilicon is phosphorus, and the dose is 2E15-2E16 per CM 2 Thus, the first doped polysilicon is P-type, and the second doped polysilicon is N-type; or,

[0032] The first ion implantation doping of the polysilicon is phosphorus, and the dose is 1E14-5E14 per CM 2 The second ion implantation doping of the polysilicon is boron, and the dose is 2E15-2E16 per CM 2The first doped polysilicon is N type and the second doped polysilicon is P type.

[0033] The region of the first doped polysilicon completely covers and is larger than the region where the first trench is located, and the region of the second doped polysilicon completely covers and is larger than the region where the second trench is located.

[0034] Preferably, the photoetching, ion implantation and annealing form the source region, the dopant of the ion implantation is the same as the type of the second ion implantation of the polysilicon and is opposite to the type of the first ion implantation of the polysilicon, and the dose of the ion implantation is larger than the dose of the first ion implantation of the polysilicon.

[0035] The first ion implantation of the polysilicon is boron and the dose is 1E14-5E14 / CM 2 The ion implantation of the source region is phosphorus or arsenic and the dose is 2E15-8E15 / CM 2 The third doped polysilicon formed thereby is N type.

[0036] Alternatively, the first ion implantation of the polysilicon is phosphorus and the dose is 1E14-5E14 / CM 2 The ion implantation of the source region is boron and the dose is 2E15-8E15 / CM 2 The third doped polysilicon formed thereby is P type.

[0037] The technical scheme provided by the embodiment of the application can have the following beneficial effects.

[0038] The polysilicon diode formed by the application is completely located in the trench, the top of the polysilicon diode is at the same level as the upper surface of the silicon base of the cell region, and the high step problem existing in the traditional manufacturing method is completely eliminated, so that the difficulty of the planarization process and the like can be reduced, the process risk can be reduced, and the integration of the chip can be improved; the isolation layer, i.e., the third silicon oxide of the sidewall of the first trench, between the polysilicon diode and the cell region has a thickness of 2000-5000 angstroms and is uniformly covered from the bottom to the top of the first trench, and is a very safe and reliable isolation layer.

[0039] The manufacturing method disclosed by the application is formed after repeated research and repeated argumentation of all steps from practice, rather than a simple process combination by imagination, and compared with the manufacturing method for forming a polysilicon diode in a trench disclosed in the existing literature and patents, the application has more practical significance and feasibility. BRIEF DESCRIPTION OF DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments description. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0041] Figure 1-A A flowchart of a semiconductor integrated circuit manufacturing method of the present application;

[0042] Figure 1-B A flowchart of a semiconductor integrated circuit manufacturing method of the present application;

[0043] Figure 1 A structural diagram of step S1 of the present application;

[0044] Figure 2 A structural diagram of step S2 of the present application;

[0045] Figure 3 A structural diagram of step S3 of the present application;

[0046] Figures 4-5 A structural diagram of step S4 of the present application;

[0047] Figures 6-8 A structural diagram of step S5 of the present application;

[0048] Figures 9-10 A structural diagram of step S6 of the present application;

[0049] Figures 11-13 A structural diagram of step S7 of the present application;

[0050] Figure 14 A structural diagram of step S8 of the present application;

[0051] Figure 15 A structural diagram of step S9 of the present application;

[0052] Figure 16 A structural diagram of step S10 of the present application;

[0053] Figure 17 A structural diagram of step S11 of the present application;

[0054] Figure 18 A structural diagram of step S12 of the present application;

[0055] Figure 19 A structural diagram of the present application.

[0056] Figure 20 A top view of a polysilicon diode of the present application.

[0057] Reference Signs List:

[0058] 100. A method of manufacturing a semiconductor integrated circuit; 1, semiconductor substrate; 2, epitaxial layer; 3, first silicon oxide; 4, silicon nitride; 5, second silicon oxide; 6, first trench; 7, second trench; 8, third silicon oxide; 9, photoresist; 10, fourth silicon oxide; 11, fifth silicon oxide; 12, polysilicon; 12.1, first doped polysilicon; 12.2, second doped polysilicon; 12.3, third doped polysilicon; 13, photoresist; Wl, width of first trench; W2, width of second trench; 15, source region; 16.1, first contact hole; 16.2, second contact hole. DETAILED DESCRIPTION

[0059] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort belong to the scope of the present application.

[0060] It should also be understood that the terms used in the specification of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application. As used in the specification and the appended claims of the present application, the singular forms "a", "an" and "the" are intended to include the plural forms, unless the context clearly indicates otherwise.

[0061] It should be further understood that the term "and / or" used in the specification and the appended claims of the present application means any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0062] Please refer to Figures 1-A to 1 -B, the present application provides a method of manufacturing a semiconductor integrated circuit 100, comprising the following steps:

[0063] Step S1: growing a hard mask medium layer on a semiconductor substrate, the semiconductor substrate comprising a heavily doped semiconductor substrate 1 and a lightly doped epitaxial layer 2, the hard mask medium layer comprising a first silicon oxide 3, a silicon nitride 4, and a second silicon oxide 5 (see Figure 1 );

[0064] Step S2: using a photoetching and etching process to form a first trench 6 and a second trench 7 on the semiconductor substrate with the hard mask medium layer as a barrier layer (see Figure 2 );

[0065] Step S3: depositing a third silicon oxide 8 (see Fig. 3) ; Figure 3 ) ;

[0066] Step S4: removing the second silicon oxide 5 and the third silicon oxide 8 above the upper surface of the silicon nitride 4 by a chemical mechanical polishing process (see Fig. 4) ; and then removing the silicon nitride 4 (see Fig. 5) ; Figure 4 ) ; Figure 5 ) ;

[0067] Step S5: removing the third silicon oxide 8 and the first silicon oxide 3 in the area outside the first trench 6 by a lithography (see Fig. 6) and etching process, with the photoresist 9 as a barrier layer, and leaving the third silicon oxide 8 at the bottom and sidewall of the first trench 6 (see Fig. 7) ; and then removing the photoresist 9 (see Fig. 8) ; Figure 6 ) ; Figure 7 ) ; Figure 8 ) ;

[0068] Step S6: growing a fourth silicon oxide 10 by a thermal oxidation process (see Fig. 9) ; and then removing the fourth silicon oxide 10 by an etching process (see Fig. 10) ; Figure 9 ) ; Figure 10 ) ;

[0069] Step S7: growing a fifth silicon oxide 11, i.e. a gate oxide layer, by a thermal oxidation process (see Fig. 11) ; depositing a polysilicon 12 (see Fig. 12) ; and first ion implantation doping of the polysilicon 12 to form a first doped polysilicon 12.1 (see Fig. 13) ; Figure 11 ) ; Figure 12 ) ; Figure 13 ) ;

[0070] Step S8: second ion implantation doping of the polysilicon 12 in a partial area by a lithography and ion implantation process, with the photoresist 13 as a barrier layer, to form a second doped polysilicon 12.2 (see Fig. 14) ; Figure 14 ) ;

[0071] Step S9: removing the photoresil 13 and high-temperature annealing to diffuse the dopants of the first ion implantation doping and the second ion implantation doping to the bottom of the polysilicon, and to extend the polysilicon (see Fig. 15) ; Figure 15 ) ;

[0072] Step S10: removing the first doped polysilicon 12.1 and the second doped polysilicon 12.2 above the upper surface of the fifth silicon oxide 11 by a chemical mechanical polishing process, and leaving the polysilicon in the first trench 6 (the first doped polysilicon 12.1) and the polysilicon in the second trench 7 (the second doped polysilicon 12.2) (see Fig. 16) ; Figure 16 ) ;

[0073] Step S11: forming a body region 14 by ion implantation and then annealing (see Fig. 17) ; Figure 17 ) ;

[0074] Step S12: using photolithography, ion implantation, annealing process, forming source region 15, and simultaneously forming third doped polysilicon 12.3 in the set region of first doped polysilicon 12.1 (see Figure 18 ).

[0075] The subsequent process steps are conventional process steps, which are not described here. Among them, the first doped polysilicon 12.1 and the third doped polysilicon 12.3 are the polysilicon diode region of the subsequent polysilicon diode, i.e. the static protection circuit region, and the second doped polysilicon 12.2 is the polysilicon gate of the MOSFET.

[0076] Before high-temperature annealing, the first doped polysilicon 12.1 and the second doped polysilicon 12.2 are only distributed on the surface layer of the polysilicon, and after high-temperature annealing, the dopants are distributed in the entire longitudinal region from the surface to the bottom of the polysilicon.

[0077] It can be understood that in the present embodiment, the thicknesses of the first silicon oxide 3 and the silicon nitride 4 are 200-800 angstroms, and the thickness of the second silicon oxide 5 is 1000-4000 angstroms (the thicknesses of the first silicon oxide 3 and the silicon nitride 4 are thinner).

[0078] It can be understood that in the present embodiment, the depths of the first trench 6 and the second trench 7 are 0.8-1.6 microns, the width W1 of the first trench is 100-400 microns, and the width W2 of the second trench is 0.1-0.5 microns. (The region of the first trench is the region where the polysilicon diode is arranged, and the region of the second trench is the preset MOSFET cell region, which contains several second trenches, and the schematic diagram only shows two second trenches).

[0079] It can be understood that in the present embodiment, the thickness of the third silicon oxide 8 is 2000-5000 angstroms (i.e. 0.2-0.5 microns), and in this deposition process, the second trench 7 is filled with the third silicon oxide 8 because of its small width, and the third silicon oxide 8 uniformly covers the bottom and sidewall of the first trench 6 because of its large width.

[0080] It can be understood that in the present embodiment, the chemical mechanical polishing is from top to bottom, and finally stops at the upper surface of the silicon nitride 4. Because the chemical mechanical polishing is selective, as shown in Figure 4 , the third silicon oxide 8 at the bottom and sidewall of the first trench 6 is retained, and the upper surface of the third silicon oxide 8 at the sidewall position of the first trench 6 is higher than the silicon surface, and the thickness of the height is equal to the sum of the thicknesses of the first silicon oxide 3 and the silicon nitride 4.

[0081] It can be understood that in the embodiment, the thickness of the fourth silicon oxide 10 is 200-1300 angstroms, and the thickness of the fourth silicon oxide 10 needs to be less than the sum of the thicknesses of the first silicon oxide 3 and the silicon nitride 4, otherwise, after the step of removing the fourth silicon oxide 10 by etching is completed, the height of the upper surface of the third silicon oxide 8 at the sidewall position of the first trench 6 will be lower than the height of the silicon surface, resulting in that the subsequently formed polysilicon diode fails to have sufficient isolation layer between the silicon base. Figure 16 and Figure 19 It can be understood that in the embodiment, the step of removing the fourth silicon oxide 10 intentionally lowers the height of the upper surface of the third silicon oxide 8 but cannot be lower than the silicon surface.

[0082] It can be understood that in the embodiment, the first-time ion implantation doping of polysilicon and the second-time ion implantation doping of polysilicon are of opposite doping types, and the second-time ion implantation doping of polysilicon has a larger dose, specifically:

[0083] The first-time ion implantation doping of polysilicon is boron with a dose of 1E14-5E14 atoms / CM 2 The second-time ion implantation doping of polysilicon is phosphorus with a dose of 2E15-2E16 atoms / CM 2 Thus, the first doped polysilicon 12.1 is P-type, and the second doped polysilicon 12.2 is N-type; or,

[0084] The first-time ion implantation doping of polysilicon is phosphorus with a dose of 1E14-5E14 atoms / CM 2 The second-time ion implantation doping of polysilicon is boron with a dose of 2E15-2E16 atoms / CM 2 Thus, the first doped polysilicon 12.1 is N-type, and the second doped polysilicon 12.2 is P-type.

[0085] It can be understood that in the embodiment, the step of forming a source region by photolithography, ion implantation and annealing has the same type of dopant as the second-time ion implantation doping of polysilicon, i.e., the opposite type of the first-time ion implantation doping of polysilicon, and has a larger dose than the first-time ion implantation doping of polysilicon. Specifically:

[0086] The first-time ion implantation doping of polysilicon is boron with a dose of 1E14-5E14 atoms / CM 2 The source region ion implantation doping is phosphorus or arsenic with a dose of 2E15-8E15 atoms / CM 2 Thus, the third doped polysilicon 12.3 is N-type;

[0087] Or, the first-time ion implantation doping of polysilicon is phosphorus with a dose of 1E14-5E14 atoms / CM 2The source region is implanted with boron ions at a dose of 2E15-8E15 / cm2 2 The third doped polysilicon 12.3 formed is P-type.

[0088] And, the following important features are provided:

[0089] The third doped polysilicon 12.3 is formed in the preset region and is spacedly distributed in several regions, Figure 18 The example shown is three regions spacedly distributed in a central symmetrical arrangement (corresponding to a planar schematic Figure 20 ); the regions between the spacedly distributed third doped polysilicon 12.3 are the first doped polysilicon 12.1, and the doping types of the two are opposite, forming an NPNPN... or PNPNP... staggered arrangement, i.e., a back-to-back polysilicon diode (a polysilicon diode in series with a forward PN junction and a reverse PN junction), and in subsequent process steps, the first contact hole 16.1 and the second contact hole 16.2 are made to lead out the two ends of the back-to-back polysilicon diode, Figure 19 and Figure 20 as shown, and are respectively connected to the gate and the source of the MOSFET, i.e., a MOSFET integrated circuit with a self-provided electrostatic protection function is formed.

[0090] After step S9, as shown in Figure 15 , the region of the first doped polysilicon 12.1 completely covers and is larger than the region where the first trench 6 is located, and the region of the second doped polysilicon 12.2 completely covers and is larger than the region where the second trench 7 is located.

[0091] The technical scheme provided by the embodiment of the present application can include the following beneficial effects:

[0092] The polysilicon diode formed by the present application is completely located in the trench, the top of the polysilicon diode is at the same level as the upper surface of the silicon base of the cell region, and the high step problem existing in the traditional manufacturing method is completely eliminated, so that the difficulty of the planarization process step and the like can be reduced, the process risk can be reduced, and the integration of the chip can be improved; the isolation layer, i.e., the third silicon oxide of the first trench sidewall, between the polysilicon diode and the cell region is uniformly covered from the bottom to the top of the first trench, and is a very safe and reliable isolation layer.

[0093] The manufacturing method disclosed by the present application is formed after repeated research and repeated argumentation of all steps from practice, rather than a simple process combination based on imagination, and compared with the manufacturing method for forming a polysilicon diode in a trench disclosed in the existing literature and patents, the present application has more practical significance and feasibility.

[0094] The above merely illustrates the specific embodiments of the present application, but the protection scope of the present application is not limited thereto, and any skilled person in the art can easily think of various equivalent modifications or replacements within the technical range disclosed by the present application, and these modifications or replacements shall be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method of manufacturing a semiconductor integrated circuit, characterized by, The method comprises the following steps: growing a hard mask medium layer on a semiconductor substrate, the semiconductor substrate comprising a heavily doped semiconductor substrate and a lightly doped epitaxial layer, the hard mask medium layer comprising a first silicon oxide, silicon nitride and a second silicon oxide; forming a first groove and a second groove on the semiconductor substrate by using a photolithography and etching process with the hard mask medium layer as a barrier layer; depositing a third silicon oxide; removing the second silicon oxide and the third silicon oxide above the upper surface of the silicon nitride by using a chemical mechanical polishing process, and then removing the silicon nitride; removing the third silicon oxide and the first silicon oxide in the area outside the first groove by using a photolithography and etching process with photoresist as a barrier layer, and then removing the photoresist; growing a fourth silicon oxide by using a thermal oxidation process, and then removing the fourth silicon oxide by using an etching method; growing a fifth silicon oxide by using a thermal oxidation process, depositing polysilicon, and first ion implantation doping of the polysilicon to form a first doped polysilicon; second ion implantation doping of the polysilicon in a partial area by using a photolithography and ion implantation process with photoresist as a barrier layer to form a second doped polysilicon; removing the photoresist and high-temperature annealing to diffuse the dopants of the first ion implantation doping and the second ion implantation doping to the bottom of the polysilicon, and to extend the polysilicon; removing the first doped polysilicon and the second doped polysilicon above the upper surface of the fifth silicon oxide by using a chemical mechanical polishing process, and retaining the first doped polysilicon in the first groove and the second doped polysilicon in the second groove; forming a body region by ion implantation and then annealing; forming a source region by using a photolithography, ion implantation and annealing process, and simultaneously forming a third doped polysilicon in a set area of the first doped polysilicon.

2. The method of manufacturing a semiconductor integrated circuit according to claim 1, wherein Before high-temperature annealing, the first doped polysilicon and the second doped polysilicon are only distributed on the surface layer of the polysilicon, and after high-temperature annealing, the dopants are distributed in the entire longitudinal area from the surface to the bottom of the polysilicon; the first doped polysilicon is a polysilicon diode area for subsequent static protection circuit area, and the second doped polysilicon is a polysilicon gate of a MOSFET.

3. The method of manufacturing a semiconductor integrated circuit according to Claim 1, wherein The thickness of the first silicon oxide and the silicon nitride is respectively 200-800 angstroms, and the thickness of the second silicon oxide is 1000-4000 angstroms.

4. The method of manufacturing a semiconductor integrated circuit according to Claim 1, wherein The depth of the first groove and the second groove is 0.8-1.6 microns, the width of the first groove is 100-400 microns, and the width of the second groove is 0.1-0.5 microns.

5. The method of manufacturing a semiconductor integrated circuit according to Claim 1, wherein The thickness of the third silicon oxide is 2000-5000 angstroms, and in this deposition process, the second groove is filled with the third silicon oxide because of the small width, and the third silicon oxide uniformly covers the bottom and the sidewall of the first groove because of the large width.

6. The method of manufacturing a semiconductor integrated circuit according to Claim 1, wherein The chemical mechanical polishing is from top to bottom, and finally stops at the upper surface of the silicon nitride, because the chemical mechanical polishing is selective, the third silicon oxide on the bottom and sidewall of the first trench is reserved, and the height of the upper surface of the third silicon oxide on the sidewall of the first trench is higher than the silicon surface, and the height is equal to the sum of the thicknesses of the first silicon oxide and the silicon nitride.

7. The method of manufacturing a semiconductor integrated circuit according to Claim 1, wherein The thickness of the fourth silicon oxide is 200-1300 angstroms, and the thickness of the fourth silicon oxide is less than the sum of the thicknesses of the first silicon oxide and the silicon nitride.

8. The method of manufacturing a semiconductor integrated circuit according to Claim 1, wherein The first and second ion implantation doping of the polysilicon are opposite in type, and the dose of the second ion implantation doping of the polysilicon is larger. The first ion implantation of polysilicon is boron doped with a dose of 1E14-5E14 / cm2 2 The second ion implantation of polysilicon is phosphorus doped with a dose of 2E15-2E16 / cm2 2 The first doped polysilicon is P-type and the second doped polysilicon is N-type; or, The first ion implantation doping of polysilicon is phosphorus, and the dose is 1E14-5E14 / cm2 2 The second ion implantation doping of polysilicon is boron, and the dose is 2E15-2E16 / cm2 2 The first doped polysilicon is N type, and the second doped polysilicon is P type. The area of the first doped polysilicon completely covers and is larger than the area of the first trench, and the area of the second doped polysilicon completely covers and is larger than the area of the second trench.

9. The method of manufacturing a semiconductor integrated circuit according to Claim 1, wherein The photoetching, ion implantation and annealing form a source region, the dopant of this step is the same as the second ion implantation doping of the polysilicon, and is opposite to the first ion implantation doping of the polysilicon, and the dose of this step is larger than the first ion implantation doping of the polysilicon. The first ion implantation doping of the polysilicon is boron, and the dose is 1E14-5E14 / CM 2 The source region is ion implanted and doped with phosphorus or arsenic, and the dose is 2E15-8E15 / CM 2 The third doped polysilicon formed thereby is N type Alternatively, the first ion implantation of polysilicon is doped with phosphorus at a dose of 1E14 to 5E14 atoms / cm2 2 The source region is ion implanted with boron at a dose of 2E15 to 8E15 atoms / cm2 2 The third doped polysilicon thus formed is P-type.

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