A flip-flop circuit, a driving circuit and a chip

Abstract

The application provides a flip-flop circuit, a driving circuit and a chip. The flip-flop circuit comprises a clock signal generating circuit, a pulse signal generating circuit connected with the clock signal generating circuit, a flip-flop, and a clock input end of the flip-flop connected with the clock signal generating circuit. The clock signal generating circuit is used for generating a clock signal. The pulse signal generating circuit is used for generating a pulse signal according to the clock signal. The period of the pulse signal is an integer multiple of the clock signal, and there is only one driving edge of the clock signal in any high level duration of the pulse signal. The clock input end of the flip-flop is connected with the clock signal generating circuit, and the clock signal is inputted. The enable end of the flip-flop is connected with the pulse signal generating circuit, and the pulse signal is inputted. The flip-flop circuit can simplify the clock tree structure.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuits and relates to a circuit, particularly a trigger circuit, a driver circuit, and a chip. Background Technology

[0002] Field-Programmable Gate Arrays (FPGAs) are a type of self-configurable and programmable digital integrated circuits (ICs), and are a type of Application-Specific Integrated Circuit (ASIC). FPGAs are essentially between semi-custom ASICs and programmable ASICs, combining the advantages of gate array circuits and programmability. They overcome the shortcomings of traditional programmable logic devices (PLDs) (low integration and low speed) and semi-custom ASICs (low flexibility), thus meeting the requirements of modern digital systems for high capacity, high performance, and highly flexible programming.

[0003] In practical applications, due to the lack of routing resources on FPGAs, it is difficult to balance complex clock trees when implementing designs on the FPGA platform. These unbalanced clock skews can lead to intractable hold-time violations in the circuit, thus necessitating the simplification or transformation of the clock tree structure. Clock dividers are one of the common components on the clock tree. In existing technologies, clock dividers typically include registers and combinational logic, making their implementation relatively complex. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a trigger circuit, a driver circuit, and a chip to solve the problem of overly complex clock tree structures in the prior art.

[0005] To achieve the above and other related objectives, a first aspect of the present invention provides a trigger circuit, the trigger circuit comprising: a clock signal generation circuit for generating a clock signal; a pulse signal generation circuit connected to the clock signal generation circuit for generating a pulse signal based on the clock signal, wherein the period of the pulse signal is an integer multiple of the clock signal, and the clock signal has only one driving edge during any high-level duration of the pulse signal; and a trigger, wherein the clock input terminal of the trigger is connected to the clock signal generation circuit for inputting the clock signal, and the enable terminal of the trigger is connected to the pulse signal generation circuit for inputting the pulse signal.

[0006] In one embodiment of the first aspect, the pulse signal generation circuit includes: a first signal generation module connected to the clock signal generation circuit, configured to invert and divide the clock signal to obtain a first signal; a second signal generation module connected to the clock signal generation circuit, configured to divide the clock signal to obtain a divided signal, and obtain a second signal based on the divided signal and the clock signal; and a signal synthesis module connected to the first signal generation module and the second signal generation module, configured to synthesize the first signal and the second signal to obtain the pulse signal.

[0007] In one embodiment of the first aspect, the second signal generation module delays the frequency division signal according to the clock period of the clock signal to obtain the second signal.

[0008] In one embodiment of the first aspect, the second signal generation module delays the frequency division signal by half a clock cycle to obtain the second signal.

[0009] In one embodiment of the first aspect, the second signal generation module includes: a frequency division unit connected to the clock signal generation circuit, used to perform frequency division processing on the clock signal to obtain the frequency-divided signal; and a trigger unit, wherein the data input terminal of the trigger unit is connected to the frequency division unit for inputting the frequency-divided signal, and the clock input terminal of the trigger unit is connected to the clock signal generation circuit for inputting the inverted signal of the clock signal.

[0010] In one embodiment of the first aspect, the driving edge is a rising edge, and the signal synthesis module is used to perform an AND operation on the inverted signal of the second signal and the first signal to obtain the pulse signal.

[0011] In one embodiment of the first aspect, the driving edge is a rising edge, and the signal synthesis module is used to perform an AND operation on the inverted signal of the second signal and the first signal to obtain the pulse signal.

[0012] A second aspect of the present invention provides a driving circuit for generating a pulse signal according to a clock signal, wherein the period of the pulse signal is an integer multiple of the clock signal, and the clock signal has only one driving edge during any high-level duration of the pulse signal; the pulse signal is used to input the enable terminal of a flip-flop, and the clock signal is used to input the clock input terminal of the flip-flop.

[0013] In one embodiment of the second aspect, the driving circuit further includes a clock signal generation circuit for generating the clock signal.

[0014] A third aspect of the present invention provides a chip, the chip comprising a trigger circuit as described in any one of the first aspects of the present invention, or a drive circuit as described in any one of the second aspects of the present invention.

[0015] As described above, the trigger circuit, driving circuit, and chip provided in one or more embodiments of the present invention have the following beneficial effects:

[0016] The trigger circuit includes a clock signal generation circuit and a pulse signal generation circuit. The clock signal generated by the clock signal generation circuit is input to the clock input terminal of the trigger, and the pulse signal generated by the pulse signal generation circuit is input to the enable terminal of the trigger. This method enables a clock divider, thereby simplifying the clock tree structure. Furthermore, using the driving edge of the original clock signal to drive the trigger circuit helps reduce clock delay and improve hold time. Attached Figure Description

[0017] Figure 1 The diagram shown is an example of a trigger circuit in the prior art.

[0018] Figure 2A The diagram shown is a structural schematic of the trigger circuit described in a specific embodiment of the present invention.

[0019] Figure 2B The diagram shows the waveforms of the clock signal and pulse signal in a specific embodiment of the trigger circuit described in this invention.

[0020] Figure 3 The diagram shown is a schematic diagram of the pulse signal generation circuit of the trigger circuit described in this invention in a specific embodiment.

[0021] Figure 4 The diagram shown is a schematic diagram of the pulse signal generation circuit of the trigger circuit described in this invention in a specific embodiment.

[0022] Figure 5 The diagram shown is a structural schematic of the chip described in a specific embodiment of the present invention.

[0023] Component designation explanation

[0024] 1. Flip-flop circuit

[0025] 11 Clock signal generation circuit

[0026] 12 Pulse Signal Generation Circuit

[0027] 121 First Signal Generation Module

[0028] 1211 NOT gate

[0029] 1212 First frequency divider unit

[0030] 122 Second Signal Generation Module

[0031] 1221 Second frequency divider unit

[0032] 1222 trigger unit

[0033] 123 Signal Synthesis Module

[0034] 13 Triggers Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to represent selected embodiments of the invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0036] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0037] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0038] Figure 1 The diagram shown is an example of a trigger circuit in the prior art. For example... Figure 1As shown, the circuit includes a clock divider that drives rising edges to trigger flip-flops. However, existing clock dividers typically include registers and combinational logic, making them complex to implement. Furthermore, the clock signal experiences a delay after passing through the clock divider, and using the rising edge of the divided signal to trigger the flip-flop can lead to a hold-time violation. The hold-time refers to the time after the rising edge of the clock signal arrives at the flip-flop, during which the data remains stable. If the hold-time is insufficient, the data cannot enter the flip-flop.

[0039] To address at least the aforementioned problems, this invention provides a flip-flop circuit. This flip-flop circuit includes a clock signal generation circuit and a pulse signal generation circuit. The clock signal generated by the clock signal generation circuit is input to the clock input terminal of the flip-flop, and the pulse signal generated by the pulse signal generation circuit is input to the enable terminal of the flip-flop. This method enables a clock divider, thereby simplifying the clock tree structure. Furthermore, this flip-flop circuit uses the driving edge of the original clock signal to drive the flip-flop, which helps reduce clock delay and improve hold time.

[0040] The trigger circuit provided by the present invention will now be described in detail through specific embodiments and accompanying drawings.

[0041] Please see Figure 2A In one embodiment of the present invention, the trigger circuit 1 includes a clock signal generation circuit 11, a pulse signal generation circuit 12, and a trigger 13.

[0042] The clock signal generation circuit 11 is used to generate clock signals. Specifically, the clock signal is the basis of sequential logic, used to determine when the state in a logic unit is updated. It is a semaphore with a fixed period and is independent of operation. The clock signal has a fixed clock frequency, which is the reciprocal of the clock period.

[0043] The pulse signal generation circuit 12 is connected to the clock signal generation circuit 11 and is used to generate a pulse signal based on the clock signal. The period of this pulse signal is N times the period of the clock signal, where N is a positive integer greater than 1. Furthermore, within any high-level duration of the pulse signal, the clock signal has only one driving edge. If the flip-flop is triggered by a rising edge, the driving edge is a rising edge; if the flip-flop is triggered by a falling edge, the driving edge is a falling edge. Figure 2B The diagram shows an example of the waveforms of the clock signal and the pulse signal in this embodiment. As shown in the figure, within any high-level duration Th of the pulse signal, the clock signal has only one rising edge, and the period of the pulse signal is Tpulse = Th + Tl.

[0044] The clock input terminal CP of flip-flop 13 is connected to the clock signal generation circuit 11 and is used to input the clock signal. The enable terminal CE of flip-flop 13 is connected to the pulse signal generation circuit 12 and is used to input the enable signal. For flip-flop 13, if its enable terminal CE is low, flip-flop 13 will not be triggered when the clock driving edge arrives, and its output data will remain unchanged. If its enable terminal CE is high, flip-flop 13 will be triggered when the clock driving edge arrives.

[0045] As described above, the trigger circuit 1 provided in this embodiment includes a clock signal generation circuit 11 and a pulse signal generation circuit 12. The clock signal generated by the clock signal generation circuit 11 is input to the clock input terminal of the trigger circuit 13, and the pulse signal generated by the pulse signal generation circuit 12 is input to the enable terminal of the trigger circuit 13. This method achieves the purpose of a clock divider conversion, thereby simplifying the clock tree structure. Furthermore, using the driving edge of the original clock signal (i.e., the clock signal generated by the clock signal generation circuit 11) to drive the trigger circuit 13 helps reduce clock delay and improve hold time.

[0046] Please see Figure 3 In one embodiment of the present invention, the pulse signal generation circuit 12 includes a first signal generation module 121, a second signal generation module 122 and a signal synthesis module 123.

[0047] The first signal generation module 121 is connected to the clock signal generation circuit 11 and is used to invert and divide the clock signal to obtain the first signal.

[0048] Optionally, the first signal generation module 121 includes a NOT gate 1211 and a first frequency divider unit 1212. The NOT gate 1211 is connected to the output of the clock signal generation circuit 11 and is used to perform NOT processing on the clock signal to obtain the inverted clock signal. The input of the first frequency divider unit 1212 is connected to the output of the NOT gate 1211 and is used to perform frequency division processing on the inverted clock signal to obtain the first signal.

[0049] The second signal generation module 122 is connected to the clock signal generation circuit 11 and is used to perform frequency division processing on the clock signal to obtain a frequency division signal, and to obtain the second signal based on the frequency division signal.

[0050] Signal synthesis module 123 is connected to the first signal generation module 121 and the second signal generation module 122, and is used to synthesize the first signal and the second signal to obtain a pulse signal.

[0051] Optionally, the second signal generation module 122 performs delay processing on the frequency division signal according to the clock period of the clock signal to obtain the second signal.

[0052] Preferably, the second signal generation module 122 delays the frequency-divided signal by half a clock cycle to obtain the second signal. That is, the frequency-divided signal is delayed by Tck / 2 to obtain the second signal, where Tck refers to the period of the clock signal.

[0053] Optionally, please refer to Figure 4 The second signal generation module 122 may include a second frequency divider unit 1221 and a trigger unit 1222.

[0054] The second frequency divider unit 1221 is connected to the clock signal generation circuit 11 and is used to perform frequency division processing on the clock signal to obtain a divided frequency signal. Preferably, the second frequency divider unit 1221 and the first frequency divider unit 1212 have the same division ratio, that is, both divide the input signal by M, where M>0. For example, in some embodiments, M can be 2 or 3.

[0055] The data input terminal D of the flip-flop unit 1222 is connected to the output terminal of the second frequency divider unit 1221, and is used to input the frequency divider signal. The clock input terminal of the flip-flop unit 1222 is connected to the clock signal generation circuit 11, and is used to input the inverted clock signal. In some embodiments, the connection between the clock input terminal of the flip-flop unit and the clock signal generation circuit means that the two are directly connected. In other embodiments, the connection between the clock input terminal of the flip-flop unit and the clock signal generation circuit means that the two are indirectly connected through other devices, such as NOT gates.

[0056] Optionally, the driving edge of the trigger 13 is a rising edge. The signal synthesis module 123 is used to perform an AND operation on the inverted signal of the second signal and the first signal to obtain a pulse signal. For example, the signal synthesis module 123 may include an inverter and an AND gate. The second signal is processed by the inverter to obtain the inverted signal of the second signal, and the inverted signal of the second signal and the first signal are ANDed by the AND gate to obtain a pulse signal.

[0057] Optionally, the driving edge of trigger 13 is a falling edge. Signal synthesis module 123 is used to perform an AND operation on the inverted signals of the second signal and the first signal to obtain a pulse signal. For example, signal synthesis module 123 may include two inverters and an AND gate. The two inverters are used to invert the first signal and the second signal respectively to obtain inverted signals of the first signal and the second signal. The AND gate is used to perform an AND operation on the inverted signals of the first signal and the second signal to obtain a pulse signal.

[0058] Based on the above description of the flip-flop circuit 1, the present invention also provides a driving circuit. This driving circuit generates a pulse signal according to a clock signal. The period of the pulse signal is an integer multiple of the period of the clock signal, and only one driving edge of the clock signal exists within any high-level duration of the pulse signal. The pulse signal is used to input the enable terminal of the flip-flop, and the clock signal is used to input the clock input terminal of the flip-flop.

[0059] Optionally, the driving circuit further includes a clock signal generation circuit. The clock signal generation circuit is used to generate a clock signal.

[0060] Based on the above description of the trigger circuit 1 and the driving circuit, the present invention also provides a chip. Figure 5 The diagram shown illustrates the structure of the chip in this embodiment. This chip includes the trigger circuit or driver circuit provided in any of the above embodiments. The chip provided in this embodiment may include at least some components of the trigger circuit or driver circuit. Taking the trigger circuit as an example, the chip may include the entire trigger circuit, or it may only include the clock signal generation circuit and / or pulse signal generation circuit within the trigger circuit. This chip may be represented as a commercially available active device packaged from a pulse signal generation circuit manufactured on a wafer using semiconductor technology; or as a commercially available active device packaged from a pulse signal generation circuit using PCB packaging technology.

[0061] In summary, the trigger circuit provided in one or more embodiments of the present invention includes a clock signal generation circuit and a pulse signal generation circuit. The clock signal generated by the clock signal generation circuit is input to the clock input terminal of the trigger, and the pulse signal generated by the pulse signal generation circuit is input to the enable terminal of the trigger. In this way, a clock divider can be implemented, thereby simplifying the clock tree structure. Furthermore, the trigger circuit uses the driving edge of the original clock signal to drive the trigger, which helps to reduce clock delay and improve hold time. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0062] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A trigger circuit, characterized in that, The trigger circuit includes: Clock signal generation circuit, used to generate clock signals; A pulse signal generation circuit, connected to the clock signal generation circuit, is used to generate a pulse signal according to the clock signal. The period of the pulse signal is an integer multiple of the clock signal, and the clock signal has only one driving edge during any high-level duration of the pulse signal. A trigger, wherein the clock input terminal of the trigger is connected to the clock signal generation circuit for inputting the clock signal, and the enable terminal of the trigger is connected to the pulse signal generation circuit for inputting the pulse signal; The flip-flop circuit uses the driving edge of the clock signal generated by the clock signal generation circuit to drive the flip-flop. If the enable terminal of the flip-flop is low, the flip-flop will not be triggered when the clock driving edge arrives, and its output data will remain unchanged. If the enable terminal of the flip-flop is high, the flip-flop will be triggered when the clock driving edge arrives.

2. The trigger circuit according to claim 1, characterized in that, The pulse signal generation circuit includes: The first signal generation module is connected to the clock signal generation circuit and is used to invert and divide the clock signal to obtain the first signal. The second signal generation module is connected to the clock signal generation circuit and is used to perform frequency division processing on the clock signal to obtain a frequency division signal, and to obtain a second signal based on the frequency division signal and the clock signal. A signal synthesis module, connected to the first signal generation module and the second signal generation module, is used to synthesize the first signal and the second signal to obtain the pulse signal.

3. The trigger circuit according to claim 2, characterized in that, The second signal generation module performs delay processing on the frequency division signal according to the clock period of the clock signal to obtain the second signal.

4. The trigger circuit according to claim 3, characterized in that, The second signal generation module delays the frequency division signal by half a clock cycle to obtain the second signal.

5. The trigger circuit according to claim 2, characterized in that, The second signal generation module includes: The frequency division unit is connected to the clock signal generation circuit and is used to perform frequency division processing on the clock signal to obtain the frequency division signal; The trigger unit has a data input terminal connected to the frequency divider unit for inputting the frequency divider signal, and a clock input terminal connected to the clock signal generation circuit for inputting the inverted signal of the clock signal.

6. The trigger circuit according to claim 5, characterized in that: The driving edge is a rising edge, and the signal synthesis module is used to perform an AND operation on the inverted signal of the second signal and the first signal to obtain the pulse signal.

7. The trigger circuit according to claim 5, characterized in that: The driving edge is a falling edge, and the signal synthesis module is used to perform an AND operation on the inverted signal of the second signal and the inverted signal of the first signal to obtain the pulse signal.

8. A driving circuit, characterized in that, The driving circuit generates a pulse signal based on a clock signal. The period of the pulse signal is an integer multiple of the clock signal, and the clock signal has only one driving edge during any high-level duration of the pulse signal. The pulse signal is used to input the enable terminal of the flip-flop, and the clock signal is used to input the clock input terminal of the flip-flop. The driving circuit uses the driving edge of the clock signal to drive the flip-flop. If the enable terminal of the flip-flop is low, the flip-flop is not triggered when the clock driving edge arrives, and its output data remains unchanged. If the enable terminal of the flip-flop is high, the flip-flop is triggered when the clock driving edge arrives.

9. The driving circuit according to claim 8, characterized in that, The driving circuit also includes a clock signal generation circuit, which is used to generate the clock signal.

10. A chip, characterized in that, The chip includes a trigger circuit as described in any one of claims 1 to 7, or a drive circuit as described in claim 8 or 9.

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