A data conversion system

Abstract

The embodiment of the present application relates to the technical field of communication, and discloses a data conversion system. The data conversion system comprises: a first conversion unit integrated in a master chip and a second conversion unit integrated in a slave chip; the first conversion unit is used for parsing information received via an AHB bus in the master chip, obtaining read-write control information and data information, and packing and encoding the read-write control information and the data information into serial data; according to a master clock signal and a selection signal sent by the master chip via a first clock pin and a first selection pin, the serial data is sent to the slave chip indicated by the selection signal via a first transmission pin; and the second conversion unit is used for receiving serial data via a second transmission pin according to the master clock signal received via a second clock pin, converting the serial data into parallel data, unpacking the parallel data, recovering the read-write control information and the data information, and writing the data information into a storage position indicated by the read-write control information in the slave chip via an AHB bus in the slave chip.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a data conversion system. Background Technology

[0002] System-on-a-Chip (SoC) design integrates multiple components of a computer or other electronic device or system onto an integrated circuit chip. A typical SoC includes one or more microcontrollers, memory, peripherals, interfaces, timing sources, voltage regulators and power management circuitry, as well as external interfaces.

[0003] Currently, external devices access the SOC's internal bus primarily through the CPU controlling the serial interface to receive or send data via interrupts or polling. During this process, the CPU performs protocol parsing and data transfer according to relevant communication protocols. Whether acquiring data per frame or intra-frame data, the series of steps—interrupts, polling, parsing, and data transfer—results in low CPU read / write efficiency and high software overhead. Furthermore, when the data transfer rate is high, the CPU's software overhead increases further, while the CPU itself has other tasks and interrupts to handle, thus preventing immediate data reception or transmission. This leads to large communication gaps and poor real-time performance. Summary of the Invention

[0004] The purpose of this application is to provide a data conversion system that performs serial-to-parallel conversion and parallel-to-serial conversion on data through a first conversion unit and a second conversion unit. It can meet the needs of reading and writing large amounts of data with a minimum of 3 pins on the chip, thereby reducing software overhead and improving data exchange efficiency.

[0005] To address the aforementioned technical problems, embodiments of this application provide a data conversion system, comprising: a first conversion unit integrated within a master chip and a second conversion unit integrated within a slave chip; the master chip includes a first clock pin, a first transmission pin, and at least one first selection pin corresponding to the number of slave chips; the slave chip includes a second clock pin, a second transmission pin, and a second selection pin; the first conversion unit is configured to parse information received via the AHB bus within the master chip, obtain read / write control information and data information, package and encode the read / write control information and data information into serial data, and, according to a master clock signal and a selection signal transmitted via the first clock pin and the first selection pin, transmit the serial data via the first transmission pin to the slave chip indicated by the selection signal; the second conversion unit is configured to, according to the master clock signal received via the second clock pin, receive the serial data via the second transmission pin, convert the serial data into parallel data, unpack the parallel data, recover the read / write control information and data information, and write the data information via the AHB bus within the slave chip to the storage location indicated by the read / write control information in the slave chip.

[0006] This application embodiment also provides a data conversion system, including: a first conversion unit integrated in a master chip and a second conversion unit integrated in a slave chip; the master chip includes a first clock pin, a first transmission pin, and at least one first selection pin corresponding to the number of slave chips; the slave chip includes a second clock pin, a second transmission pin, and a second selection pin; the first conversion unit is used to parse information received via the AHB bus in the master chip, obtain read / write control information, package and encode the read / write control information into serial data, and send the serial data via the first transmission pin to the slave chip indicated by the selection signal according to the master clock signal and the selection signal sent by the master chip via the first clock pin and the first selection pin; the second conversion unit is used to read the data information indicated by the read / write control information received via the second transmission pin through the AHB bus in the slave chip, package and encode the data information into serial data, and send the serial data via the second transmission pin to the master chip according to the slave clock signal sent via the second clock pin.

[0007] The data conversion system provided in this application includes a first conversion unit integrated in a master chip and a second conversion unit integrated in a slave chip. The master and slave chips communicate and interact via a serial bus. The master chip includes a first clock pin, a first transmission pin, and at least one first selection pin corresponding to the number of slave chips. The slave chip includes a second clock pin, a second transmission pin, and a second selection pin. The first conversion unit sends a selection signal through the first selection pin to indicate the slave chip communicating with the master chip, sends a clock signal through the first clock pin to facilitate subsequent data transmission based on the clock signal, and parses the information received via the AHB bus, packages and encodes it into serial data, and sends it to the slave chip through the first transmission pin. Similarly, the second conversion unit receives the selection signal through the second selection pin, receives the master clock signal through the second clock pin, receives serial data through the second transmission pin, and converts the serial data into parallel data. In other words, the master chip can achieve the read and write requirements of large amounts of data between chips with a minimum of 3 pins, and the slave chip only needs 3 pins, reducing software overhead, improving data exchange efficiency, and occupying fewer chip pins. Attached Figure Description

[0008] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0009] Figure 1 This is a schematic diagram of the structure of the data conversion system provided in the embodiments of this application. Figure 1 ;

[0010] Figure 2 This is a schematic diagram of the structure of the data conversion system provided in the embodiments of this application. Figure 2 ;

[0011] Figure 3 This is a timing diagram of the signal for the first conversion unit to send serial data in the data conversion system provided in this application embodiment. Detailed Implementation

[0012] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the various embodiments of this application will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been presented in the various embodiments of this application to enable readers to better understand this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0013] Currently, external devices access the SOC's internal bus primarily through the CPU controlling the serial interface to receive or send data via interrupts or polling. During this process, the CPU performs protocol parsing and data transfer according to relevant communication protocols. Whether acquiring data per frame or intra-frame data, the series of steps—interrupts, polling, parsing, and data transfer—results in low CPU read / write efficiency and high software overhead. Furthermore, when the data transfer rate is high, the CPU's software overhead increases further, while the CPU itself has other tasks and interrupts to handle, thus preventing immediate data reception or transmission. This leads to large communication gaps and poor real-time performance.

[0014] In addition, if data is exchanged directly between chips (or between devices, or between chips and devices) through a parallel bus, such as the AHB bus, although the parallel bus has fast communication speed and good real-time performance, it is not suitable for integrated and miniaturized products because its interface occupies a lot of pins (the AHB bus interface has more than 100 pins).

[0015] Embodiments of this application relate to a data exchange system, such as... Figure 1 As shown, it specifically includes: a first conversion unit 101 integrated in the master chip and a second conversion unit 102 integrated in the slave chip; the master chip includes a first clock pin CLK1, a first transmission pin SDIO1 and at least one first selection pin CSN1 corresponding to the number of slave chips; the slave chip includes a second clock pin CLK2, a second transmission pin SDIO2 and a second selection pin CSN2.

[0016] The master chip and slave chip communicate and interact through a serial bus. For example, the master and slave chips can interact through a serial peripheral interface bus (SPI), a universal asynchronous serial data bus (UART), or an I2C bus (Inter-Integrated Circuit).

[0017] The first conversion unit 101 receives information sent by the CPU or other functional modules (such as DMA, DSP, etc.) in the main chip via the AHB bus, or the first conversion unit stores the received information in the corresponding functional module in the main chip via the AHB bus. Similarly, the second conversion unit 102 also exchanges information with the CPU or other functional modules in the slave chip via the AHB bus.

[0018] It should be noted that the data conversion system in this embodiment can be applied to a master-slave scenario or a master-multiple-slave scenario. When applied to a master-slave scenario, the master chip has 3 pins, and each slave chip also has 3 pins. When applied to a master-multiple-slave scenario, the master chip has 2 + n pins (where n is the number of slave chips), and each slave chip has 3 pins. For example... Figure 2 The diagram illustrates an application scenario where a master chip communicates with two slave chips. The master chip communicates with slave chip 1 via the first clock pin CLK1, the first transmission pin SDIO1, and the first selection pin CSN11. The master chip communicates with slave chip 2 via the same pins. When the master chip performs write operations on multiple slave chips, the first conversion unit 101 time-multiplexes the first clock pin CLK1 and the first transmission pin SDIO1. Of course, a chip can function as both a master and a slave chip; the master / slave role is not fixed.

[0019] When the master chip performs a write operation on the slave chip, the first conversion unit 101 is used to parse the information received via the AHB bus in the master chip, obtain read / write control information and data information, package and encode the read / write control information and data information into serial data, and send the serial data to the slave chip indicated by the selection signal via the first transmission pin SDIO1 according to the master clock signal and selection signal sent via the first clock pin CLK1 and the first selection pin CSN1; the second conversion unit 102 is used to receive the serial data via the second transmission pin SDIO2 according to the master clock signal received via the second clock pin CLK2, convert the serial data into parallel data, unpack the parallel data, recover the read / write control information and data information, and write the data information to the storage location indicated by the read / write control information in the slave chip via the AHB bus in the slave chip.

[0020] Specifically, the first conversion unit 101 parses the information received via the AHB bus according to the AMBA protocol to obtain read / write control information and data information. It then packages and encodes the read / write control information and data information into serial data and sends the serial data to the slave chip via the first transmission pin SDIO1. Before sending the serial data to the slave chip, the first conversion unit 101 first sends a selection signal to the slave chip via the first selection pin CSN1 to instruct the master chip, where the first conversion unit 101 resides, to perform communication operations on the slave chip. Then, the first conversion unit 101 sends a master clock signal via the first clock pin CLK1 and sends the serial data to the slave chip indicated by the selection signal according to the master clock signal.

[0021] The read / write control information includes: a 2-bit read / write identifier (hwrite), a 32-bit address (addr), and a 2-bit byte size (hsize). Specifically, a read / write identifier (hwrite) of 1 indicates a write operation, and a read operation indicates a read operation. A byte size (hsize) of 00 indicates the transfer of 1 byte of data per operation, 01 indicates the transfer of 2 bytes per operation, 10 indicates the transfer of 4 bytes per operation, and 11 indicates the transfer of 8 bytes per operation.

[0022] Additionally, when the first conversion unit 101 transmits serial data via the first transmission pin SDIO1 according to the main clock signal, it shifts the output to the falling edge of the main clock signal. The structure of the serial data includes: read / write identifier information hwrite, address information addr, byte size information hsize, and data information arranged in sequence. For example... Figure 3 The diagram shown is a timing diagram of the signals transmitted by the first conversion unit for serial data. Figure 3 As can be seen, during the write operation of the master chip to the slave chip, the selection signal CSN remains at a low level. After the write operation is completed, the first conversion unit 101 sends a high-level selection signal through the first selection pin CSN1 to indicate that a data transmission is completed.

[0023] Specifically, after receiving the selection signal and the master clock signal via the second selection pin CSN2 and the second clock pin CLK2, the second conversion unit 102 samples the received serial data across the clock domain on the rising edge of the master clock signal, converts the serial data into parallel data, unpacks the parallel data, and recovers the read / write control and data information according to the AMBA protocol. The second conversion unit 102 then writes this data information to the storage location indicated by the read / write control information in the chip via the AHB bus.

[0024] Furthermore, the first conversion unit 101 is also used to package and transmit only the current data information when it is determined from the previous read / write control information and the current read / write control information that the current address information is continuous with the previous address information and the current byte size information is consistent with the previous byte size information; the second conversion unit 102 is also used to determine the current address information from the previous address information and the previous byte size information when the current read / write control information is not obtained.

[0025] Specifically, when the first conversion unit 101 determines, based on the previous and current read / write control information, that the current address information is continuous with the previous address information and that the current byte size information is consistent with the previous byte size information, it determines that it is a continuous write operation. In this case, only the current data information is packaged, encoded into serial data, and transmitted to the slave chip, without retransmitting the read / write control information, thus saving the transmission time of the read / write control information and improving data exchange efficiency. When the second conversion unit 102 does not receive the current read / write control information, it predicts the address information of the current write operation based on the address information and byte size information corresponding to the previous write operation, thereby realizing address prediction for continuous write operations.

[0026] For example, if the address information of the previous write operation was 0x3000_0000 and the byte size was 1 byte, and the write operation continues this time, the address information will be 0x3000_0001, and the byte size will still be 1 byte. If the second conversion unit 102 does not receive read / write control information, it predicts that the address information for this operation will be 0x3000_0001 based on the previous address information and byte size. That is, even without receiving read / write control information, the second conversion unit 102 can continue the write operation based on the address prediction function.

[0027] The data conversion system provided in this embodiment occupies 3 pins of the chip, enabling efficient read and write operations between chips without additional software overhead. It also allows for multi-chip cascading, with the main chip managing the system and providing a unified external interface. This transforms the passive chip-based approach into a solution for scenarios that a single chip cannot handle, significantly reducing costs and improving versatility through multi-chip cascading.

[0028] Embodiments of this application also relate to a data exchange system, specifically including: a first conversion unit 101 integrated in a master chip and a second conversion unit 102 integrated in a slave chip; the master chip includes a first clock pin CLK1, a first transmission pin SDIO1 and at least one first selection pin CSN1 corresponding to the number of slave chips; the slave chip includes a second clock pin CLK2, a second transmission pin SDIO2 and a second selection pin CSN2.

[0029] The data conversion system of this embodiment can be applied to a master-slave scenario or a master-multiple-slave scenario. When applied to a master-slave scenario, the master chip has 3 pins, and the slave chip also has 3 pins. When applied to a master-multiple-slave scenario, the master chip has 2+n pins (n ​​is the number of slave chips), and each slave chip has 3 pins. When the master chip performs read operations on multiple slave chips, the first conversion unit 101 time-division multiplexes the first clock pin CLK1 and the first transmission pin SDIO1. Of course, a chip can act as both a master and a slave chip; the master / slave role of a chip is not fixed.

[0030] When the master chip performs a read operation on the slave chip, the first conversion unit 101 is used to parse the information received via the AHB bus in the master chip, obtain read / write control information, package and encode the read / write control information into serial data, and send the serial data to the slave chip indicated by the selection signal via the first transmission pin SDIO1 according to the master clock signal and selection signal sent by the master chip via the first clock pin CLK1 and the first selection pin CSN1; the second conversion unit 102 is used to read the data information indicated by the read / write control information through the AHB bus in the slave chip according to the read / write control information received via the second transmission pin SDIO2, package and encode the data information into serial data, and send the serial data to the master chip via the second transmission pin according to the slave clock signal sent via the second clock pin CLK2.

[0031] The first conversion unit is also used to receive serial data sent by the slave chip via the first transmission pin SDIO1 based on the slave clock signal received via the first clock pin CLK1, convert the serial data into parallel data, depacketize the parallel data to recover the data information, and store the data information in the main chip via the AHB bus in the main chip.

[0032] The read / write control information includes: a 2-bit read / write identifier (hwrite), a 32-bit address (addr), and a 2-bit byte size (hsize). Specifically, a read / write identifier (hwrite) of 1 indicates a write operation, and a read operation indicates a read operation. A byte size (hsize) of 00 indicates the transfer of 1 byte of data per operation, 01 indicates the transfer of 2 bytes per operation, 10 indicates the transfer of 4 bytes per operation, and 11 indicates the transfer of 8 bytes per operation.

[0033] When the master chip performs a read operation on the slave chip, the first conversion unit 101 only packages and encodes the read / write control information into serial data (the structure of the serial data includes: read / write identification information, address information, and byte size information arranged in sequence) and sends it to the slave chip. After receiving the read / write control information via the second transmission pin SDIO2, the second conversion unit 102 reads the data information indicated by the read / write control information through the AHB bus, packages and encodes the data information into serial data, and sends it to the master chip. According to the slave clock signal, the first conversion unit 101 samples and receives the serial data sent by the slave chip across the clock domain on the rising edge of the slave clock signal, converts the serial data into parallel data, unpacks the parallel data, recovers the data information, and stores the data information in the master chip via the AHB bus.

[0034] Furthermore, the first conversion unit 101 is also used to determine, based on the previous read / write control information and the current read / write control information, that the current address information is continuous with the previous address information and that the current byte size information is consistent with the previous byte size information, without packaging and transmitting the current read / write control information; the second conversion unit 102 is used to determine the current address information based on the previous address information and the previous byte size information when the current read / write control information is not obtained.

[0035] Specifically, when the first conversion unit 101 determines that the current address information is continuous with the previous address information and that the current byte size information is consistent with the previous byte size information, i.e., the master chip performs a continuous read operation on the slave chip, the first conversion unit 101 does not need to transmit the current read / write control information. The second conversion unit 102, without obtaining the current read / write control information, directly determines the current address information based on the previous address information and byte size information. That is, the second conversion unit predicts the address information of the current read operation based on the address information and byte size information corresponding to the previous read operation, thus achieving address prediction for continuous read operations.

[0036] For example, if the address information of the previous read operation was 0x2000_0000 and the byte size was 4 bytes, and the read operation continues this time, the address information will be 0x2000_0004, and the byte size will still be 4 bytes. If the second conversion unit 102 does not receive read / write control information, it predicts that the address information for this operation will be 0x2000_0004 based on the previous address information and byte size. That is, even without receiving read / write control information, the second conversion unit 102 can continue the read operation based on the address prediction function.

[0037] Furthermore, the second conversion unit 102 is also used to, when receiving address information but not receiving byte size information, pre-read data information of a preset byte size according to the address information via the AHB bus in the chip; after receiving byte size information, obtain the data information indicated by the byte size information from the pre-read data information, and package and encode the data information indicated by the byte size information into serial data.

[0038] Specifically, when the first conversion unit 101 has completed transmitting the address information but not yet the byte size information, the second conversion unit 102 already knows the read address. Since reading does not destroy data, the second conversion unit immediately reads back the preset byte size data from the slave chip's memory via the AHB bus. Assuming the preset byte size is 4 bytes, the second conversion unit pre-reads 4 bytes of data according to the read address. Upon receiving the byte size information hsize, assuming hsize indicates the need to read 2 bytes of data, the second conversion unit 102 obtains 2 bytes of data from the pre-read 4 bytes and packages and encodes these 2 bytes of data into serial data, which is then sent to the master chip. This data prefetching function of the second conversion unit 102 significantly improves data reading efficiency, reduces communication gaps, and enables real-time data reading.

[0039] The data conversion system provided in this embodiment occupies three pins of the chip, enabling efficient read and write operations between chips without additional software overhead. It also allows for multi-chip cascading, with the main chip managing the system and providing a unified external interface. This transforms the passive chip-based approach into a solution for scenarios that a single chip cannot handle, significantly reducing costs and improving versatility through multi-chip cascading.

[0040] Those skilled in the art will understand that the above embodiments are specific embodiments for implementing this application, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of this application.

Claims

1. A data conversion system, characterized in that, include: A first conversion unit integrated within a master chip and a second conversion unit integrated within a slave chip; the master chip includes a first clock pin, a first transmission pin, and at least one first selection pin corresponding to the number of slave chips; the slave chip includes a second clock pin, a second transmission pin, and a second selection pin; The first conversion unit is used to parse the information received via the AHB bus in the main chip, obtain read / write control information and data information, package and encode the read / write control information and data information into serial data, and send the serial data to the slave chip indicated by the selection signal via the first transmission pin according to the main clock signal sent via the first clock pin and the selection signal sent via the first selection pin. The second conversion unit is configured to receive the serial data via the second transmission pin across the clock domain at the rising edge of the main clock signal, based on the main clock signal received via the second clock pin and the selection signal received via the second selection pin, convert the serial data into parallel data, unpack the parallel data, recover the read / write control information and data information according to the AMBA protocol, and write the data information to the storage location indicated by the read / write control information in the chip via the AHB bus in the chip.

2. The data conversion system according to claim 1, characterized in that, The read / write control information includes: read / write identification information, address information, and byte size information; the structure of the serial data includes: the read / write identification information, the address information, the byte size information, and the data information arranged in sequence.

3. The data conversion system according to claim 2, characterized in that, The first conversion unit is further configured to, when it is determined from the previous read / write control information and the current read / write control information that the current address information is continuous with the previous address information and the current byte size information is consistent with the previous byte size information, only pack and encode the current data information into serial data. The second conversion unit is also used to determine the current address information based on the previous address information and the previous byte size information when the current read / write control information is not obtained.

4. The data conversion system according to any one of claims 1-3, characterized in that, When the master chip performs write operations on multiple slave chips, the first conversion unit time-multiplexes the first clock pin and the first transmission pin.

5. A data conversion system, characterized in that, include: A first conversion unit integrated within a master chip and a second conversion unit integrated within a slave chip; the master chip includes a first clock pin, a first transmission pin, and at least one first selection pin corresponding to the number of slave chips; the slave chip includes a second clock pin, a second transmission pin, and a second selection pin; The first conversion unit is used to parse the information received via the AHB bus in the main chip, obtain read and write control information, package and encode the read and write control information into serial data, and send the serial data to the slave chip indicated by the selection signal via the first transmission pin according to the main clock signal sent via the first clock pin and the selection signal sent via the first selection pin. The second conversion unit is used to read the data information indicated by the read / write control information received via the second transmission pin from the AHB bus in the chip, package and encode the data information into serial data, and send the serial data to the main chip via the second transmission pin according to the slave clock signal sent via the second clock pin. The first conversion unit is further configured to receive serial data sent by the slave chip via the first transmission pin based on the slave clock signal received via the first clock pin, convert the serial data into parallel data, depacketize the parallel data to recover data information, and store the data information in the main chip via the AHB bus in the main chip.

6. The data conversion system according to claim 5, characterized in that, The read / write control information includes: read / write identification information, address information, and byte size information.

7. The data conversion system according to claim 5, characterized in that, The first conversion unit is further configured to not package and transmit the current read and write control information when it is determined, based on the previous read and write control information and the current read and write control information, that the current address information is continuous with the previous address information and the current byte size information is consistent with the previous byte size information. The second conversion unit is used to determine the current address information based on the previous address information and the previous byte size information when the current read / write control information is not obtained.

8. The data conversion system according to claim 5, characterized in that, The second conversion unit is further configured to, when receiving address information but not receiving byte size information, pre-read data information of a preset byte size according to the address information via the AHB bus in the slave chip; after receiving the byte size information, obtain the data information indicated by the byte size information from the pre-read data information, and package and encode the data information indicated by the byte size information into serial data.

9. The data conversion system according to claim 5, characterized in that, When the master chip performs read operations on multiple slave chips, the first conversion unit time-multiplexes the first clock pin and the first transmission pin.

Images