An Accelerated Method and Device for Polynomial Multiplication

Abstract

The present invention provides a polynomial multiplication acceleration method and device. The device comprises m pre-processing external blocks, an input sorting module, k pre-processing internal blocks, a central multiplier array, k post-processing internal blocks, an output integration module, and m post-processing external blocks. The method and device of the present invention further simplify high-bitwidth polynomial multipliers, further reducing the multiplication complexity of N-term polynomial multiplication operations. The hardware area ratio compared to traditional polynomial multiplication algorithms can be less than 0.001%.

Description

Technical Field

[0001] The present invention relates to a polynomial multiplication acceleration method and device. Background Art

[0002] In fields such as digital signal processing, cryptography, and coding theory, the problem of how to quickly multiply two polynomials is often encountered. The number of cycles, total latency, and resource consumption are all important factors that determine the overall area-efficiency ratio of the hardware architecture in this application scenario. Therefore, people have proposed many feasible optimization methods for it.

[0003] Since the Karatsuba algorithm was proposed in 1962 (Reference: Karatsuba, Anatolii & Ofman, Yu. (1962). Multiplication of Multidigit Numbers on Automata. Soviet Physics Doklady. 7.595), after decades of development, it is considered to be one of the best ways to reduce the computational complexity of polynomial multiplication. It can reduce the multiplication complexity of N-term polynomial multiplication from down to The addition complexity is no greater than However, in practical applications, polynomial multiplication operations with large bit widths of polynomial coefficients sometimes arise. For example, in elliptic curve research, this problem may be encountered in modular multiplication operations within Galois fields. Typically, a traditional multiplier is used as the central multiplier, or the multiplier IP built into the FPGA is used as the central multiplier. However, when the bit width of the polynomial coefficients reaches tens or hundreds of bits, it may exceed the functional range of the multiplier IP. Using a traditional multiplier design will lead to problems such as excessive computational complexity and excessive hardware area. Therefore, the polynomial multiplier in this case will have a negative impact on the performance of the overall hardware implementation.

[0004] There are many implementations of polynomial multiplication and integer multiplication based on the Karatsuba algorithm. For two binomial polynomials A(x) = a0 + a1x and B(x) = b0 + b1x, the classic multiplication algorithm is:

[0005] C(x)=a0b0+(a0b1+a0b1)x+a1b1x 2

[0006] This algorithm requires four multiplications and one addition. The binomial polynomial multiplication algorithm KA2 based on the Karatsuba algorithm is:

[0007] C(x)=a0b0+((a0+a1)(b0+b1)-a0b0-a1b1)x+a1b1x 2

[0008] This algorithm requires three multiplications and four additions. Under the premise that the delay and resource consumption of multiplication are much higher than those of addition, this algorithm reduces the complexity of binomial multiplication to a certain extent. Based on Karatsuba binomial multiplication, the number of recursive terms can be obtained as 2 n The Karatsuba algorithm can be used to calculate the n The specific algorithm is shown in Algorithm 1, where Algorithm 1: Recursive Karatsuba2 n Polynomial multiplication algorithm

[0009] All are unsigned integers (including 0).

[0010]

[0011] After calculation, the multiplication complexity of the algorithm is 4 times that of the traditional algorithm. n Reduced to 3 n , the addition complexity is no more than 2·3 n +1 -2 n+3 +2. In addition to 2 n In addition to the Karatsuba polynomial multiplication of 1 term, there are also Karatsuba algorithms for 3, 5, and 7 terms. Then, using a method similar to the above recursive algorithm, we can also form the Karatsuba polynomial multiplication of any integer term. In the reference "Weimerskirch, André and Christof Paar. "Generalizations of the Karatsuba Algorithm for Efficient Implementations." IACR Cryptol. ePrint Arch. 2006 (2006): 224", it is proved that for any positive integer N, the ratio of the hardware area of Karatsuba polynomial multiplication to traditional polynomial multiplication will not be less than Summary of the Invention

[0012] Purpose of the invention: The technical problem to be solved by the present invention is to address the deficiencies of the prior art and provide a method and device for accelerating polynomial multiplication, specifically a method and device for accelerating polynomial multiplication based on the Karatsuba architecture, wherein the method comprises:

[0013] Input two sets of polynomial coefficients, the number of terms in each set of polynomial coefficients is where p1, p2, ..., p m are the 1st, 2nd, ..., mth repeatable prime factors of the number respectively;

[0014] The two sets of polynomial coefficients are divided into The Karatsuba algorithm performs operations on all operation rules before the data stream reaches the multiplication operation, and obtains two sets of external pre-processed data;

[0015] The two sets of external pre-processed data are respectively sorted and re-ordered to obtain sorted data;

[0016] The sorted data is sorted by the number of items The Karatsuba algorithm performs operations on all the operation rules before the data stream reaches the multiplication operation, and obtains two sets of internal pre-processed data, where p -1 、p -2 、……、p -k These are the 1st, 2nd, ..., kth prime factors specified according to usage requirements. Usage requirements refer to the area (resource) of the multiplier that the user can accept. For example, to calculate 4 64-bit polynomial multiplications, a traditional multiplier requires 256 DSPs, while a traditional Karatsuba multiplier uses 144 DSPs. If p-1=2 is set in this method, 108 DSPs are used. If p-1=p-2=2 is set, 81 DSPs are used.

[0017] Perform multiplication operation on the corresponding data in the two sets of internal preprocessed data to obtain a set of preliminary product data;

[0018] The preliminary product data is divided into The Karatsuba algorithm performs operations on all operation rules after the multiplication operation in the data stream to obtain internal post-processed data;

[0019] Rearrange, shift and add the internal post-processed data to obtain integrated data;

[0020] The integrated data is divided into The Karatsuba algorithm performs all the operation rules after the multiplication operation in the data stream to obtain the final output data, that is, the number of items is The product polynomial coefficients of .

[0021] The present invention also provides an acceleration device for polynomial multiplication, comprising m pre-processing external blocks, an input sorting module, k pre-processing internal blocks, a group of central multiplier arrays, k post-processing internal blocks, an output integration module, and m post-processing external blocks, where m and k are positive integers.

[0022] The m pre-processing external blocks are used to input two sets of polynomial coefficients, and the number of terms in each set of polynomial coefficients is where p1, p2, ..., p m are the 1st, 2nd, ..., mth repeatable prime factors of the term respectively; then the two sets of polynomial coefficients are The Karatsuba algorithm performs operations on all operation rules before the data stream reaches the multiplication operation, and obtains two sets of external pre-processed data;

[0023] The input sorting module is used to sort and reorder the two sets of external pre-processed data to obtain sorted data;

[0024] The k pre-processing internal blocks are used to sort the sorted data into The Karatsuba algorithm performs operations on all the operation rules before the data stream reaches the multiplication operation, and obtains two sets of internal pre-processed data, where p -1 、p -2 、……、p -k are the 1st, 2nd, ..., kth prime factors specified according to usage requirements;

[0025] The set of central multiplier arrays is used to perform multiplication operations on corresponding data in the two sets of internal pre-processed data to obtain a set of preliminary product data;

[0026] The k post-processing internal blocks are used to process the preliminary product data according to the number of items. The Karatsuba algorithm performs operations on all operation rules after the multiplication operation in the data stream to obtain internal post-processed data;

[0027] The output integration module is used to reorder, shift and add the internal post-processed data to obtain integrated data;

[0028] The m post-processing external blocks are used to process the integrated data in terms of the number of items. The Karatsuba algorithm performs all the operation rules after the multiplication operation in the data stream to obtain the final output data, that is, the number of items is The product polynomial coefficients of .

[0029] The m preprocessing external blocks are KA_pre module;

[0030] The k preprocessing internal blocks are KA_pre module;

[0031] The k post-processing internal blocks are KA_post module;

[0032] The m post-processing external blocks are KA_post module;

[0033] in Respectively represent the number of items p1, p2, ..., p m Karatsuba algorithm module; References "Weimerskirch, Andréand Christof Paar. "Generalizations of the Karatsuba Algorithm for Efficient Implementations." IACR Cryptol. ePrintArch. 2006 (2006): 224" and "Montgomery, Peter L.. "Five, six, and seven-term Karatsuba-like formulae." IEEE Transactions on Computers 54 (2005): 362-369";

[0034] in Respectively represent the 1st, 2nd, ..., kth prime factors p specified according to usage requirements -1 、p -2 、……、p -k The corresponding number of terms is p -1 、p -2 、……、p -kKaratsuba algorithm module; reference "Weimerskirch, Andréand Christof Paar. "Generalizations of the KaratsubaAlgorithm for Efficient Implementations." IACR Cryptol.ePrint Arch. 2006 (2006): 224" and "Montgomery, Peter L.. "Five, six, and seven-term Karatsuba-like formulae." IEEE Transactions on Computers 54 (2005): 362-369";

[0035] The KA_pre module represents the hardware device that performs all operations that the data flow in the Karatsuba algorithm undergoes from the input to all multiplication operations.

[0036] The KA_post module represents the hardware device that performs all operations that the data flow undergoes after all multiplication operations to the output end in the Karatsuba algorithm.

[0037] The central multiplier array includes a plurality of integer multipliers, wherein the number of multipliers is determined by and The structure of and The corresponding number of central multipliers are l1, l2, ..., l m and l -1 ,l -2 ,...,l -k When , the number of central multipliers is indivual.

[0038] The input sorting module is used to execute the following input sorting algorithm:

[0039]

[0040]

[0041] where a_i0,a_i1,..., Indicates the first group number of input sorting modules is The 1st, 2nd, ..., Input binary integer data, b_i0,b_i1,..., Indicates the number of two groups of input sorting modules is The first, second, ..., Input binary integer data;

[0042] a_o 00 ,a_o 01 ,..., Indicates the first group of the first group of output data of the input sorting module, the first, second, ..., Binary integer data, a_o 10 ,a_o 11 ,..., Indicates the first group of output data of the input sorting module, the first, second, ..., binary integer data, ..., Indicates the first set of output data of the input sorting module. The first, second, ..., binary integer data;

[0043] b_o 00 ,b_o 01 ,..., Indicates the first, second, ..., Binary integer data, b_o 10 ,b_o 11 ,..., Indicates the first, second, ..., binary integer data, ..., Indicates the first output data of the second group of input sorting modules The first, second, ..., Binary integer data.

[0044] The output integration module is used to execute the following output integration algorithm:

[0045]

[0046] where c_i 00 ,c_i 01 ,…, Indicates the first set of input data of the output integration module, 1, 2, ..., Binary integer data, c_i 10 ,c_i 11 ,…, Indicates the 1st, 2nd, ..., binary integer data, ..., Indicates the output integration module The 1st, 2nd, ..., binary integer data;

[0047] where c_o0, c_o1, ..., Indicates the 1st, 2nd, ..., Binary positive integer data.

[0048] The input sorting module includes a sorting module and an input reordering module;

[0049] The sorting module will two groups Each of the binary integer data is from low to high 0th to t-1th, tth to 2t-1th, ..., To The bits are taken out and formed into a new integer, where t is an integer set according to the usage requirements, and the initial data is obtained from each new integers into a group, forming A new array;

[0050] The input reordering module will In the new array All the 1st, 2nd, ..., The data are taken out and spliced into new 1, 2, ..., The number of data is Array of After the new array All the 1st, 2nd, ..., data are taken out and new The number of data is Array of .

[0051] The output integration module includes an output reordering module, a shift module array, and an addition array;

[0052] The output reordering module will The number of data is The 1st, 2nd, ..., The data are taken out and spliced into new 1, 2, ..., The number of data is Array of;

[0053] The shift module array shifts the 1st, 2nd, ..., The data are filled with zeros in the high position, and then the shift register is used to shift left by 0, t, ..., Get new data;

[0054] The addition array will shift all the The data are added together using an adder to get a sum, and the total number of all arrays is Such sums are obtained and the obtained sums are output as output data of the addition array.

[0055] By adding a set of input sorting modules and output integration modules to the Karatsuba polynomial multiplication architecture, the present invention allows for bidirectional extension of the Karatsuba polynomial multiplication architecture, both inward and outward. Consequently, a low-complexity, low-resource, high-bitwidth polynomial multiplication method and apparatus based on the Karatsuba architecture is proposed. The components outside the input sorting and output integration modules include the Karatsuba pre-processing external block and the Karatsuba post-processing external block, which implement the desired polynomial multiplication functions. The components between the input sorting and output integration modules include the Karatsuba pre-processing internal block, the central multiplier array, and the Karatsuba post-processing internal block, extending the existing Karatsuba architecture internally and further optimizing its functionality.

[0056] Furthermore, the present invention also provides a key exchange acceleration method, in which the polynomial multiplication operations in the CSIDH key exchange process are all implemented by the aforementioned polynomial multiplication acceleration method, wherein the number of multipliers is N, and N is the number of terms of the polynomials involved in the CSIDH key exchange process.

[0057] Correspondingly, the present invention also provides a key exchange acceleration device, including the polynomial multiplication acceleration device as described above.

[0058] Beneficial effect: The method and device of the present invention further simplify the high-bitwidth polynomial multiplier, further reducing the multiplication complexity of N-term polynomial multiplication operations, and the ratio of hardware area to traditional polynomial multiplication algorithm can be less than BRIEF DESCRIPTION OF THE DRAWINGS

[0059] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, and the above and / or other advantages of the present invention will become more apparent.

[0060] Figure 1 This is a diagram of the Karatsuba polynomial multiplication hardware architecture.

[0061] Figure 2Schematic diagram of the low-complexity, low-resource, high-bitwidth polynomial Karatsuba multiplication architecture of the present invention.

[0062] Figure 3 This is the circuit diagram of the input sorting module.

[0063] Figure 4 This is a circuit diagram of the output integration module. DETAILED DESCRIPTION

[0064] The present invention provides a polynomial multiplication acceleration method and device, specifically a polynomial multiplication acceleration method and device based on the Karatsuba architecture, wherein the method comprises:

[0065] Input two sets of polynomial coefficients, the number of terms in each set of polynomial coefficients is where p1, p2, ..., p m are the 1st, 2nd, ..., mth repeatable prime factors of the number respectively;

[0066] The two sets of polynomial coefficients are divided into The Karatsuba algorithm performs operations on all operation rules before the data stream reaches the multiplication operation, and obtains two sets of external pre-processed data;

[0067] The two sets of external pre-processed data are respectively sorted and re-ordered to obtain sorted data;

[0068] The sorted data is sorted by the number of items The Karatsuba algorithm performs operations on all the operation rules before the data stream reaches the multiplication operation, and obtains two sets of internal pre-processed data, where p -1 、p -2 、……、p -k are the 1st, 2nd, ..., kth prime factors specified according to usage requirements;

[0069] Perform multiplication operation on the corresponding data in the two sets of internal preprocessed data to obtain a set of preliminary product data;

[0070] The preliminary product data is divided into The Karatsuba algorithm performs operations on all operation rules after the multiplication operation in the data stream to obtain internal post-processed data;

[0071] Rearrange, shift and add the internal post-processed data to obtain integrated data;

[0072] The integrated data is divided into The Karatsuba algorithm performs all the operation rules after the multiplication operation in the data stream to obtain the final output data, that is, the number of items is The product polynomial coefficients of .

[0073] The present invention also provides an acceleration device for polynomial multiplication, comprising m pre-processing external blocks, an input sorting module, k pre-processing internal blocks, a group of central multiplier arrays, k post-processing internal blocks, an output integration module, and m post-processing external blocks, where m and k are positive integers.

[0074] The m pre-processing external blocks are used to input two sets of polynomial coefficients, and the number of terms in each set of polynomial coefficients is where p1, p2, ..., p m are the 1st, 2nd, ..., mth repeatable prime factors of the term respectively; then the two sets of polynomial coefficients are The Karatsuba algorithm performs operations on all operation rules before the data stream reaches the multiplication operation, and obtains two sets of external pre-processed data;

[0075] The input sorting module is used to sort and reorder the two sets of external pre-processed data to obtain sorted data;

[0076] The k pre-processing internal blocks are used to sort the sorted data into The Karatsuba algorithm performs operations on all the operation rules before the data stream reaches the multiplication operation, and obtains two sets of internal pre-processed data, where p -1 、p -2 、……、p -k are the 1st, 2nd, ..., kth prime factors specified according to usage requirements;

[0077] The set of central multiplier arrays is used to perform multiplication operations on corresponding data in the two sets of internal pre-processed data to obtain a set of preliminary product data;

[0078] The k post-processing internal blocks are used to process the preliminary product data according to the number of items. The Karatsuba algorithm performs operations on all operation rules after the multiplication operation in the data stream to obtain internal post-processed data;

[0079] The output integration module is used to reorder, shift and add the internal post-processed data to obtain integrated data;

[0080] The m post-processing external blocks are used to process the integrated data in terms of the number of items. The Karatsuba algorithm performs all the operation rules after the multiplication operation in the data stream to obtain the final output data, that is, the number of items is The product polynomial coefficients of .

[0081] The present invention is based on a The Karatsuba architecture is designed based on the terms of the Karatsuba outer architecture, where m is the order of the Karatsuba outer architecture, that is, the number of terms in the overall architecture input polynomial, k is the order of the Karatsuba inner architecture, and p i The minus sign in the subscript is used to distinguish it from other subscripts and also to indicate that the corresponding KA_pre and KA_post functions are used in the Karatsuba framework. A set of input sorting modules and output integration modules are added to the Karatsuba polynomial multiplication architecture, so that the architecture can be extended in both directions, forming a Figure 2 The improved Karatsuba polynomial multiplication architecture with low complexity, low resources and high bit width is shown.

[0082] It can be seen that Figure 2 The overall architecture and Figure 1 Similar, but with some slight differences in details. Figure 2 The two red dotted lines in the figure represent the input sorting module and output integration module designed by the present invention. The blue modules outside the two red lines represent the external blocks in this architecture. The KA_pre module and KA_post module; the yellow modules within the two red lines represent the internal blocks in this architecture, from the red line inwards are The polynomial multiplication operation implemented in the outer architecture is the function implemented by the overall architecture. The inner architecture is a vertical extension of the original Karatsuba architecture, which is a deeper optimization based on the outer architecture. In the middle is a row of central multiplier arrays, the number of which is determined by and The structure of is determined by, if the number of their corresponding central multipliers is l1,l2,...,l m and l -1 ,l -2 ,...,l -k ,So Figure 2 The number of central multipliers in is The subscripts of KA, KA_pre, and KA_post indicate the number of terms in the Karatsuba polynomial multiplication architecture of this layer.

[0083] The input sorting algorithm and output integration algorithm are shown in Algorithm 2 and Algorithm 3, and the circuit diagram of the input sorting module and the circuit diagram of the output integration module are shown in Figure 3 、 Figure 4 As shown. There is a new parameter t in Algorithm 2 and Algorithm 3, which satisfies And try to minimize it.

[0084] Algorithm 2: Input sorting algorithm:

[0085]

[0086]

[0087] Algorithm 3: Output integration algorithm:

[0088] Represents an integer In the binary representation, the slice from jt-1 to (j-1)t bits has only one number in the subscript of a_i and b_i, and two numbers in the subscript of a_o and b_o, which are only used to distinguish them.

[0089]

[0090]

[0091] The coefficient c_o has a single subscript, while c_i has two subscripts, both for differentiation. The numbers a_i and b_i have a single subscript, while a_o and b_o have two subscripts, both for differentiation.

[0092] Algorithm 2 and Figure 3 The input sorting module shown includes a set of functional blocks that perform bit-wise interception on the input data, and a set of circuits that rearrange the order of the output data. Figure 4 The output integration module shown includes a set of circuits that rearrange the order of input data, some shift module arrays and a set of addition arrays ( Figure 4 The input sorting module and the output integration module have two functions in the circuit: one is to convert the length of the coefficient vector. The length of the input and output vectors of the central multiplier of the Karatsuba architecture becomes The first is to count the length of the data vector transmitted from the outside to the inside between the m-th layer of pre-processing or post-processing and the m+1-th layer of pre-processing or post-processing in the Karatsuba architecture; the second is to reduce the bit width of each value in the transmission process and increase the number of items to facilitate the bidirectional extension of the Karatsuba architecture and further optimize the architecture.

[0093] Take a 4-term (N=4, then according to Take m = 2, p1 = p2 = ... = p m =2) polynomial multiplication unit as an example, the polynomial coefficient bit width is set to 64. Then the multiplier unit using traditional polynomial multiplication, the multiplier unit using traditional Karatsuba polynomial multiplication, and the low-complexity, low-resource, high-bitwidth polynomial multiplication unit based on Karatsuba architecture designed in this solution (k is 2, t is 16, p is 16) are used. -1 =p -2 =...=p -k =2) The resource and area comparison of the three in FPGA is shown in Table 1.

[0094] Table 1

[0095]

[0096] The EDA (Electronic Design Automation) platform used for simulation, synthesis, and implementation in this embodiment is Vivado 2021.1, and the FPGA model used is Xilinx Virtex-7xc7vx690tffg1157-3. In the above data, #Slices and #DSP are directly obtained after synthesis and implementation, and #SEC is the calculated data that represents the hardware resource consumption or area. The calculation formula is:

[0097] #SEC=#BRAMs×100+#DSPs×100+#Slices

[0098] Since BRAM is not used in any of the three multipliers, #BRAMs defaults to 0. Theoretically, the minimum limit of the ratio of the hardware area of Karatsuba polynomial multiplication to the traditional polynomial multiplication algorithm is In the above example, the limit is As can be seen from Table 1, the traditional Karatsuba method is slightly larger than this limit value, while the proposed scheme is smaller than this limit value.

[0099] This embodiment also provides a CSIDH key exchange acceleration method, which includes: all polynomial multiplication operations in the CSIDH key exchange process are implemented by a polynomial multiplication acceleration method described in the present invention.

[0100] Furthermore, the number of multipliers is N, where N is the number of terms of the polynomial involved in the CSIDH key exchange process. In a 64-bit integer computing environment, N is 8 in the CSIDH key exchange process using the CSIDH512 parameter set, N is 16 in the CSIDH key exchange process using the CSIDH1024 parameter set, and N is 32 in the CSIDH key exchange process using the CSIDH2048 parameter set.

[0101] The CSIDH key exchange process involves multiple polynomial multiplication operations. The polynomials involved in each polynomial multiplication operation are the same. The number of multipliers N is the number of terms in different polynomials corresponding to the CSIDH key exchange process with different parameters.

[0102] Correspondingly, an embodiment of the present invention further provides a CSIDH encryption and decryption acceleration device, including the polynomial multiplication acceleration device described in the present invention.

[0103] The CSIDH key exchange acceleration method and device provided in this embodiment can improve the efficiency of the CSIDH key exchange process while reducing the resource consumption of the FPGA hardware implementation of CSIDH.

[0104] In a specific implementation, the present application provides a computer storage medium and a corresponding data processing unit, wherein the computer storage medium is capable of storing a computer program that, when executed by the data processing unit, can execute the invention content of the polynomial multiplication acceleration method provided by the present invention and some or all of the steps in each embodiment. The storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

[0105] Those skilled in the art can clearly understand that the technical solutions in the embodiments of the present invention can be implemented by means of computer programs and their corresponding general hardware platforms. Based on this understanding, the technical solutions in the embodiments of the present invention, in essence or in other words, the part that contributes to the prior art, can be embodied in the form of a computer program, i.e., a software product. The computer program software product can be stored in a storage medium and includes several instructions for enabling a device including a data processing unit (which can be a personal computer, a server, a single-chip microcomputer, a MUU, or a network device, etc.) to execute the methods described in various embodiments of the present invention or certain parts of the embodiments.

[0106] The present invention provides a method and apparatus for accelerating polynomial multiplication. There are numerous methods and approaches for implementing this technical solution. The foregoing merely represents a preferred embodiment of the present invention. It should be noted that those skilled in the art may make various improvements and modifications without departing from the principles of the present invention, and such improvements and modifications are also within the scope of protection of the present invention. Any components not specified in this embodiment may be implemented using existing technologies.

Claims

1. A method for accelerating polynomial multiplication, characterized in that: include: Input two sets of polynomial coefficients, the number of terms in each set of polynomial coefficients is where p1, p2, ..., p m are the 1st, 2nd, ..., mth repeatable prime factors of the number respectively; The two sets of polynomial coefficients are divided into The Karatsuba algorithm performs operations on all operation rules before the data stream reaches the multiplication operation, and obtains two sets of external pre-processed data; The two sets of external pre-processed data are respectively sorted and re-ordered to obtain sorted data; The sorted data is sorted by the number of items The Karatsuba algorithm performs operations on all the operation rules before the data stream reaches the multiplication operation, and obtains two sets of internal pre-processed data, where p -1 、p -2 、……、p -k are the 1st, 2nd, ..., kth prime factors specified according to usage requirements; Perform multiplication operation on the corresponding data in the two sets of internal preprocessed data to obtain a set of preliminary product data; The preliminary product data is divided into The Karatsuba algorithm performs operations on all operation rules after the multiplication operation in the data stream to obtain internal post-processed data; Rearrange, shift and add the internal post-processed data to obtain integrated data; The integrated data is divided into The Karatsuba algorithm performs all the operation rules after the multiplication operation in the data stream to obtain the final output data, that is, the number of items is The product polynomial coefficients of ; The acceleration method of polynomial multiplication is used in the key exchange acceleration method, specifically including: the polynomial multiplication operations in the CSIDH key exchange process are all implemented by the acceleration method of polynomial multiplication, wherein the number of multipliers is N, N is the number of terms of the polynomial involved in the CSIDH key exchange process, in a 64-bit integer operation environment, N is 8 in the CSIDH key exchange process using the CSIDH512 parameter set, N is 16 in the CSIDH key exchange process using the CSIDH1024 parameter set, and N is 32 in the CSIDH key exchange process using the CSIDH2048 parameter set.

2. A polynomial multiplication acceleration device, characterized in that: It includes m pre-processing external blocks, an input sorting module, k pre-processing internal blocks, a set of central multiplier arrays, k post-processing internal blocks, an output integration module, and m post-processing external blocks, where m and k are positive integers. The m pre-processing external blocks are used to input two sets of polynomial coefficients, and the number of terms in each set of polynomial coefficients is where p1, p2, ..., p m are the 1st, 2nd, ..., mth repeatable prime factors of the term respectively; then the two sets of polynomial coefficients are The Karatsuba algorithm performs operations on all operation rules before the data stream reaches the multiplication operation, and obtains two sets of external pre-processed data; The input sorting module is used to sort and reorder the two sets of external pre-processed data to obtain sorted data; The k pre-processing internal blocks are used to sort the sorted data into The Karatsuba algorithm performs operations on all the operation rules before the data stream reaches the multiplication operation, and obtains two sets of internal pre-processed data, where p -1 、p -2 、……、p -k are the 1st, 2nd, ..., kth prime factors specified according to usage requirements; The set of central multiplier arrays is used to perform multiplication operations on corresponding data in the two sets of internal pre-processed data to obtain a set of preliminary product data; The k post-processing internal blocks are used to process the preliminary product data according to the number of items. The Karatsuba algorithm performs operations on all operation rules after the multiplication operation in the data stream to obtain internal post-processed data; The output integration module is used to reorder, shift and add the internal post-processed data to obtain integrated data; The m post-processing external blocks are used to process the integrated data in terms of the number of items. The Karatsuba algorithm performs all the operation rules after the multiplication operation in the data stream to obtain the final output data, that is, the number of items is The product polynomial coefficients of ; The polynomial multiplication acceleration device is used as a key exchange acceleration device.

3. The device according to claim 2, characterized in that The m preprocessing external blocks are KA_pre module; The k preprocessing internal blocks are KA_pre module; The k post-processing internal blocks are KA_post module; The m post-processing external blocks are KA_post module; in Respectively represent the number of items p1, p2, ..., p m Karatsuba algorithm module; in Respectively represent the 1st, 2nd, ..., kth prime factors p specified according to usage requirements -1 、p -2 、……、p -k The corresponding number of terms is p -1 、p -2 、……、p -k Karatsuba algorithm module; The KA_pre module represents the hardware device that performs all operations that the data flow in the Karatsuba algorithm undergoes from the input to all multiplication operations. The KA_post module represents the hardware device that performs all operations that the data flow undergoes after all multiplication operations to the output end in the Karatsuba algorithm.

4. The device according to claim 3, characterized in that The central multiplier array includes a plurality of integer multipliers, wherein the number of multipliers is determined by and The structure of and The corresponding number of central multipliers are l1, l2, ..., l m and l -1 ,l -2 ,...,l -k When , the number of central multipliers is indivual.

5. The device according to claim 4, characterized in that The input sorting module is used to execute the following input sorting algorithm: enter: Output: in Indicates the first group number of input sorting modules is The first Input binary integer data, Indicates the number of two groups of input sorting modules is The first group of input data Input binary integer data; Indicates the first group of the first output data of the input sorting module. binary integer data, Indicates the first group of output data in the input sorting module. binary integer data, ..., Indicates the first set of output data of the input sorting module. The first in the group binary integer data; Indicates the first group of the second group of output data of the input sorting module. binary integer data, Indicates the first of the second group of the second group of output data of the input sorting module. binary integer data, ..., Indicates the first output data of the second group of input sorting modules The first in the group Binary integer data.

6. The device according to claim 5, characterized in that The output integration module is used to execute the following output integration algorithm: enter: Output: in Indicates the first set of input data of the output integration module. binary integer data, Indicates the first binary integer data, ..., Indicates the output integration module The first binary integer data; in Indicates the output data of the output integration module. Binary positive integer data.

7. The device according to claim 6, characterized in that The input sorting module includes a sorting module and an input reordering module; The sorting module will two groups Each of the binary integer data is from low to high 0th to t-1th, tth to 2t-1th, ..., To The bits are taken out and formed into a new integer, where t is an integer set according to the usage requirements, and the initial data is obtained from each new integers into a group, forming A new array; The input reordering module will In the new array All the first The data are taken out and spliced into a new The number of data is Array of After the new array All the first data are taken out and new The number of data is Array of .

8. The device according to claim 7, characterized in that The output integration module includes an output reordering module, a shift module array, and an addition array; The output reordering module will The number of data is The first The data are taken out and spliced into a new The number of data is Array of .

9. The device according to claim 8, characterized in that The shift module array will reorder the first The data are filled with zeros in the high position, and then shifted left using the shift register in binary Get new data.

10. The device according to claim 9, characterized in that The addition array will shift all the The data are added together using an adder to get a sum, and all the arrays get Such sums are obtained and the obtained sums are output as output data of the addition array.

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