A method for preparing a trench gate IGBT and a trench gate IGBT chip

Abstract

The present invention belongs to the field of power device technology and provides a trench-gate IGBT, a method for manufacturing the same, and a chip. A photomask is used to form alignment marks on the wafer surface to define scribe lines and chip regions, facilitating alignment of subsequent photomasks. P-type dopant ions are then implanted into the front surface of the drift layer under the cover of an isolation layer in the terminal region to form multiple P-type rings in the terminal region. Multiple trenches are formed in the cell region, a gate oxide layer is formed within each trench, and polysilicon material is deposited to form a polysilicon layer. P-type dopant ions are implanted into the front surface of the drift layer to form a P-type well region. N-type dopant ions are then implanted to form an N-type source region and a stop ring region. P-type dopant ions are then implanted through contact holes in the dielectric layer to form an ohmic contact impurity layer on the N-type source region. Metal material is then deposited to form a gate electrode, an emitter electrode, and a terminal metal layer. Through the novel process and structure, an IGBT structure is formed without the use of a polysilicon photomask, thus saving the need for a polysilicon photomask.

Description

Technical Field

[0001] The present invention belongs to the technical field of power devices, and in particular relates to a method for preparing a trench gate IGBT, a trench gate IGBT, and a chip. Background Art

[0002] The insulated gate bipolar transistor (IGBT) is a new type of power electronic device that combines the bipolar junction transistor (BJT) and the metal-oxide-semiconductor field-effect transistor (MOSFET). IGBTs combine the simple control and high input impedance of MOSFETs with the low on-state voltage and high current capacity of BJTs. They are widely used in new energy, medical, industrial automation, rail transportation, and other fields.

[0003] Since the advent of the IGBT, improving performance and reducing costs have been the development direction of IGBT technology. To reduce the on-state voltage drop of the IGBT, the trench gate structure has been applied to IGBT devices. By converting the lateral channel into a vertical channel, the trench gate structure can eliminate the JFET resistance, reduce the cell size, increase the cell density, reduce the channel resistance, and achieve better performance than the planar gate.

[0004] However, in existing trench gate IGBT devices, polysilicon needs to be modified by designing a polysilicon etching mask, which not only complicates the preparation process but also increases the production cost of the device. Summary of the Invention

[0005] The purpose of the present invention is to provide a method for preparing a trench gate IGBT, a trench gate IGBT, and a chip, aiming to solve the problem that in existing trench gate IGBT devices, the preparation process is complicated and the production cost of the device is increased due to the need to modify the polysilicon by designing a polysilicon etching mask.

[0006] A first aspect of an embodiment of the present invention provides a method for manufacturing a trench gate IGBT, the method comprising:

[0007] Using a first mask to form an alignment mark at a preset position on the front surface of the drift layer; wherein the alignment mark is used to determine the chip area, and the chip area includes a cell area and a terminal area;

[0008] forming a thermal oxide layer on the front surface of the drift layer, and etching the thermal oxide layer under a second mask to form an isolation layer of a preset pattern; wherein the isolation layer is located in the terminal region;

[0009] Using the third photomask as a mask, implanting P-type dopant ions into the front surface of the drift layer to form a plurality of P-type rings in the terminal region;

[0010] Using a fourth mask to form a plurality of trenches on the front surface of the drift layer, and forming a gate oxide layer in each of the trenches; wherein the plurality of trenches are located in the cell region;

[0011] Depositing a polysilicon material on the front surface of the drift layer, and etching the polysilicon material to form a polysilicon layer in the trench;

[0012] Injecting P-type dopant ions into the front surface of the drift layer to form a P-type well region, and using a fifth mask to inject N-type dopant ions into the front surface of the drift layer to form an N-type source region and a stop ring region;

[0013] forming a dielectric layer, and forming a contact hole on the dielectric layer using a sixth photomask;

[0014] Using the dielectric layer as a mask, P-type dopant ions are implanted at the contact hole to form an ohmic contact impurity layer, and a metal material is deposited. Under the cover of a seventh photomask, the metal material is etched to obtain a gate electrode, an emitter electrode, and a terminal metal layer; wherein the emitter electrode contacts the ohmic contact impurity layer, and the terminal metal layer contacts the P-type ring and the cutoff ring region;

[0015] A buffer layer is formed on the back side of the drift layer, and P-type dopant ions are implanted on the back side of the buffer layer to form a collector region. A metal material is sputtered on the collector region to form a collector electrode.

[0016] In one embodiment, the doping concentration of the P-type ring is greater than the doping concentration of the P-type well region.

[0017] In one embodiment, the depth of the P-type ring is greater than the depth of the P-type well region.

[0018] In one embodiment, forming an alignment mark at a preset position on the front surface of the drift layer using a first mask includes:

[0019] The alignment mark is formed in a scribing street of the drift layer using the first photomask, wherein the alignment mark is located in a diagonal region of the scribing street, and the chip region is surrounded by the scribing street.

[0020] In one embodiment, the step of forming a plurality of trenches on the front surface of the drift layer using a fourth mask and forming a gate oxide layer in each of the trenches includes:

[0021] Etching the drift layer under the cover of the fourth photomask to form a plurality of trenches in a cell region on the drift layer;

[0022] The gate oxide layer is formed on the surface of each trench by thermal oxidation.

[0023] In one embodiment, depositing a polysilicon material on the front surface of the drift layer and etching the polysilicon material to form a polysilicon layer in the trench includes:

[0024] Polysilicon is deposited on the front side of the drift layer, and the polysilicon material on the surface of the drift layer is etched without a mask until the drift layer is exposed, so as to retain the polysilicon in the trench.

[0025] In one embodiment, the forming of the dielectric layer and forming the contact hole on the dielectric layer using a sixth photomask includes:

[0026] forming the dielectric layer in the cell region on the front side of the drift layer by depositing silicon nitride or silicon oxide;

[0027] Etching the dielectric layer under the cover of the fifth photomask to form a plurality of contact holes on the dielectric layer;

[0028] Wherein, the contact hole is provided between adjacent trenches.

[0029] In one embodiment, the depositing of the metal material and etching the metal material under the cover of the seventh mask to obtain the gate electrode, the emitter electrode and the terminal metal layer include:

[0030] Depositing a metal material on the dielectric layer, and etching the metal material under the cover of the seventh mask to form a gate electrode and an emitter electrode in the cell region, and forming a terminal metal layer in the terminal region;

[0031] The emitter electrode is located above the polysilicon layer, and the emitter electrode is in contact with the ohmic contact impurity layer.

[0032] A second aspect of the embodiments of the present application further provides a trench gate IGBT, which is prepared by any of the preparation methods described above.

[0033] A third aspect of the embodiments of the present application further provides a chip, which includes the trench gate IGBT as described above; or the chip includes the trench gate IGBT prepared by any of the preparation methods described above.

[0034] The present application provides a trench gate IGBT and a method for manufacturing the same, as well as a chip. First, a first mask is used to form an alignment mark at a preset position on the front side of a drift layer to define a chip region including a cell region and a terminal region. Then, an isolation layer of a preset pattern is formed in the terminal region. Under the cover of the isolation layer, P-type dopant ions are implanted into the front side of the drift layer to form a plurality of P-type rings in the terminal region. Multiple trenches are formed in the cell region, a gate oxide layer is formed in each trench, and polysilicon material is deposited in the trenches to form a polysilicon layer in each trench. P-type dopant ions are implanted into the front side of the drift layer to form a P-type well region. N-type dopant ions are then implanted to form an N-type source region and a stop ring region. P-type dopant ions are implanted through contact holes in a dielectric layer to form an ohmic contact impurity layer on the N-type source region. Metal material is deposited to obtain a gate electrode, an emitter electrode, and a terminal metal layer. The IGBT structure is formed without using a polysilicon mask, thus saving the polysilicon mask without affecting the performance of the IGBT. This solves the problems of complex process and high production cost associated with trench gate structure IGBTs due to the need for a polysilicon etching process. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a schematic flow chart of a method for preparing a trench gate IGBT provided in an embodiment of the present invention.

[0036] Figure 2 It is a schematic diagram of forming an alignment mark provided by an embodiment of the present invention.

[0037] Figure 3 is a schematic diagram of a chip area 200 provided in an embodiment of the present invention.

[0038] Figure 4 It is a schematic cross-sectional view of a trench gate IGBT provided by an embodiment of the present invention.

[0039] Figure 5 1 is a schematic top view of a trench gate IGBT provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0041] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0042] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0043] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0044] In existing trench gate IGBT devices, polysilicon needs to be modified by designing a polysilicon etching mask, which not only complicates the preparation process but also increases the production cost of the device.

[0045] In order to solve the above technical problems, the present invention provides a method for preparing a trench gate IGBT. Figure 1 As shown, the preparation method in this embodiment includes steps S100 to S900.

[0046] In step S100 , an alignment mark is formed at a predetermined position on the front surface of the drift layer using a first mask.

[0047] For details, see Figure 2 As shown, an alignment mark 101 is formed at a preset position of the drift layer for position reference in subsequent process steps, wherein the alignment mark 101 is used to determine the scribing lane 102 to set a reference for the scribing process of subsequent devices, wherein the chip area 200 is surrounded by the scribing lane 102.

[0048] In a specific application embodiment, in step S100 , forming an alignment mark at a preset position on the front surface of the drift layer using a first mask specifically includes: forming the alignment mark in a scribe line of the drift layer using the first mask.

[0049] In this embodiment, combined with Figure 2 As shown, the alignment mark 101 is located at a diagonal region of a scribe line 102 , and the chip region 200 of the trench gate IGBT is surrounded by the scribe lines 102 . The scribe lines 102 are arranged in a grid pattern on the drift layer.

[0050] In this embodiment, the position of the alignment mark 101 is determined by the first mask, for example, by etching a designated area on the front surface of the drift layer to form the alignment mark. The alignment mark 101 is set at the diagonal area of ​​the scribe line 102. The scribe line 102 is used to cut the chip substrate. The chip area 200 of each trench gate IGBT is surrounded by the scribe line 102. Figure 3 As shown, the chip region 200 includes a cell region 201 and a terminal region 202 , and the cell region 201 is surrounded by the terminal region 202 .

[0051] In step S200 , a thermal oxide layer is formed on the front surface of the drift layer, and the thermal oxide layer is etched under a second mask to form an isolation layer with a preset pattern.

[0052] In this embodiment, combined with Figure 4 As shown, the isolation layer 502 is disposed in the terminal region 202 within the chip region 200 , and a plurality of strip-shaped through holes are disposed on the isolation layer.

[0053] Specifically, a thermal oxide layer is formed on the drift layer 401 , and then the thermal oxide layer is etched under the cover of a second photomask to form the isolation layer 502 of a preset pattern.

[0054] In one embodiment, the plurality of strip-shaped through holes on the isolation layer 502 are arranged in parallel.

[0055] In one embodiment, the plurality of strip-shaped through holes on the isolation layer 502 are parallel to the dicing streets 102 .

[0056] In step S300 , using a third photomask as a mask, P-type dopant ions are implanted into the front surface of the drift layer to form a P-type ring.

[0057] In this embodiment, combined with Figure 4 As shown, the position of the P-type ring 301 is determined by using the third mask as a mask, and the cell area 201 and the preset stop ring area are covered by the third mask. Then, P-type dopant ions are injected into the front surface of the drift layer 401, so that the P-type dopant ions are injected into the drift layer 401 through the strip-shaped through-holes on the isolation layer 502 to form the P-type ring 301. Specifically, the P-type ring 301 is located in the terminal area 202, Figure 4 The dotted line B in the figure indicates that there can be multiple P-type rings 301 , the distance between adjacent P-type rings 301 is L1 , and the P-type rings 301 near the boundary between the terminal region 202 and the cell region 201 are in contact with the P-type well region 407 .

[0058] In one embodiment, the strip-shaped through hole is located in the central area of ​​the P-type ring 301 , and the P-type ring 301 may be arranged symmetrically with respect to the strip-shaped through hole.

[0059] In some embodiments, the doping ions in the P-type ring 301 are of different types from the doping ions in the drift layer 401 . For example, the P-type ring 301 is doped with P type, and the drift layer 401 is doped with N type.

[0060] In some embodiments, the N-type dopant ions doped into the drift layer 401 may be phosphorus ions, nitrogen ions, etc.

[0061] In some embodiments, the P-type dopant ions doped in the P-type ring 301 may be aluminum ions, boron ions, etc.

[0062] In step S400 , a fourth photomask is used to form a plurality of trenches on the front surface of the drift layer, and a gate oxide layer is formed in each of the trenches.

[0063] In this embodiment, combined with Figure 4 As shown, a fourth mask can be used to cover the cell region 201, and the position of the groove can be determined by the fourth mask. By etching the drift layer 401, multiple grooves are formed in the cell region 201 on the front side of the drift layer 401. The multiple grooves penetrate into the drift layer 401 and a gate oxide layer 405 is formed in each groove.

[0064] In a specific application embodiment, the drift layer 401 may serve as a drift region, and its doping type is N-type doping.

[0065] In a specific application embodiment, in step S400, a fourth mask is used to form a plurality of grooves on the front surface of the drift layer, and a gate oxide layer is formed in each of the grooves, specifically including: etching the drift layer 401 under the cover of the fourth mask to form a plurality of grooves in the cell region 201 on the drift layer 401; and forming a gate oxide layer 405 on the surface of each groove by thermal oxidation.

[0066] In this embodiment, the groove position is determined by a fourth mask, and then under the cover of the fourth mask, the cell region 201 on the front side of the drift layer 401 is etched to form a plurality of grooves in the cell region 201 on the front side of the drift layer 401. Furthermore, the inner surface of the groove is oxidized by thermal oxidation to obtain silicon oxide, thereby serving as the gate oxide layer 405.

[0067] In some embodiments, the plurality of grooves are arranged in parallel.

[0068] In some embodiments, the distances between adjacent grooves are equal.

[0069] In some specific application embodiments, the width of the groove is 0.1-0.5 um.

[0070] In some specific application embodiments, the width of the trench in the cell region 201 is smaller than the width of the P-type ring 301 in the terminal region 202 .

[0071] In step S500 , a polysilicon material is deposited on the front surface of the drift layer 401 , and the polysilicon material is etched to form a polysilicon layer 406 in the trench.

[0072] In this embodiment, combined with Figure 4 As shown, polysilicon material is deposited on the front side of the drift layer 401 formed in step S400, and then the polysilicon material on the front side of the drift layer 401 is removed, leaving only the polysilicon material in the trench, and forming a polysilicon layer 406 in the trench. At this time, only the trench is provided with polysilicon material in the IGBT device, and all the polysilicon material in the terminal area 202 is etched away, so that after the polysilicon material is deposited, there is no need to use a mask for etching, and all of it can be directly etched, thereby saving a layer of mask and one photolithography, which greatly saves costs.

[0073] In this embodiment, step S500 specifically includes: depositing polysilicon material on the front side of the drift layer 401, and performing indiscriminate etching on the polysilicon material on the front side of the drift layer 401 without a mask until the drift layer 401 is exposed, so as to retain the polysilicon material in the trench.

[0074] In this embodiment, the polysilicon material deposited on the front side of the drift layer 401 is etched indiscriminately until the front side of the drift layer 401 is exposed. At this time, due to the same etching rate, the polysilicon in the trench is retained, while the polysilicon material deposited in the terminal area 202 is completely removed, leaving only the polysilicon material in the trench, thereby forming a polysilicon layer 406 in the trench.

[0075] In step S600 , P-type dopant ions are implanted into the front surface of the drift layer 401 to form a P-type well region 407 , and N-type dopant ions are implanted into the front surface of the drift layer 401 using a fifth mask to form an N-type source region 408 and a stop ring region 302 .

[0076] In this embodiment, the N-type source region 408 is located on the P-type well region 407. Since a plurality of trenches are provided on the front side of the drift layer 401 for filling polysilicon material to form a polysilicon layer 406, the P-type well region 407 is divided into a plurality of sub-well regions, and a plurality of N-type source regions 408 are respectively located on a plurality of P-type well regions 407.

[0077] The cut-off ring region 302 is located at the edge of the terminal region 202. At this time, the cut-off ring region 302 and the P-type well region 407 are located on both sides of the P-type ring 301. Multiple P-type rings 301 are provided between the cut-off ring region 302 and the P-type well region 407, and the distance between the cut-off ring region 302 and its adjacent P-type rings 301 is greater than the distance between adjacent P-type rings 301.

[0078] In one embodiment, combined Figure 4As shown, the distance between the cut-off ring region 302 and its adjacent P-type ring 301 is L2, and the distance between adjacent P-type rings 301 is L1, and L2 is greater than L1.

[0079] In one embodiment, L2 is at least three times greater than L1.

[0080] In some specific application embodiments, the depth of the P-type well region 407 may be 0.1-0.7 um.

[0081] In some specific embodiments, the thickness of the P-type well region 407 is less than the distance between adjacent trenches. In one specific embodiment, aluminum ions are implanted into the front surface of the drift layer 401. The aluminum ions enter the drift layer 401 through the drift layer region between adjacent trenches, thereby forming a P-type well region 407 in the drift layer 401 and a PN junction between the P-type well region 407 and the drift layer 401.

[0082] In one embodiment, the thickness of the P-type well region 407 is smaller than the thickness of the polysilicon layer 406 .

[0083] In a specific application embodiment, under the cover of a fifth photomask, phosphorus ions or nitrogen ions are implanted into the front surface of the drift layer 401 to form the N-type source region 408 and the stop ring region 302 .

[0084] In one embodiment, the thickness of the N-type source region 408 is less than half the thickness of the P-type well region 407 .

[0085] In one embodiment, the doping concentration of the P-type ring 301 is greater than the doping concentration of the P-type well region 407 .

[0086] In one embodiment, the doping concentration of the P-type ring 301 is at least ten times the doping concentration of the P-type well region 407 .

[0087] In one embodiment, the thickness of the P-type ring 301 is greater than the thickness of the P-type well region 407 .

[0088] In step S700 , a dielectric layer 501 is formed, and a contact hole is formed on the dielectric layer 501 using a sixth photomask.

[0089] In this embodiment, combined with Figure 4 As shown, a dielectric layer 501 is formed on the N-type source region 408 and the polysilicon layer 406, and the positions of the contact holes on the dielectric layer 501 are determined by a sixth photomask. Then, the dielectric layer 501 is etched under the cover of the sixth photomask to form multiple contact holes on the dielectric layer 501, wherein the contact holes extend deep into the P-type well region 407. At this time, the N-type source region 408 between adjacent polysilicon layers 406 is divided into two parts, and the two parts of the N-type source region 408 are respectively located on both sides of the contact hole.

[0090] In one embodiment, the dielectric layer 501 covers the N-type source region 408 , the polysilicon layer 406 , and the gate oxide layer 405 , and the contact hole is located between adjacent sub-well regions.

[0091] In some specific application embodiments, in step S700 , a dielectric layer 501 can be formed on the surface of the N-type source region 408 and the polysilicon layer 406 by depositing silicon nitride material or silicon oxide, and then the dielectric layer 501 is etched under the cover of a sixth mask to form multiple contact holes.

[0092] In step S800, Figure 4 and Figure 5 As shown, using the dielectric layer 501 as a mask, P-type dopant ions are implanted at the contact hole to form an ohmic contact impurity layer 409, and metal material is deposited. Under the cover of the seventh mask, the metal material is etched to obtain a gate electrode 530, an emitter electrode 521 and a terminal metal layer 522.

[0093] In this embodiment, the gate electrode 530 is arranged on the dielectric layer 501. At this time, the dielectric layer 501 is arranged between the gate electrode 530 and the drift layer 401, that is, there is neither a P-type well region 407 nor a polysilicon layer 406 below the gate electrode 530, and the emitter electrode 521 covers the dielectric layer 501 above the P-type well region 407 and the polysilicon layer 406.

[0094] In one embodiment, the emitter electrode 521 contacts the ohmic contact impurity layer 409 , and the terminal metal layer 522 contacts the P-type ring 301 and the stop ring region 302 .

[0095] In this embodiment, there are multiple terminal metal layers 522 , and the multiple terminal metal layers 522 are respectively connected to the multiple P-type rings 301 and the stop ring area 302 .

[0096] In one embodiment, Figure 4 As shown, the vertical cross section of the terminal metal layer 522 is L-shaped, as shown in FIG. Figure 5 As shown, the horizontal cross-section of the terminal metal layer 522 is rectangular.

[0097] In one embodiment, the plurality of terminal metal layers 522 are arranged horizontally.

[0098] In one embodiment, multiple terminal metal layers 522 can be connected to different voltages, so that the electric field of the terminal area 202 can be adjusted by connecting to different voltages. For example, the cut-off ring area 302 is connected to the external voltage through its corresponding terminal metal layer 522, which can ensure that there is no potential difference at the edge of the chip even when it is subjected to high voltage. At this time, the electric field is cut off at the cut-off ring area 302.

[0099] In a specific application embodiment, multiple P-type rings 301 are connected to an external voltage through their corresponding terminal metal layers 522 , so that the electric field in the P-type rings 301 can be led to the outside, thereby improving the curvature of the device.

[0100] In a specific application embodiment, the external voltage connected to the terminal metal layer 522 corresponding to the plurality of P-type rings 301 gradually increases from close to the cell region 201 to far away from the cell region 201 .

[0101] In a specific application embodiment, the voltage values ​​of the external voltages connected to the terminal metal layers 522 corresponding to the multiple P-type rings 301 are arranged in an equidistant manner.

[0102] In one embodiment, the thickness of the isolation layer 502 is greater than the thickness of the dielectric layer 501 .

[0103] In one embodiment, the thickness of the isolation layer 502 is 120 μm.

[0104] In step S900 , a buffer layer 402 is formed on the back side of the drift layer 401 , and P-type dopant ions are implanted on the back side of the buffer layer 402 to form a collector region 403 . Metal material is sputtered on the collector region 403 to form a collector electrode 523 .

[0105] In this embodiment, the buffer layer 402 is disposed between the collector region 403 and the drift layer 401 , and the collector region 403 is disposed between the buffer layer 402 and the collector electrode 523 .

[0106] In one embodiment, the doping concentration of the drift layer 401 is lower than the doping concentration of the buffer layer 402 .

[0107] In one embodiment, both the drift layer 401 and the buffer layer 402 are doped with N-type dopant ions.

[0108] An embodiment of the present application further provides a trench gate IGBT, which is prepared by any of the preparation methods described above.

[0109] In this embodiment, the chip area of ​​the trench gate IGBT consists of a cell area and a terminal area, and the cell area is surrounded by the terminal area. P-type dopant ions are injected into the front side of the drift layer under the cover of the isolation layer in the terminal area to form a plurality of P-type rings in the terminal area, a plurality of trenches are formed in the cell area, a gate oxide layer is formed in each trench, and polysilicon material is deposited to form a polysilicon layer, P-type dopant ions are injected into the front side of the drift layer to form a P-type well region, and then N-type dopant ions are injected to form an N-type source region and a cut-off ring region, P-type dopant ions are injected through the contact hole on the dielectric layer to form an ohmic contact impurity layer on the N-type source region, and metal material is deposited to obtain a gate electrode, an emitter electrode and a terminal metal layer. By designing a novel process and structure, an IGBT structure is formed without using a polysilicon mask, thus saving a polysilicon mask.

[0110] An embodiment of the present application further provides a chip, which includes the trench gate IGBT described above.

[0111] In one embodiment, a chip includes a trench gate IGBT manufactured by any of the above manufacturing methods.

[0112] In this embodiment, an integrated circuit is provided in the chip, and the trench gate IGBT is applied to the integrated circuit. The integrated circuit is formed on a wafer substrate, and the trench gate IGBT in the integrated circuit can be the trench gate IGBT described in any of the above embodiments.

[0113] Those skilled in the art will clearly understand that for the sake of convenience and brevity in description, only the division of the above-mentioned doping regions is used as an example. In actual applications, the above-mentioned functional areas can be allocated to different doping regions as needed, that is, the internal structure of the device can be divided into different doping regions to complete all or part of the functions described above.

[0114] The doping regions in the embodiment can be integrated into one functional region, or each doping region can exist physically separately, or two or more doping regions can be integrated into one functional region. The above-mentioned integrated functional regions can be implemented by using the same doping ion or by using multiple doping ions. In addition, the specific names of the doping regions are only for the convenience of distinguishing each other and are not used to limit the scope of protection of this application. The specific working process of the doping region in the preparation method of the above-mentioned device can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0115] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention, and should all be included in the scope of protection of the present invention.

Claims

1. A method for preparing a trench gate IGBT, characterized in that: The preparation method comprises: Using a first mask to form an alignment mark at a preset position on the front surface of the drift layer; wherein the alignment mark is used to determine the chip area, and the chip area includes a cell area and a terminal area; forming a thermal oxide layer on the front surface of the drift layer, and etching the thermal oxide layer under a second mask to form an isolation layer of a preset pattern; wherein the isolation layer is located in the terminal region; Using the third photomask as a mask, implanting P-type dopant ions into the front surface of the drift layer to form a plurality of P-type rings in the terminal region; Using a fourth mask to form a plurality of trenches on the front surface of the drift layer, and forming a gate oxide layer in each of the trenches; wherein the plurality of trenches are located in the cell region; Depositing a polysilicon material on the front surface of the drift layer, and etching the polysilicon material to form a polysilicon layer in the trench; Injecting P-type dopant ions into the front surface of the drift layer to form a P-type well region, and using a fifth mask to inject N-type dopant ions into the front surface of the drift layer to form an N-type source region and a stop ring region; forming a dielectric layer, and forming a contact hole on the dielectric layer using a sixth photomask; Using the dielectric layer as a mask, P-type dopant ions are implanted at the contact hole to form an ohmic contact impurity layer, and a metal material is deposited. Under the cover of a seventh photomask, the metal material is etched to obtain a gate electrode, an emitter electrode, and a terminal metal layer; wherein the emitter electrode contacts the ohmic contact impurity layer, and the terminal metal layer contacts the P-type ring and the cutoff ring region; A buffer layer is formed on the back side of the drift layer, and P-type dopant ions are implanted on the back side of the buffer layer to form a collector region. A metal material is sputtered on the collector region to form a collector electrode.

2. The preparation method according to claim 1, wherein The doping concentration of the P-type ring is greater than the doping concentration of the P-type well region.

3. The preparation method according to claim 2, wherein The depth of the P-type ring is greater than the depth of the P-type well region.

4. The preparation method according to any one of claims 1 to 3, wherein The method of forming an alignment mark at a preset position on the front side of the drift layer using a first mask comprises: The alignment mark is formed in a scribing street of the drift layer using the first photomask, wherein the alignment mark is located in a diagonal region of the scribing street, and the chip region is surrounded by the scribing street.

5. The preparation method according to any one of claims 1 to 3, characterized in that The method of forming a plurality of trenches on the front surface of the drift layer by using a fourth mask and forming a gate oxide layer in each of the trenches includes: Etching the drift layer under the cover of the fourth photomask to form a plurality of trenches in a cell region on the drift layer; The gate oxide layer is formed on the surface of each trench by thermal oxidation.

6. The preparation method according to claim 1, wherein The method comprises depositing a polysilicon material on the front surface of the drift layer and etching the polysilicon material to form a polysilicon layer in the trench, comprising: Polysilicon is deposited on the front side of the drift layer, and the polysilicon material on the surface of the drift layer is etched without a mask until the drift layer is exposed, so as to retain the polysilicon in the trench.

7. The preparation method according to claim 1, wherein The step of forming a dielectric layer and forming a contact hole on the dielectric layer using a sixth photomask includes: forming the dielectric layer in the cell region on the front side of the drift layer by depositing silicon nitride or silicon oxide; Etching the dielectric layer under the cover of the fifth photomask to form a plurality of contact holes on the dielectric layer; Wherein, the contact hole is provided between adjacent trenches.

8. The preparation method according to claim 1, wherein The depositing of the metal material and etching the metal material under the cover of the seventh mask to obtain the gate electrode, the emitter electrode and the terminal metal layer include: Depositing a metal material on the dielectric layer, and etching the metal material under the cover of the seventh mask to form a gate electrode and an emitter electrode in the cell region, and forming a terminal metal layer in the terminal region; The emitter electrode is located above the polysilicon layer, and the emitter electrode is in contact with the ohmic contact impurity layer.

9. A trench gate IGBT, characterized in that: The trench gate IGBT is prepared by the preparation method according to any one of claims 1 to 8.

10. A chip, characterized in that: The chip includes the trench gate IGBT according to claim 9; or the chip includes the trench gate IGBT prepared by the preparation method according to any one of claims 1 to 8.

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