Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The application provides a semiconductor structure preparation method and a semiconductor structure, and relates to the technical field of semiconductors. The semiconductor structure preparation method comprises the following steps: providing a first interconnection layer; forming an interlayer dielectric layer on the first interconnection layer; forming a via in the interlayer dielectric layer, wherein the via comprises a first via, a second via and a third via which are sequentially connected, the diameter of the central cross section of the second via is greater than the diameter of the central cross section of the first via and the third via; and forming a conductive structure in the via. The application increases the diameter of the central cross section of the second via, so that a gap is not easily generated when the conductive material is filled into the via, the resistance of the conductive structure is effectively reduced, and the transmission performance of the semiconductor structure is improved without changing the metal interconnection structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure and the semiconductor structure thereof. Background Technology

[0002] Dynamic random access memory (DRAM) is a semiconductor memory that allows for high-speed, random writing and reading of data and is widely used in data storage devices or apparatuses.

[0003] Dynamic random access memory typically includes at least two interconnect layers, which are connected by conductive structures to achieve electrical connection between adjacent interconnect layers.

[0004] However, during the formation of the conductive structure, air gaps can easily form within the conductive structure, increasing the resistance of the conductive structure and thus reducing the performance of the semiconductor structure. Summary of the Invention

[0005] In view of the above problems, embodiments of the present invention provide a method for preparing a semiconductor structure and a semiconductor structure, which are used to reduce the resistance of the conductive structure and improve the performance of the semiconductor structure.

[0006] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0007] A first aspect of this invention provides a method for fabricating a semiconductor structure, comprising the following steps:

[0008] Provide the first interconnect layer;

[0009] An interlayer dielectric layer is formed on the first interconnect layer;

[0010] A via is formed within the interlayer dielectric layer. The via includes a first via, a second via, and a third via connected in sequence. The diameter of the central cross-section of the second via is larger than the diameter of the central cross-section of the first via and the third via.

[0011] A conductive structure is formed within the through hole;

[0012] A second interconnect layer is formed on the interlayer dielectric layer, at least covering the conductive structure.

[0013] The semiconductor structure fabrication method described above, wherein the step of forming a via within the interlayer dielectric layer includes:

[0014] An etched hole is formed within the interlayer dielectric layer;

[0015] An etching barrier layer is formed inside the etching hole, the top surface of the etching barrier layer is lower than the top surface of the interlayer dielectric layer, and the etching barrier layer and the interlayer dielectric layer form an intermediate hole;

[0016] The intermediate hole is etched to form a second through hole;

[0017] The etching barrier layer is removed to form a first through-hole, and the etched holes other than the first and second through-holes constitute a third through-hole.

[0018] In the semiconductor structure fabrication method described above, the longitudinal section is a plane perpendicular to the first interconnect layer, and the longitudinal section shape of the second via is a polygon.

[0019] In the semiconductor structure fabrication method described above, the via includes at least two sub-vias, each of which includes a first sub-via, a second sub-via, and a third sub-via connected in sequence.

[0020] In the semiconductor structure fabrication method described above, the diameter of the central cross-section of the second sub-via is larger than the diameter of the central cross-section of the first sub-via and the third sub-via.

[0021] In the semiconductor structure fabrication method described above, two adjacent sub-vias are spaced apart.

[0022] In the semiconductor structure fabrication method described above, the second sub-vias of two adjacent sub-vias are in point contact.

[0023] In the semiconductor structure fabrication method described above, the second sub-vias of two adjacent sub-vias are connected.

[0024] The semiconductor structure fabrication method described above, wherein the step of forming a conductive structure within the via includes:

[0025] A barrier layer is formed on the sidewall of the through hole;

[0026] A conductive layer is formed within the area enclosed by the barrier layer, and the conductive layer fills the area enclosed by the barrier layer.

[0027] In the semiconductor structure fabrication method described above, the barrier layer is made of titanium nitride, and the conductive layer is made of tungsten.

[0028] A second aspect of the present invention provides a semiconductor structure comprising:

[0029] First interconnect layer;

[0030] An interlayer dielectric layer is disposed on the first interconnect layer;

[0031] A conductive structure is disposed within the interlayer dielectric layer. The conductive structure includes a first conductive structure, a second conductive structure, and a third conductive structure connected in sequence. The diameter of the central cross-section of the second conductive structure is larger than the diameter of the central cross-section of the first conductive structure and the third conductive structure.

[0032] A second interconnect layer is disposed on the interlayer dielectric layer and at least covers the conductive structure.

[0033] In the semiconductor structure described above, the longitudinal section of the second conductive structure is a polygon with a plane perpendicular to the first interconnect layer as its longitudinal section.

[0034] The semiconductor structure described above, wherein the second conductive structure includes a first segment and a second segment connected to the first segment;

[0035] Along the vertical direction from bottom to top, the width of the first segment gradually increases, while the width of the second segment gradually decreases.

[0036] In the semiconductor structure described above, the conductive structure includes at least two sub-conductive structures, each of which includes a first sub-conductive structure, a second sub-conductive structure, and a third sub-conductive structure connected in sequence.

[0037] The diameter of the central cross-section of the second sub-conductive structure is larger than the diameter of the central cross-section of the first sub-conductive structure and the third sub-conductive structure.

[0038] In the semiconductor structure described above, two adjacent sub-conductive structures are spaced apart, or the second sub-conductive structures of two adjacent sub-conductive structures are connected.

[0039] Compared with the prior art, the semiconductor structure preparation method and semiconductor structure provided in the embodiments of the present invention, when preparing the through hole, by increasing the diameter of the central cross-section of the second through hole, it is not easy to generate voids when filling the through hole with conductive material, which effectively reduces the resistance of the conductive structure, thereby improving the transmission performance of the semiconductor structure without changing the metal interconnect structure.

[0040] In addition to the technical problems solved by the embodiments of the present invention, the technical features constituting the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, the semiconductor structure preparation method and semiconductor structure provided by the embodiments of the present invention, other technical problems that can be solved by the semiconductor structure, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further explained in detail in the specific embodiments. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 The process flow of the semiconductor structure fabrication method provided in the embodiments of the present invention Figure 1 ;

[0043] Figure 2 This is a schematic diagram of the structure forming the interlayer dielectric layer in the semiconductor structure fabrication method provided in the embodiments of the present invention;

[0044] Figure 3 The process flow of the semiconductor structure fabrication method provided in the embodiments of the present invention Figure 2 ;

[0045] Figure 4 This is a schematic diagram of the structure for forming etched holes in the semiconductor structure fabrication method provided in the embodiments of the present invention;

[0046] Figure 5 This is a schematic diagram of the structure forming the etch barrier layer in the semiconductor structure fabrication method provided in the embodiments of the present invention;

[0047] Figure 6 A schematic diagram of the structure for forming the second through-hole in the semiconductor structure fabrication method provided in this embodiment of the invention. Figure 1 ;

[0048] Figure 7 A schematic diagram of the structure for forming the second through-hole in the semiconductor structure fabrication method provided in this embodiment of the invention. Figure 2 ;

[0049] Figure 8 A schematic diagram of the structure forming a through hole in the semiconductor structure fabrication method provided in this embodiment of the invention. Figure 1 ;

[0050] Figure 9 A schematic diagram of the structure forming a through hole in the semiconductor structure fabrication method provided in this embodiment of the invention. Figure 2 ;

[0051] Figure 10 A schematic diagram of the structure forming a through hole in the semiconductor structure fabrication method provided in this embodiment of the invention. Figure 3 ;

[0052] Figure 11A schematic diagram of the structure forming a through hole in the semiconductor structure fabrication method provided in this embodiment of the invention. Figure 4 ;

[0053] Figure 12 This is a schematic diagram of the formation of a conductive structure in the semiconductor structure fabrication method provided in the embodiments of the present invention. Figure 1 ;

[0054] Figure 13 A schematic diagram of the structure forming a conductive structure in the semiconductor structure fabrication method provided in this embodiment of the invention. Figure 2 ;

[0055] Figure 14 A schematic diagram of the structure forming a conductive structure in the semiconductor structure fabrication method provided in this embodiment of the invention. Figure 3 ;

[0056] Figure 15 A schematic diagram of the structure for forming the second interconnect layer in the semiconductor structure fabrication method provided in this embodiment of the invention. Figure 1 ;

[0057] Figure 16 A schematic diagram of the structure for forming the second interconnect layer in the semiconductor structure fabrication method provided in this embodiment of the invention. Figure 2 ;

[0058] Figure 17 A schematic diagram of the structure for forming the second interconnect layer in the semiconductor structure fabrication method provided in this embodiment of the invention. Figure 3 ;

[0059] Figure 18 A schematic diagram of the structure for forming the second interconnect layer in the semiconductor structure fabrication method provided in this embodiment of the invention. Figure 4 .

[0060] Figure label:

[0061] 10: First interconnect layer; 11: First dielectric layer; 12: First interconnect structure; 20: Interlayer dielectric layer; 21: Etched via; 22: Etching barrier layer; 23: Intermediate via; 24: First through-hole; 25: Second through-hole; 251: First segment; 252: Second segment; 26: Third through-hole; 30: Through-hole; 31: Sub-through-hole; 311: First sub-through-hole; 312: Second sub-through-hole; 313: Third sub-through-hole; 40: Conductive structure; 41: First conductive structure; 42: Second conductive structure; 421: First segment; 422: Second segment; 43: Third conductive structure; 50: Second interconnect layer. Detailed Implementation

[0062] When forming a conductive structure, vias are usually formed in the interlayer dielectric layer, and then conductive material is deposited into the vias using a deposition process. As semiconductor structures become more integrated, the diameter of the vias is decreasing. Due to the limitations of the deposition process, voids will form in the formed conductive structure. These voids will increase the resistance of the conductive structure and thus reduce the transmission performance of the semiconductor structure.

[0063] Based on the above-mentioned technical problems, embodiments of the present invention provide a method for preparing a semiconductor structure and a semiconductor structure. By increasing the diameter of the central cross-section of the second through hole, it is not easy to generate voids when filling the through hole with conductive material, which effectively reduces the resistance of the conductive structure, thereby improving the transmission performance of the semiconductor structure without changing the metal interconnect structure.

[0064] To make the above-mentioned objectives, features, and advantages of the embodiments of the present invention more apparent and understandable, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0065] Figure 1 The process flow of the semiconductor structure fabrication method provided in the embodiments of the present invention Figure 1 , Figure 3 The process flow of the semiconductor structure fabrication method provided in the embodiments of the present invention Figure 2 ; Figure 2 , Figures 4-18 The diagram below illustrates the various stages of semiconductor structure fabrication. Figures 1-18 The methods for fabricating semiconductor structures are described in detail.

[0066] This embodiment does not limit the semiconductor structure. The following description will take dynamic random access memory (DRAM) as an example, but this embodiment is not limited to this. Other semiconductor structures are also possible in this embodiment.

[0067] like Figure 1 As shown in the figure, an embodiment of the present invention provides a method for fabricating a semiconductor structure, comprising the following steps:

[0068] Step S100: Provide the first interconnect layer.

[0069] like Figure 2As shown, the first interconnect layer 10 is used to realize the electrical connection between various devices in the semiconductor structure. The first interconnect layer 10 typically includes a first dielectric layer 11 and a first interconnect structure 12 disposed in the first dielectric layer 11. The material of the first dielectric layer 11 may include silicon oxide, and the material of the first interconnect structure 12 may include tungsten or copper.

[0070] Step S200: Form an interlayer dielectric layer on the first interconnect layer.

[0071] For example, continue to refer to Figure 2 An interlayer dielectric layer 20 can be formed on the first interconnect layer 10 using atomic layer deposition, chemical vapor deposition, or physical vapor deposition processes. The interlayer dielectric layer 20 is used to achieve insulation between the first interconnect layer 10 and other devices.

[0072] The material of the interlayer dielectric layer 20 may include insulating materials such as silicon oxide or silicon nitride.

[0073] Step S300: Form a via in the interlayer dielectric layer. The via includes a first via, a second via, and a third via connected in sequence. The diameter of the central cross-section of the second via is larger than the diameter of the central cross-section of the first and third vias.

[0074] It should be noted that, in this embodiment, the central cross-section refers to the cross-section passing through the center of the central axis of the second through hole.

[0075] like Figure 3 As shown, exemplarily, step S310: forming an etched hole within the interlayer dielectric layer.

[0076] A photoresist layer is formed on the interlayer dielectric layer 20, and an opening is formed in the photoresist layer by exposure, development or etching.

[0077] like Figure 4 As shown, the interlayer dielectric layer 20 exposed in the opening is removed by using an etching solution or etching gas to form an etching hole 21 in the interlayer dielectric layer 20. The etching hole 21 exposes the first interconnect structure 12. For example, the etching hole 21 can expose the entire first interconnect structure 12 or only a part of the first interconnect structure 12.

[0078] Step S320: An etching barrier layer is formed inside the etching hole. The top surface of the etching barrier layer is lower than the top surface of the interlayer dielectric layer. The etching barrier layer and the interlayer dielectric layer form an intermediate hole.

[0079] like Figure 5 As shown, an etching barrier layer 22 is formed in the etching hole 21 by chemical vapor deposition or physical vapor deposition. The top surface of the etching barrier layer 22 and the interlayer dielectric layer 20 form an intermediate hole 23.

[0080] The material of the etching barrier layer 22 may include silicon oxynitride.

[0081] Step S330: Etch the intermediate hole to form a second through hole.

[0082] A portion of the intermediate hole 23 can be etched to increase the width of that portion, and the widened portion of the intermediate hole 23 forms the second through hole 25.

[0083] Specifically, such as Figure 5 As shown, etching gas is introduced into the intermediate hole 23. The etching gas has a higher selectivity for etching the interlayer dielectric layer 20 than that for the barrier layer 22. During the etching process, due to the presence of the etching barrier layer, the sidewalls of the intermediate hole 23 can be etched without damaging the metal interconnect structure 12, thereby increasing the width of a portion of the intermediate hole 23 to form a second via 25. Compared with the prior art, the diameter of the central cross-section of the second via 25 formed in this embodiment is increased. When filling the via with conductive material, it can effectively avoid the formation of voids in the via during the filling process, which is beneficial to increasing the density of the conductive material filling and improving the transmission performance of the device.

[0084] It should be noted that, in this embodiment, the diameter and shape of the second via can be changed by controlling the etching rate.

[0085] like Figure 6 As shown, with the plane perpendicular to the first interconnect layer 10 as the longitudinal section, the longitudinal section shape of the second via 25 can be rectangular. The above structure can be formed in a one-time process, thereby simplifying the fabrication process of the second via.

[0086] like Figure 7 As shown, the longitudinal cross-sectional shape of the second through hole 25 can also be polygonal, for example, it can be hexagonal, that is, the diameter of the second through hole 25 increases first and then decreases along the vertical direction from bottom to top.

[0087] In other words, along the direction perpendicular to the first interconnect layer 10, the second via 25 includes a first via segment 251 and a second via segment 252 communicating with the first via segment 251. The longitudinal cross-sectional shape of the first via segment 251 and the second via segment 252 can be a trapezoidal structure, and the shapes of the first via segment 251 and the second via segment 252 are symmetrically arranged.

[0088] In this embodiment, the second through-hole 25 is divided into a first segment 251 and a second segment 252. When depositing conductive material into the second through-hole 25, it can be deposited in two stages: first, the first segment 251 is filled, and then the second segment 252 is filled. This avoids the generation of voids in the first and second segments during the filling process, which helps to reduce the through-hole resistance and improve the transmission performance of the semiconductor structure.

[0089] Step S340: Remove the etching barrier layer to form a first via, and the area of ​​the etched holes other than the first and second vias constitutes a third via.

[0090] like Figure 8 As shown, the etching barrier layer 22 can be removed by dry etching or wet etching. The via region formed after removing the etching barrier layer 22 constitutes the first via 24. The area of ​​the etched hole 21 other than the first via 24 and the second via 25 constitutes the third via 26. The first via 24, the second via 25 and the third via 26 constitute the via 30. Since the diameter of the central interface of the second via 25 increases, the volume of the via 30 increases. When filling the via with conductive material, the generation of voids during the filling process can be effectively avoided, which is beneficial to improving the density of the conductive material filling and improving the transmission performance of the semiconductor structure.

[0091] In some embodiments, such as Figures 9 to 11 As shown, the through hole 30 includes at least two sub-through holes 31. Each of the two sub-through holes 31 includes a first sub-through hole 311, a second sub-through hole 312, and a third sub-through hole 313 connected in sequence. The two second sub-through holes 312 can be simultaneously etched into a polygonal shape, for example, a hexagon. From bottom to top in the vertical direction, the diameter of the central cross-section of the second sub-through hole 312 shows a trend of first increasing and then decreasing, and the diameter of the central cross-section of the second sub-through hole 312 is greater than the diameter of the central cross-section of the first sub-through hole 311 and the third sub-through hole 313.

[0092] It should be noted that in this embodiment, the fabrication process of each sub-through hole is the same as the fabrication process of the through hole described above, and the concept of the central cross-section of the second sub-through hole is the same as that of the central cross-section of the second through hole. This embodiment will not elaborate further here.

[0093] In this embodiment, at least two sub-vias are provided. By simultaneously increasing the diameter of the central cross-section of the second sub-via, the generation of voids in the conductive structure can be minimized, the resistance of the conductive structure in the via can be reduced, and the transmission performance of the semiconductor structure can be improved.

[0094] In this embodiment, the positional relationship between two adjacent sub-holes can be selected in several ways, such as... Figure 9 As shown, two adjacent sub-through holes 31 can be spaced apart.

[0095] like Figure 10 As shown, the second sub-through holes 312 of two adjacent sub-through holes 31 can make point contact, so that the diameter of the two second sub-through holes is used as the diameter of the second through hole, thereby achieving the purpose of further increasing the diameter of the second through hole.

[0096] like Figure 11 As shown, the second sub-vias 312 of two adjacent sub-vias 31 can be connected, so that the sum of the diameters of the central cross-sections of the second sub-vias is equal to the diameter of the central cross-section of the second via. On the one hand, this can effectively reduce the resistance of the conductive structure, and on the other hand, it can also effectively reduce the parasitic resistance between the sub-vias. Without changing the metal interconnect structure, the transmission performance of the semiconductor structure is further improved.

[0097] Step S400: Form a conductive structure inside the through hole.

[0098] like Figures 12 to 14 As shown, conductive material is deposited into the through-holes through a deposition process to form a conductive structure 40.

[0099] For example, an atomic layer deposition process can be used to form a barrier layer on the sidewall of the via, wherein the barrier layer is made of titanium nitride. After the barrier layer is formed, a conductive layer can be formed in the area enclosed by the barrier layer using a physical vapor deposition process or a chemical vapor deposition process. The conductive layer fills the area enclosed by the barrier layer, and the conductive layer and the barrier layer constitute a conductive structure 40, wherein the conductive layer can be made of tungsten.

[0100] Step S500: Form a second interconnect layer on the interlayer dielectric layer that at least covers the conductive structure.

[0101] like Figures 15 to 18 As shown, a second interconnect layer 50 can be formed on the surface of the interlayer dielectric layer 20 away from the first interconnect layer 10 using a deposition process. The second interconnect layer 50 can completely cover the interlayer dielectric layer 20 or only cover the conductive structure 40.

[0102] It should be noted that the second interconnect layer 50 may also include a second dielectric layer and a second interconnect structure disposed within the second dielectric layer. The material of the second dielectric layer may include silicon oxide, and the material of the second interconnect structure may include copper.

[0103] like Figure 15 As shown, this embodiment of the invention also provides a semiconductor structure, including: a first interconnect layer 10, an interlayer dielectric layer 20, a conductive structure 40, and a second interconnect layer 50.

[0104] An interlayer dielectric layer 20 is disposed on the first interconnect layer 10, and a conductive structure 40 is disposed within the interlayer dielectric layer 20. The conductive structure 40 includes a first conductive structure 41, a second conductive structure 42, and a third conductive structure 43 connected in sequence. The diameter of the central cross-section of the second conductive structure 42 is larger than the diameter of the central cross-section of the first conductive structure and the third conductive structure.

[0105] It should be noted that, in this embodiment, the second conductive structure has a vertically arranged central axis running from bottom to top in the vertical direction, and the cross-section perpendicular to the center of the central axis is called the central cross-section.

[0106] The second interconnect layer 50 is disposed on the interlayer dielectric layer 20 and at least covers the conductive structure 40. The second interconnect layer 50 is used to realize the electrical connection between the conductive structure 40 and other devices of the semiconductor structure.

[0107] This embodiment utilizes the semiconductor structure fabrication method described in the above embodiments to increase the diameter of the central cross-section of the second conductive structure, making the diameter of the central cross-section of the second conductive structure larger than the diameters of the central cross-sections of the first and third conductive structures. This results in a larger volume of the conductive structure, which effectively avoids the generation of voids within the conductive structure during the filling of conductive material. This helps to reduce the resistance of the conductive structure and improve the transmission performance of the semiconductor structure.

[0108] In some embodiments, taking a plane perpendicular to the first interconnect layer 10 as the longitudinal section, the longitudinal section shape of the second conductive structure is a polygon. The polygon can be rectangular or hexagonal. For example, as shown... Figure 12 As shown, the longitudinal cross-sectional shape of the second conductive structure 42 can be rectangular, which can be prepared by a one-time deposition process, thus simplifying the preparation process of the second conductive structure.

[0109] like Figure 15 As shown, the second conductive structure 42 may also include a first segment 421 and a second segment 422 connected to the first segment 421. From bottom to top in the vertical direction, the width of the first segment 421 gradually increases and the width of the second segment 422 gradually decreases. The longitudinal cross-sectional shape of the first segment 421 and the second segment 422 are both trapezoidal, and the first segment 421 and the second segment 422 are symmetrical.

[0110] The second conductive structure can be formed through two deposition processes, which can effectively reduce the probability of voids forming in the second conductive structure, thereby helping to reduce the resistance of the second conductive structure and improve the transmission performance of the semiconductor structure.

[0111] Furthermore, such as Figures 16 to 18As shown, to minimize the resistance of the conductive structure, in this embodiment, the conductive structure 40 includes at least two sub-conductive structures 44. Each sub-conductive structure 44 includes a first sub-conductive structure, a second sub-conductive structure, and a third sub-conductive structure connected in sequence. The diameter of the central cross-section of the second sub-conductive structure is larger than the diameters of the central cross-sections of the first and third sub-conductive structures. By increasing the diameter of the central cross-section of the second sub-conductive structure, the filling volume of the conductive structure is effectively increased, further avoiding the generation of voids during the filling of the conductive material, improving the density of the filling material, and reducing the resistance of the conductive structure.

[0112] In some embodiments, such as Figure 16 As shown, adjacent sub-conductive structures 44 can be arranged at intervals, or as shown in the diagram. Figure 17 and Figure 18 As shown, the second sub-conductive structures of two adjacent sub-conductive structures 44 are connected.

[0113] Specifically, the connection of the second sub-conductive structures of two adjacent sub-conductive structures can be understood as the two second sub-conductive structures making point contact, or the two adjacent sub-conductive structures connecting to form a whole. By connecting the two sub-conductive structures at their point contact or forming a whole, the parasitic resistance between the sub-conductive structures can be effectively reduced, further improving the transmission performance of the semiconductor structure without changing the metal interconnect structure.

[0114] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0115] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with an embodiment or example that are included in at least one embodiment or example of the present invention.

[0116] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.

[0117] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: Provide the first interconnect layer; An interlayer dielectric layer is formed on the first interconnect layer; A via is formed within the interlayer dielectric layer. The via includes a first via, a second via, and a third via connected in sequence. The diameter of the central cross-section of the second via is larger than the diameter of the central cross-section of the first via and the third via. The through hole includes at least two sub-through holes, each of which includes a first sub-through hole, a second sub-through hole, and a third sub-through hole connected in sequence; the diameter of the central cross-section of the second sub-through hole is larger than the diameter of the central cross-section of the first sub-through hole and the third sub-through hole; the second sub-through holes of two adjacent sub-through holes are in point contact, or the second sub-through holes of two adjacent sub-through holes are connected. A conductive structure is formed within the through hole; A second interconnect layer is formed on the interlayer dielectric layer, at least covering the conductive structure.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The step of forming a via within the interlayer dielectric layer includes: An etched hole is formed within the interlayer dielectric layer; An etching barrier layer is formed inside the etching hole, the top surface of the etching barrier layer is lower than the top surface of the interlayer dielectric layer, and the etching barrier layer and the interlayer dielectric layer form an intermediate hole; The intermediate hole is etched to form a second through hole; The etching barrier layer is removed to form a first through-hole, and the etched holes other than the first and second through-holes constitute a third through-hole.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, With the plane perpendicular to the first interconnect layer as the longitudinal section, the longitudinal section shape of the second via is a polygon.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that, The step of forming a conductive structure within the through-hole includes: A barrier layer is formed on the sidewall of the through hole; A conductive layer is formed within the area enclosed by the barrier layer, and the conductive layer fills the area enclosed by the barrier layer.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that, The barrier layer is made of titanium nitride, and the conductive layer is made of tungsten.

6. A semiconductor structure, characterized in that, include: First interconnect layer; An interlayer dielectric layer is disposed on the first interconnect layer; A conductive structure is disposed within the interlayer dielectric layer. The conductive structure includes a first conductive structure, a second conductive structure, and a third conductive structure connected in sequence. The diameter of the central cross-section of the second conductive structure is larger than the diameter of the central cross-section of the first conductive structure and the third conductive structure. The second conductive structure includes a first segment and a second segment connected to the first segment; Along the vertical direction from bottom to top, the width of the first segment gradually increases, and the width of the second segment gradually decreases; The conductive structure includes at least two sub-conductive structures, each of which includes a first sub-conductive structure, a second sub-conductive structure, and a third sub-conductive structure connected in sequence. The diameter of the central cross-section of the second sub-conductive structure is larger than the diameter of the central cross-section of the first sub-conductive structure and the third sub-conductive structure; The second sub-conductive structures of two adjacent sub-conductive structures are connected; A second interconnect layer is disposed on the interlayer dielectric layer and at least covers the conductive structure.

7. The semiconductor structure according to claim 6, characterized in that, With the plane perpendicular to the first interconnect layer as the longitudinal section, the longitudinal section shape of the second conductive structure is a polygon.

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