A high-speed multi-concurrency programmable interlocking protection device

Abstract

The present invention provides a high-speed multi-concurrent programmable interlock protection device, which includes a main control unit and a first control and protection unit. The first control and protection unit includes a multi-channel interface configuration circuit, a high-speed optocoupler isolation circuit, and a logic transformation circuit connected in sequence. The interface configuration circuit is connected to a signal input end, and the logic transformation circuit is signal-connected to the main control unit. The main control unit includes a programmable logic device circuit, an output signal driving module connected to the programmable logic device circuit, and an MCU circuit. The programmable logic device circuit meets the requirements of the required functions under the programming of a hardware description language program. The present invention can be compatible with both level signals and interlock (on-off) signals as input signals at the same time, can control the positive and negative logic of the interlock channel, and achieves logical unity before entering the programmable logic device circuit for processing. The input channels formed by the combination of the interface configuration circuit and the logic transformation circuit have consistency, and all channels can be applicable to different signals and different logics.

Description

Technical Field

[0001] The present invention relates to the technical field of interlock protection devices, and in particular, to a high-speed multi-concurrency programmable interlock protection device. Background Art

[0002] An interlock protection device is a device that can control the automatic operation of related equipment according to specified conditions or procedures. The purposes of interlock protection generally include two aspects: First, interlock protection is caused by parameter overrun. When abnormal conditions or failures occur during the operation of equipment, individual or part of the equipment is automatically operated according to certain rules and requirements, so that the working process is transferred to normal operation or protection state, achieving the purpose of eliminating abnormalities and preventing accidents. This type of interlock often combines with a signal alarm system. Second, the interlock necessary for the normal operation of the equipment itself or the normal connection between equipment. During the working process, the start, stop, and normal operation of many equipment must be carried out under certain conditions or comply with certain operating procedures. There are also often relationships of mutual connection and restriction between equipment, and automatic control must be carried out according to certain procedures or conditions. Through interlock, not only can the above requirements be achieved, but also the operation steps can be transformed to avoid misoperation. This type of interlock is an interlock necessary for normal work.

[0003] Interlock protection devices are widely used in the field of industrial safety. The development of interlock protection devices is not limited to protection devices such as protective covers, but develops towards a more general concept. However, no matter how it develops, it at least includes two concepts: First, for safety; Second, it must be linked with control devices such as equipment and machinery. Fundamentally speaking: An interlock protection device is a technical measure to control hazard sources in the field of industrial safety.

[0004] For example Figure 5As shown in the figure, a block diagram of an interlock protection device that is currently used more frequently is shown; it has at least the following several defects: First, the input signals of the interlock protection device can basically be divided into two types: level signals and interlock (on-off) signals. In the absence of an interface configuration circuit, only one of these signals can be fixedly input, and each input channel cannot be adjusted and converted arbitrarily; Second, after passing through the optocoupler isolation circuit, the input signal directly enters the logic integrated circuit for processing. Without a logic transformation circuit, the optocoupler isolation circuit can only output a fixed logic. For example, some channels are positive logic (high level is normal), and some channels are negative logic (low level is normal). The logics are not unified, which is not convenient for the processing of the logic integrated circuit; Third, the logic integrated circuit can only process the input signals of all channels into one or several control signals according to a fixed logic, and it is not convenient to change the logic processing process; Fourth, after passing through the optocoupler isolation circuit, the input signal directly enters the MCU circuit to detect the channel state. Limited by devices and programs, the MCU cannot identify the sequence of changes in the states of multiple channels with close time, and cannot determine which channel is the first signal that causes the fault.

[0005] Therefore, it is urgent to improve the interlock protection device. Summary of the Invention

[0006] The purpose of the present invention is to solve the problems pointed out in the background technology, and provide a high-speed multi-concurrent programmable interlock protection device that can be compatible with both level signals and interlock (on-off) signals at the same time, can control the positive and negative logics of the interlock channels, achieve unified logic before entering the programmable logic device for processing, the input channels formed by the combination of the interface configuration circuit and the logic transformation circuit have consistency, all channels can be applicable to different signals and different logics, can identify the first fault signal in case of multi-channel concurrent faults, can latch all fault signals, quickly perform interlock protection, and can flexibly configure the bypass and shielding of each interlock channel.

[0007] The embodiment of the present invention is realized through the following technical solutions: A high-speed multi-concurrent programmable interlock protection device includes a main control unit and a first control and protection unit. Among them, the first control and protection unit includes a multi-channel interface configuration circuit, a high-speed optocoupler isolation circuit, and a logic transformation circuit connected in sequence. The logic transformation circuit consists of positive and negative logic control and logic gate circuits. The interface configuration circuit is connected to the signal input end, and the logic transformation circuit is signal-connected to the main control unit;

[0008] The master control unit includes: a programmable logic device circuit, an output signal driving module, and an MCU circuit. The output signal driving module and the MCU circuit are both connected to the programmable logic device circuit. The MCU circuit is responsible for communicating with the programmable logic device circuit to issue bypass, shielding settings, read the first fault signal, and the status of all channels. The output signal driving module is connected to the signal output terminal. Among them, the programmable logic device circuit meets the requirements of the required functions under the programming of the hardware description language program, so as to quickly lock the first signal of the fault generated in the case of multi-channel concurrent faults, latch the status of all channels where faults occur, and receive the bypass data and shielding data issued by the MCU circuit.

[0009] Further, the output signal driving module includes: a level conversion circuit, a device control circuit, an opto-isolation circuit, and a second interface configuration circuit. The programmable logic device circuit, the level conversion circuit, and the device control circuit are connected in sequence. The programmable logic device circuit, the opto-isolation circuit, and the second interface configuration circuit are connected in sequence.

[0010] Further, the output signal driving module further includes: a driving circuit and a relay circuit. The programmable logic device circuit, the driving circuit, and the relay circuit are connected in sequence.

[0011] Further, the first control and protection unit further includes a filter protection circuit. The filter protection circuit is connected between the interface configuration circuit and the signal input terminal.

[0012] According to a preferred embodiment, a second control and protection unit is further included. On the basis of the first control and protection unit, the second control and protection unit further includes a second programmable logic device circuit, a second opto-isolation circuit, and a second MCU circuit. The second opto-isolation circuit is connected to the output terminal of the second programmable logic device circuit. The logic transformation circuit in the second control and protection unit is connected to the input terminal of the second programmable logic device circuit. The second MCU circuit is connected to the second programmable logic device circuit.

[0013] Further, a plurality of the second control and protection units are provided. The plurality of second control and protection units are connected in series with each other, and output signals to one of the paths in the first control and protection unit through one of them;

[0014] The second MCU circuit is connected to the MCU circuit through a communication bus.

[0015] According to a preferred embodiment, the first control and protection unit further includes a third programmable logic device circuit, a third opto-isolation circuit, and a third MCU circuit. The third opto-isolation circuit is connected to the output end of the third programmable logic device circuit, the logic transformation circuit is connected to the input end of the third programmable logic device circuit, and the third MCU circuit is connected to the third programmable logic device circuit;

[0016] The main control unit further includes a third interface configuration circuit and a second high-speed opto-isolation circuit connected in series. The second high-speed opto-isolation circuit is connected to the programmable logic device circuit, and each third interface configuration circuit is respectively connected to a third opto-isolation circuit;

[0017] The third MCU circuit is connected to the MCU circuit through a communication bus.

[0018] Furthermore, third high-speed opto-isolation circuits are connected to the input ends of the programmable logic device circuit, the second programmable logic device circuit, and the third programmable logic device circuit, and the third high-speed opto-isolation circuit is connected to the second signal input end.

[0019] Furthermore, a second filter protection circuit is connected between the third high-speed opto-isolation circuit and the second signal input end.

[0020] Furthermore, a communication drive circuit is connected to the MCU circuit; indicator lights are connected to the MCU circuit, the second MCU circuit, and the third MCU circuit.

[0021] The technical solutions of the embodiments of the present invention have at least the following advantages and beneficial effects: (1) Both the control and protection unit and the main control unit have interface configuration circuits, which can be compatible with both level signals and interlock (on / off) signals at the same time; (2) The control and protection unit has a logic conversion circuit, which can control the positive and negative logic of the interlock channel, making the logic unified before entering the programmable logic device for processing, and being more efficient; (3) The input channels formed by the combination of the interface configuration circuit and the logic conversion circuit have consistency, and all channels can be applicable to different signals and different logics; (4) By using a programmable logic device circuit to replace the logic integrated circuit and programming through a hardware description language to complete the corresponding logic processing, compared with the logic integrated circuit, the processing is more flexible, the configuration is more convenient, and the function is more powerful. The programmable logic device has a high enough processing speed (up to more than 100 MHz), and can quickly lock the first signal generating a fault in the case of multi-channel concurrency, and latch the states of all channels generating faults; through communication with the MCU, the first fault signal and the states of all channels can be transmitted to the MCU, and bypass data (bypassing the corresponding channel so that its corresponding channel no longer participates in the interlock protection) and masking data (masking the corresponding channel so that its corresponding channel does not appear in the system, that is, the channel indicator light, the transmitted communication data, etc. no longer have this channel) issued by the MCU can be received; (5) The MCU does not directly perform state detection, but reads the state data from the programmable logic device and uploads it, with higher efficiency; by controlling the indicator light to display the channel state, it is more intuitive; (6) The interlock protection response time of the programmable logic device can be controlled within 50 ns, and the interlock protection response time of the control and protection unit can be controlled within 100 ns; (7) In the parallel control and protection module, each first control and protection unit can realize the input of N interlock channels, and at most M first control and protection units can be combined with one main control unit to form a control and protection module, so each control and protection module can realize the input of M*N interlock channels at most; in the series control and protection module, the number of second control and protection units can be serially connected without limit; this solution is easier to expand and convenient to use in a multi-channel interlock system. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a circuit schematic diagram of a high-speed multi-concurrency programmable interlock protection device provided by Embodiment 1 of the present invention;

[0023] Figure 2 It is a circuit schematic diagram of the second control and protection unit provided by Embodiment 2 of the present invention;

[0024] Figure 3 It is a circuit schematic diagram of a high-speed multi-concurrency programmable interlock protection device provided by Embodiment 2 of the present invention;

[0025] Figure 4 It is a circuit schematic diagram of a high-speed multi-concurrency programmable interlock protection device provided by Embodiment 3 of the present invention;

[0026] Figure 5 It is a block diagram of an interlock protection device that is currently used more frequently. Specific embodiments

[0027] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Usually, the components of the embodiments of the present invention described and illustrated herein can be arranged and designed in various different configurations.

[0028] Embodiment 1

[0029] Refer to Figure 1 as shown Figure 1 It is a circuit schematic diagram of a high-speed multi-concurrency programmable interlock protection device provided by Embodiment 1 of the present invention.

[0030] After research by the applicant, it is found that for the interlock protection devices that are currently used more frequently, such as Figure 5 the block diagram of an interlock protection device that is currently used more frequently as shown. It has at least the following several defects during use: First, the input signals of the interlock protection device can basically be divided into two types: level signals and interlock (on-off) signals. Without an interface configuration circuit, only one of the signals can be input fixedly, and the input channels cannot be adjusted and converted arbitrarily; Second, after the input signal passes through the optocoupler isolation circuit, it directly enters the logic integrated circuit for processing. Without a logic transformation circuit, the optocoupler isolation circuit can only output a fixed logic. For example, some channels are positive logic (high level is normal), and some channels are negative logic (low level is normal), and the logics are not unified, which is not convenient for the processing of the logic integrated circuit; Third, the logic integrated circuit can only process the input signals of all channels into one or several control signals according to a fixed logic, and cannot conveniently change the logic processing process; Fourth, after the input signal passes through the optocoupler isolation circuit, it directly enters the MCU circuit to detect the channel state. Limited by the devices and programs, the MCU cannot identify the sequence of changes in the states of multiple channels with close time, and cannot determine which channel is the first signal that causes the fault. Therefore, the present application provides a high-speed multi-concurrency programmable interlock protection device, specifically as follows:

[0031] It includes a main control unit and a first control and protection unit. Among them, the first control and protection unit includes a multi-channel interface configuration circuit, a high-speed optocoupler isolation circuit, and a logic transformation circuit connected in sequence. The logic transformation circuit is composed of positive and negative logic control and logic gate circuits. The interface configuration circuit is connected to the signal input end; the logic transformation circuit is signal-connected to the main control unit.

[0032] Specifically, the processing flow of the interlock signal is as follows: The input signal of the interlock channel passes through the filter protection circuit, interface configuration circuit, high-speed optocoupler isolation circuit, and logic conversion circuit in sequence and then enters the main control unit. It should be noted that the input signals at the signal input end of the interlock protection device can basically be divided into two types: level signals and interlock (on / off) signals; in this embodiment, by setting the interface configuration circuit, both types of signals can be input, and it can also support the random adjustment and conversion of input channels. Among them, when the device is used in an interference-free environment, the filter protection circuit can be omitted.

[0033] Regarding the functions and structures of the filter protection circuit, interface configuration circuit, high-speed optocoupler isolation circuit, and logic conversion circuit, the following is a specific description. Specifically: Filter protection circuit: It is mainly composed of filter devices and protection devices, and is used to filter out interference and stabilize signals and prevent impacts from damaging subsequent circuits. Interface configuration circuit: Uses methods such as configuration resistors or jumpers to be compatible with both level signals and interlock (on / off) signals simultaneously. High-speed optocoupler isolation circuit: Uses high-speed optocouplers to isolate external signals and subsequent processing circuits, which not only ensures the anti-interference ability and safety of the subsequent processing circuit but also ensures the processing speed of the interlock signal. Logic conversion circuit: It is mainly composed of positive and negative logic controls and logic gate circuits, and is used to control the positive and negative logics of the interlock channel. For example, for some channels, the positive logic (high level is normal), and for some channels, the negative logic (low level is normal). This circuit can be used to unify their logics. The positive and negative logic controls can be implemented using methods such as pull-up and pull-down resistors, jumpers, or DIP switches, and the logic gates can be implemented using chips such as exclusive-OR gates, AND gates, and OR gates.

[0034] It should be noted that compared with the commonly used interlock protection devices in the prior art, the interlock protection device provided by the present invention can be compatible with both level signals and interlock (on / off) signals simultaneously through the set interface configuration circuit; it can control the positive and negative logics of the interlock channel, unify the logics before entering the programmable logic device for processing, and the input channels formed by the combination of the interface configuration circuit and the logic conversion circuit have consistency, and all channels can be applicable to different signals and different logics.

[0035] Specifically, in one embodiment, the master control unit includes: a programmable logic device circuit, an output signal driving module, and an MCU circuit. The output signal driving module and the MCU circuit are both connected to the programmable logic device circuit. The output signal driving module is connected to the signal output terminal. The MCU circuit does not directly perform status detection, but reads status data from the programmable logic device and uploads it, which has obvious improvements in terms of function division and efficiency. The MCU circuit is responsible for communicating with the programmable logic device circuit to send down bypass, shielding settings, read the first fault signal, and all channel statuses. Among them, the programmable logic device circuit completes the requirements of the required functions under the programming of the hardware description language program. The programmable logic device has a high enough processing speed (up to more than 100 MHz) to quickly lock the first signal generating the fault in the case of multi-channel concurrent faults and latch the statuses of all channels generating faults, and receive the bypass data sent down by the MCU circuit (bypass the corresponding channel so that its corresponding channel no longer participates in the interlock protection) and shielding data (shield the corresponding channel so that its corresponding channel does not appear in the system, that is, the channel indicator light, transmitted communication data, etc. no longer have this channel).

[0036] Further, the input end of the programmable logic device circuit is also connected with a third high-speed optocoupler isolation circuit, and the third high-speed optocoupler isolation circuit is connected to the second signal input terminal; the input signal of the second signal input terminal is a reset signal, which is used for the restoration operation after the interlock protection device performs the protection action; a second filter protection circuit is connected between the third high-speed optocoupler isolation circuit and the second signal input terminal.

[0037] Further, in one embodiment, the output signal driving module includes: a level conversion circuit, a device control circuit, an optocoupler isolation circuit, and a second interface configuration circuit. The programmable logic device circuit, the level conversion circuit, and the device control circuit are sequentially connected. The device control circuit is connected to the first signal output terminal to output a control signal. The programmable logic device circuit, the optocoupler isolation circuit, and the second interface configuration circuit are sequentially connected. The second interface configuration circuit is connected to the second signal output terminal to output a fast interlock / level signal. The output signal driving module further includes: a driving circuit and a relay circuit. The programmable logic device circuit, the driving circuit, and the relay circuit are sequentially connected. The relay circuit is connected to the third signal output terminal to output a slow interlock signal. It should be noted that after the input signal is processed by the hardware description language program of the programmable logic device circuit, multiple device control signals, multiple fast interlock / level signals, and multiple slow interlock signals can be output (the corresponding interfaces can be configured according to requirements).

[0038] It should be noted that in the embodiments of the present invention, a programmable logic device circuit is used to replace the logic integrated circuit, and the corresponding logic processing is completed through programming in a hardware description language. Compared with the logic integrated circuit, the processing is more flexible, the configuration is more convenient, and the function is more powerful.

[0039] Furthermore, in one implementation, the MCU circuit is connected to communication driver circuits such as PHY driver, CAN driver, and RS485 driver, status lights, working lights, and fault indicator lights. Among them, the PHY driver circuit is connected to the RJ45 network port, the CAN driver circuit is connected to the CAN communication interface, and the RS485 driver circuit is connected to the RS485 communication interface. By controlling the indicator lights to display the channel status, it is more intuitive.

[0040] Embodiment 2

[0041] Refer to Figure 2 and Figure 3 as shown Figure 2 is the circuit schematic diagram of the second control and protection unit provided by the embodiments of the present invention; Figure 3 is the circuit schematic diagram of a high-speed multi-concurrent programmable interlocking protection device provided by the embodiments of the present invention.

[0042] It should be noted that the interlocking protection device of the prior art solution is not conducive to expansion. If the current number of interlocking input signals exceeds the designed number, it needs to be redesigned and cannot be directly expanded and used on the original basis. Therefore, this embodiment provides another implementation solution of a high-speed multi-concurrent programmable interlocking protection device, which is specifically as follows:

[0043] Different from the above embodiments, in this embodiment, a series-connected control and protection module is provided, which further includes a second control and protection unit on the basis of the solution provided in Embodiment 1. The circuit structure of the second control and protection unit refers to Figure 2 as shown. On the basis of the first control and protection unit, the second control and protection unit further includes a second programmable logic device circuit, a second opto-isolation circuit, and a second MCU circuit; specifically, the second opto-isolation circuit is connected to the output end of the second programmable logic device circuit, the logic transformation circuit in the second control and protection unit is connected to the input end of the second programmable logic device circuit, the second MCU circuit is connected to the second programmable logic device circuit, and the second MCU circuit is responsible for communicating with the second programmable logic device circuit to issue bypass, shielding settings, read the first fault signal, and all channel statuses, and also realizes functions such as communicating with the main control unit and controlling the status indicator lights.

[0044] In an implementation manner of this embodiment, a plurality of second control and protection units are provided. The plurality of second control and protection units are connected in series with each other, and output signals to one of the paths in the first control and protection unit through one of them; the second MCU circuit is connected to the MCU circuit through a communication bus (such as an Ethernet port, CAN, RS485, etc.). The MCU circuit communicates with the second MCU circuits of each second control and protection unit through a communication bus (such as an Ethernet port, CAN, RS485, etc.) to obtain the first fault signals and channel states of each second control and protection unit, and issue bypass and shielding settings; obtain the first fault signals and channel states from the programmable logic device of this unit, and issue bypass and shielding settings; communicate with the host computer through communication methods such as Ethernet port, CAN or RS485, upload the first fault signals and channel states, and obtain bypass and shielding settings.

[0045] In the series-connected control and protection module, the second control and protection units are connected in series level by level, and only the output of one second control and protection unit is connected to the main control unit. It should be noted that the number of second control and protection units can be connected in series without limit, but for the Nth second control and protection unit connected in series, the interlock protection response time is N + 1 times.

[0046] Embodiment 3

[0047] Refer to Figure 4 as shown Figure 4 which is a circuit schematic diagram of a high-speed multi-concurrency programmable interlock protection device provided by Embodiment 3 of the present invention.

[0048] Different from the series-connected control and protection module provided in Embodiment 2, this embodiment provides a parallel-connected control and protection module, which is similar to the series-connected type provided in Embodiment 2, except that the second control and protection units are no longer connected in series level by level, but all outputs are connected to the main control unit (the first control and protection unit in this embodiment). The specific solution is as follows:

[0049] This embodiment is different from the solution provided in Embodiment 2. On the basis of Embodiment 1, the first control and protection unit further includes a third programmable logic device circuit, a third opto-isolation circuit, and a third MCU circuit. The third opto-isolation circuit is connected to the output end of the third programmable logic device circuit, the logic transformation circuit is connected to the input end of the third programmable logic device circuit, and the third MCU circuit is connected to the third programmable logic device circuit. The main control unit further includes a plurality of third interface configuration circuits connected in sequence and a second high-speed opto-isolation circuit. The second high-speed opto-isolation circuit is connected to the programmable logic device circuit.

[0050] It should be noted that the circuit structure of the first control and protection unit in this embodiment is the same as that of the second control and protection unit provided in Embodiment 2. However, the third opto-isolation circuit in the first control and protection unit of this embodiment is respectively connected to the third interface configuration circuit of each path of the main control unit. The third MCU circuit is connected to the MCU circuit through a communication bus (such as an Ethernet port, CAN, RS485, etc.).

[0051] Each first control and protection unit outputs a fast interlock signal passing through the third opto-isolation circuit into the main control unit. After passing through the third interface configuration circuit and the second high-speed opto-isolation circuit, it enters the programmable logic device circuit in the main control unit. After being processed by the hardware description language program of the programmable logic device circuit, multiple device control signals, multiple fast interlock / level signals, and multiple slow interlock signals (corresponding interfaces can be configured according to requirements) are output. In this embodiment, the interlock protection response time of the programmable logic device can be controlled within 50 ns, and the interlock protection response time of the first control and protection unit can be controlled within 100 ns.

[0052] In summary, the interlock protection device provided by the present invention has at least the following advantages: (1) Both the control protection unit and the main control unit are equipped with interface configuration circuits, which can be compatible with both level signals and interlock (on-off) signals; (2) The control protection unit has a logic conversion circuit, which can control the positive and negative logic of the interlock channel, making the logic unified before entering the programmable logic device for processing, which is more efficient; (3) The input channels formed by the combination of the interface configuration circuit and the logic conversion circuit are consistent, and all channels can be applicable to different signals and different logics; (4) By using a programmable logic device circuit instead of a logic integrated circuit, the corresponding logic processing is completed through hardware description language programming. Compared with the logic integrated circuit, it is more flexible in processing, more convenient in configuration, and more powerful in function. The programmable logic device has a high enough processing speed (up to more than 100 MHz), and can quickly lock the first signal that generates a fault in the case of multi-channel concurrency, and latch the states of all channels that generate faults; through communication with the MCU, the first fault signal and the states of all channels can be transmitted to the MCU, and bypass data (bypassing the corresponding channel so that its corresponding channel no longer participates in the interlock protection) and masking data (masking the corresponding channel so that its corresponding channel does not appear in the system, that is, the channel indicator light, the transmitted communication data, etc. no longer have this channel) sent by the MCU can be received; (5) The MCU does not directly perform status detection, but reads the status data from the programmable logic device and uploads it, which is more efficient; by controlling the indicator light to display the channel status, it is more intuitive; (6) The interlock protection response time of the programmable logic device can be controlled within 50 ns, and the interlock protection response time of the control protection unit can be controlled within 100 ns; (7) In the parallel control protection module, each first control protection unit can realize the input of N interlock channels. One main control unit can be combined with at most M first control protection units to form a control protection module. Then, each control protection module can realize the input of M*N interlock channels at most, and the response time of each interlock channel is twice; in the series control protection module, the number of second control protection units can be serially connected without limit, but for the Nth second control protection unit in series, the interlock protection response time is N + 1 times; this solution is more easily expandable and convenient to use in a multi-channel interlock system.

[0053] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A high-speed multi-concurrency programmable interlocking protection device, characterized in that, It includes a main control unit and a first control and protection unit. Among them, the first control and protection unit includes a multi-channel sequentially connected interface configuration circuit, a high-speed optocoupler isolation circuit, and a logic conversion circuit. The logic conversion circuit consists of positive and negative logic control and logic gate circuits. The interface configuration circuit is connected to the signal input terminal, and the logic conversion circuit is signal-connected to the main control unit; The main control unit includes: a programmable logic device circuit, an output signal driving module, and an MCU circuit. Both the output signal driving module and the MCU circuit are connected to the programmable logic device circuit. The MCU circuit is responsible for communicating with the programmable logic device circuit to issue bypass, shielding settings, read the first fault signal, and the status of all channels. The output signal driving module is connected to the signal output terminal. Among them, the programmable logic device circuit meets the requirements of the required functions under the programming of the hardware description language program. The processing speed of the programmable logic device circuit is greater than 100 MHz, so as to quickly lock the first signal of the fault generated in the case of multi-channel concurrent faults, and latch the status of all channels where faults occur, and receive the bypass data and shielding data issued by the MCU circuit.

2. The high-speed multi-concurrency programmable interlock protection device according to claim 1, wherein The output signal driving module includes: a level conversion circuit, a device control circuit, an optocoupler isolation circuit, and a second interface configuration circuit. The programmable logic device circuit, the level conversion circuit, and the device control circuit are sequentially connected. The programmable logic device circuit, the optocoupler isolation circuit, and the second interface configuration circuit are sequentially connected.

3. The high-speed multi-concurrency programmable interlock protection device according to claim 2, characterized in that The output signal driving module further includes: a driving circuit and a relay circuit. The programmable logic device circuit, the driving circuit, and the relay circuit are sequentially connected.

4. The high-speed multi-concurrency programmable interlock protection device according to claim 3, characterized in that, The first control and protection unit further includes a filtering and protection circuit, and the filtering and protection circuit is connected between the interface configuration circuit and the signal input terminal.

5. The high-speed multi-concurrency programmable interlock protection device according to claim 4, characterized in that It further includes a second control and protection unit. On the basis of the first control and protection unit, the second control and protection unit further includes a second programmable logic device circuit, a second optocoupler isolation circuit, and a second MCU circuit. The second optocoupler isolation circuit is connected to the output terminal of the second programmable logic device circuit. The logic conversion circuit in the second control and protection unit is connected to the input terminal of the second programmable logic device circuit. The second MCU circuit is connected to the second programmable logic device circuit.

6. The high-speed multi-concurrency programmable interlock protection device according to claim 5, characterized in that, There are multiple second control and protection units. The multiple second control and protection units are connected in series with each other, and output signals to one of the paths in the first control and protection unit through one of them; The second MCU circuit is connected to the MCU circuit through a communication bus.

7. The high-speed multi-concurrency programmable interlock protection device according to claim 4, characterized in that The first control and protection unit further includes a third programmable logic device circuit, a third optocoupler isolation circuit, and a third MCU circuit. The third optocoupler isolation circuit is connected to the output terminal of the third programmable logic device circuit. The logic conversion circuit is connected to the input terminal of the third programmable logic device circuit. The third MCU circuit is connected to the third programmable logic device circuit; The main control unit further includes a plurality of third interface configuration circuits and second high-speed optocoupler isolation circuits connected in sequence. The second high-speed optocoupler isolation circuit is connected to the programmable logic device circuit, and each of the third interface configuration circuits is respectively connected to a third optocoupler isolation circuit; The third MCU circuit is connected to the MCU circuit through a communication bus.

8. The high-speed multi-concurrency programmable interlock protection device according to any one of claims 6 to 7, characterized in that The input ends of the programmable logic device circuit, the second programmable logic device circuit and the third programmable logic device circuit are all connected with third high-speed optocoupler isolation circuits, and the third high-speed optocoupler isolation circuit is connected to the second signal input end.

9. The high-speed multi-concurrency programmable interlock protection device according to claim 8, characterized in that, A second filtering and protection circuit is connected between the third high-speed optocoupler isolation circuit and the second signal input end.

10. The high-speed multi-concurrency programmable interlock protection device according to claim 8, wherein The MCU circuit is connected with a communication drive circuit; the MCU circuit, the second MCU circuit and the third MCU circuit are all connected with indicator lights.

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