A new adder

Abstract

The application discloses a novel adder, which comprises: an input end of a first inverter as a first input end of the adder, an output end of the first inverter connected to a third input end of a first transmission gate, a first input end of the first transmission gate as the first input end of the adder, and a second input end of the first transmission gate as a second input end of the adder; an input end of a second inverter as the second input end of the adder, an output end of the second inverter connected to a second input end of a second transmission gate, a third input end of the second transmission gate as the first input end of the adder, a first input end of the second transmission gate connected to the third input end of the first transmission gate, and output ends of the first transmission gate and the second transmission gate both connected to an input end of a third inverter, and an output end of the third inverter connected to a third input end of a third transmission gate. The adder disclosed by the application has reduced power consumption and area and improved performance.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuit, in particular to a new type of adder. BACKGROUND

[0002] The adder is a device for generating the sum of numbers. The adder with input of addend and addend and output of sum and carry is a half adder. The adder with input of addend, addend and low bit carry and output of sum and carry is a full adder. The adder is commonly used as the arithmetic logic unit of computer to perform logical operation, shift and instruction call. In electronics, the adder is a digital circuit which can perform digital addition. The main adder is operated by binary. In electronic circuit, a large number of adders are used. The conventional adder has large quantity of MOS, large area and large power consumption. SUMMARY

[0003] The present application aims at overcoming the deficiencies of the prior art and provides a new type of adder which uses transmission gate to transmit high and low levels to reduce loss.

[0004] The object of the present application is achieved by the following technical solutions.

[0005] The novel adder comprises: an input end of a first inverter as a first input end of the adder, an output end of the first inverter connected to a third input end of a first transmission gate, a first input end of the first transmission gate as a first input end of the adder, and a second input end of the first transmission gate as a second input end of the adder; an input end of a second inverter as a second input end of the adder, an output end of the second inverter connected to a second input end of a second transmission gate, a third input end of the second transmission gate as a first input end of the adder, a first input end of the second transmission gate connected to the third input end of the first transmission gate, output ends of the first transmission gate and the second transmission gate both connected to an input end of a third inverter, an output end of the third inverter connected to a third input end of a third transmission gate, a first input end of the third transmission gate connected to the output end of the second transmission gate, a second input end of the third transmission gate as a third input end of the adder, an input end of a fourth inverter as the third input end of the adder, an output end of the fourth inverter connected to a second input end of a fourth transmission gate, a third input end of the fourth transmission gate connected to the output end of the second transmission gate, a first input end of the fourth transmission gate connected to the third input end of the third transmission gate, and output ends of the third transmission gate and the fourth transmission gate both as a first output end of the adder; a first input end of a fifth transmission gate connected to the output end of the second transmission gate, a second input end of the fifth transmission gate as a first input end of the adder, a third input end of the fifth transmission gate connected to the output end of the third inverter, a third input end of a sixth transmission gate connected to the output end of the second transmission gate, a second input end of the sixth transmission gate as a third input end of the adder, a first input end of the sixth transmission gate connected to a third input end of the fifth transmission gate, and output ends of the fifth transmission gate and the sixth transmission gate both as a second output end of the adder.

[0006] Preferably, the first inverter, the second inverter, the third inverter and the fourth inverter are of the same structure, each comprising a first field effect transistor and a second field effect transistor, the first field effect transistor being PMOS and the second field effect transistor being NMOS; a source of the first field effect transistor is connected to a first power supply end VDD, a gate of the first field effect transistor is connected to a gate of the second field effect transistor, the gate of the second field effect transistor being one of a first input end of the adder, a second input end of the adder, a third input end of the adder or connected to an output end of the second transmission gate; a drain of the first field effect transistor is connected to a drain of the second field effect transistor, and a source of the second field effect transistor is connected to a second power supply end VSS.

[0007] Preferably, the first transmission gate, the second transmission gate, the third transmission gate, the fourth transmission gate, the fifth transmission gate and the sixth transmission gate are of the same structure, each comprising a third field effect transistor and a fourth field effect transistor, the third field effect transistor being PMOS and the fourth field effect transistor being NMOS; a source of the third field effect transistor is connected to a source of the fourth field effect transistor, and a drain of the third field effect transistor is connected to a drain of the fourth field effect transistor.

[0008] Preferably, the new adder comprises 20 field effect transistors.

[0009] The present application has the following advantages over the prior art:

[0010] The present application combines the functions of inverters and transmission gates to realize the function of the adder according to the functional behavior of the adder. The adder of the present application has reduced power consumption, reduced area and improved performance. BRIEF DESCRIPTION OF DRAWINGS

[0011] The accompanying drawings, which form a part of this specification, are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification. The embodiments of the present application, illustrated in the drawings and herein described, are described in terms of the best mode for practicing the application. It should be understood that no limitation of the scope of the application is intended by the description of a specific embodiment.

[0012] Figure 1 is a logic diagram of the new adder of the present application.

[0013] Figure 2 is a circuit diagram of the new adder of the present application.

[0014] Figure 3 is a circuit diagram of a conventional adder.

[0015] Figure 4 is a truth table of the new adder of the present application. DETAILED DESCRIPTION

[0016] The present application will be further described by examples in conjunction with the accompanying drawings.

[0017] Figure 1 is a logic diagram of the new adder of the present application. Figure 2 is a circuit diagram of the new adder of the present application. As Figures 1-2As shown, a new adder includes: the input end of a first inverter INV1 as the first input end A of the adder, the output end of the first inverter INV1 connected to the third input end of a first transmission gate TG1, the first input end of the first transmission gate TG1 as the first input end A of the adder, and the second input end of the first transmission gate TG1 as the second input end B of the adder; the input end of a second inverter INV2 as the second input end B of the adder, the output end of the second inverter INV2 connected to the second input end of a second transmission gate TG2, the third input end of the second transmission gate TG2 as the first input end A of the adder, the first input end of the second transmission gate TG2 connected to the third input end of the first transmission gate TG1, the output ends of the first transmission gate TG1 and the second transmission gate TG2 both connected to the input end nc of a third inverter INV3, the output end ncn of the third inverter INV3 connected to the third input end of a third transmission gate TG3, the first input end of the third transmission gate TG3 connected to the output end nc of the second transmission gate TG2, the second input end of the third transmission gate TG3 as the third input end Ci of the adder, the input end of a fourth inverter INV4 as the third input end Ci of the adder, the output end of the fourth inverter INV4 connected to the second input end of a fourth transmission gate TG4, the third input end of the fourth transmission gate TG4 connected to the output end nc of the second transmission gate TG2, the first input end of the fourth transmission gate TG4 connected to the third input end of the third transmission gate TG3, and the output ends of the third transmission gate TG3 and the fourth transmission gate TG4 both as the first output end S of the adder; the first input end of a fifth transmission gate TG5 connected to the output end nc of the second transmission gate TG2, the second input end of the fifth transmission gate TG5 as the first input end A of the adder, the third input end of the fifth transmission gate TG5 connected to the output end ncn of the third inverter INV3, the third input end of a sixth transmission gate TG6 connected to the output end nc of the second transmission gate TG2, the second input end of the sixth transmission gate TG6 as the third input end Ci of the adder, the first input end of the sixth transmission gate TG6 connected to the third input end of the fifth transmission gate TG5, and the output ends of the fifth transmission gate TG5 and the sixth transmission gate TG6 both as the second output end Co of the adder.

[0018] In the embodiment, the first inverter INV1, the second inverter INV2, the third inverter INV3 and the fourth inverter INV4 have the same structure, each comprising a first field effect transistor Q1 and a second field effect transistor Q2, the first field effect transistor being PMOS and the second field effect transistor being NMOS; the source of the first field effect transistor Q1 is connected to a first power supply end VDD, the gate of the first field effect transistor Q1 is connected to the gate of the second field effect transistor Q2, the gate of the second field effect transistor Q2 is one of a first input end A of an adder, a second input end B of the adder, a third input end Ci of the adder or an output end connected to the second transmission gate TG2; the drain of the first field effect transistor Q1 is connected to the drain of the second field effect transistor Q2, and the source of the second field effect transistor Q2 is connected to a second power supply end VSS.

[0019] In the embodiment, the first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3, the fourth transmission gate TG4, the fifth transmission gate TG5 and the sixth transmission gate TG6 have the same structure, each comprising a third field effect transistor Q3 and a fourth field effect transistor Q4, the third field effect transistor being PMOS and the fourth field effect transistor being NMOS; the source of the third field effect transistor Q3 is connected to the source of the fourth field effect transistor Q4, and the drain of the third field effect transistor Q3 is connected to the drain of the fourth field effect transistor Q4.

[0020] In the embodiment, the adder comprises 20 field effect transistors. Figure 3 The circuit diagram of the conventional adder is shown in FIG. 1. Figure 3 As shown in FIG. 1, the number of MOSs of the conventional adder is 28 field effect transistors.

[0021] Figure 4 The truth table of the new adder of the application is shown in FIG. 2. The functional behavior of the adder is expressed in the truth table.

[0022] In summary, the new adder of the application has the same function as the conventional adder. The power is reduced and the area is decreased. The simulation results of the power consumption of the adder of the application and the conventional adder are shown in the following table.

[0023] The simulation results of the power consumption of the adder of the application and the conventional adder

[0024]

[0025] As can be seen from the above table, the power of the adder of the application is reduced by 46.37% compared with the power of the conventional adder.

[0026] In summary, the conventional adder has a structure of 28 MOSs, and the new adder of the application has only 20 MOSs. Since the area is proportional to the number of transistors, with the reduction of the number of transistors, the area is also reduced. The reduction of the area means the reduction of the chip cost. Since the power consumption is proportional to the number of transistors, with the reduction of the number of transistors, the power consumption is also reduced.

[0027] The above detailed description is merely exemplary in nature and is not intended to limit the application or the application thereof. Any variation of the described embodiments, or any other equivalent embodiments, which do not depart from the spirit of the application, are intended to be within the scope of the application.

Claims

1. A new adder characterized by, The input end of the first inverter is the first input end of the adder, the output end of the first inverter is connected to the third input end of the first transmission gate, the first input end of the first transmission gate is the first input end of the adder, and the second input end of the first transmission gate is the second input end of the adder. The input end of the second inverter is the second input end of the adder, the output end of the second inverter is connected to the second input end of the second transmission gate, the third input end of the second transmission gate is the first input end of the adder, and the first input end of the second transmission gate is connected to the third input end of the first transmission gate. The output ends of the first transmission gate and the second transmission gate are both connected to the input end of the third inverter, the output end of the third inverter is connected to the third input end of the third transmission gate, the first input end of the third transmission gate is connected to the output end of the second transmission gate, the second input end of the third transmission gate is the third input end of the adder, the input end of the fourth inverter is the third input end of the adder, the output end of the fourth inverter is connected to the second input end of the fourth transmission gate, the third input end of the fourth transmission gate is connected to the output end of the second transmission gate, the first input end of the fourth transmission gate is connected to the third input end of the third transmission gate, and the output ends of the third transmission gate and the fourth transmission gate are both the first output end of the adder. The first input end of the fifth transmission gate is connected to the output end of the second transmission gate, the second input end of the fifth transmission gate is the first input end of the adder, the third input end of the fifth transmission gate is connected to the output end of the third inverter, the third input end of the sixth transmission gate is connected to the output end of the second transmission gate, the second input end of the sixth transmission gate is the third input end of the adder, the first input end of the sixth transmission gate is connected to the third input end of the fifth transmission gate, and the output ends of the fifth transmission gate and the sixth transmission gate are both the second output end of the adder. The structures of the first inverter, the second inverter, the third inverter and the fourth inverter are the same, the first field effect tube is PMOS, and the second field effect tube is NMOS.

2. The new adder according to claim 1, characterized in that, The source of the first field effect tube is connected to the first power supply end VDD, the gate of the first field effect tube is connected to the gate of the second field effect tube, the gate of the second field effect tube is one of the first input end of the adder, the second input end of the adder, the third input end of the adder or the output end connected to the second transmission gate, the drain of the first field effect tube is connected to the drain of the second field effect tube, and the source of the second field effect tube is connected to the second power supply end VSS. The structures of the first transmission gate, the second transmission gate, the third transmission gate, the fourth transmission gate, the fifth transmission gate and the sixth transmission gate are the same, and each includes a third field effect tube and a fourth field effect tube, the third field effect tube is PMOS, and the fourth field effect tube is NMOS. The source of the third field effect tube is connected to the source of the fourth field effect tube, and the drain of the third field effect tube is connected to the drain of the fourth field effect tube.

3. The new adder according to claim 1, characterized in that, The novel adder includes 20 field effect tubes. ​ ​ 4. The new adder according to claim 1, characterized in that, ​

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