An input sampling method, circuit, memory, and electronic device

Abstract

This application discloses an input sampling method, circuit, memory, and electronic device. The method includes: acquiring a first pulse signal and a second pulse signal respectively; then, widening the pulse width of the first pulse signal to obtain a widened first pulse signal; then, based on the widened first pulse signal, masking invalid signals in the second pulse signal to obtain a signal to be sampled; finally, sampling the signal to be sampled based on a clock signal. In this way, invalid signals are masked before signal sampling, avoiding additional power consumption caused by sampling invalid signals; simultaneously, the pulse width of the signal is widened to avoid sampling failure.

Description

Technical Field

[0001] This application relates to the field of integrated circuits, and more particularly to an input sampling method, circuit, memory, and electronic device. Background Technology

[0002] With the development of electronic technology, DRAM (Dynamic Random Access Memory) has been widely used in various electronic systems. Because the C / A (Command / Address) data bus of a DRAM DIMM (Dual Inline Memory Module) is shared by multiple DRAMs, meaning that the C / A signals of multiple DRAMs share a single data bus, each DRAM may receive invalid C / A signals belonging to other DRAMs. Therefore, the DRAM needs to determine the validity of the received C / A signal based on the CS (Chip Select) signal.

[0003] However, DRAM samples all received C / A signals, thus including invalid C / A signals and causing unnecessary energy consumption. Furthermore, as DRAM operating frequencies increase, the pulse widths of the C / A and chip select signals become narrower, potentially leading to signal sampling failures. Summary of the Invention

[0004] In view of this, embodiments of this application provide an input sampling method and circuit that broadens and shields the signal before sampling. This prevents invalid signals from being sampled, thereby reducing energy consumption; at the same time, it broadens the pulse width of the signal, thereby reducing the possibility of signal sampling failure.

[0005] The technical solution of this application embodiment is implemented as follows:

[0006] This application provides an input sampling method, the method comprising:

[0007] The first pulse signal and the second pulse signal are acquired respectively;

[0008] The pulse width of the first pulse signal is widened to obtain the widened first pulse signal;

[0009] Based on the broadened first pulse signal, the invalid signal in the second pulse signal is masked to obtain the signal to be sampled;

[0010] The signal to be sampled is sampled based on the clock signal.

[0011] This application embodiment also provides an input sampling circuit, the circuit including: an acquisition unit, a widening unit, a shielding unit, and a sampling unit;

[0012] The first output terminal of the acquisition unit is connected to the input terminal of the widening unit;

[0013] The second output terminal of the acquisition unit and the output terminal of the widening unit are respectively connected to the first input terminal and the second input terminal of the shielding unit;

[0014] The output terminal of the shielding unit is connected to the data input terminal of the sampling unit;

[0015] The clock signal is connected to the control input terminal of the sampling unit;

[0016] in,

[0017] The acquisition unit is used to acquire the first pulse signal and the second pulse signal respectively;

[0018] The widening unit is used to widen the pulse width of the first pulse signal to obtain a widened first pulse signal.

[0019] The shielding unit is used to shield invalid signals in the second pulse signal based on the broadened first pulse signal to obtain the signal to be sampled;

[0020] The sampling unit is used to sample the signal to be sampled based on a clock signal.

[0021] This application also provides a memory, which includes at least the aforementioned input sampling circuit.

[0022] This application also provides an electronic device, which includes at least the aforementioned memory.

[0023] Therefore, the embodiments of this application provide an input sampling method, circuit, memory, and electronic device capable of acquiring a first pulse signal and a second pulse signal respectively; then, widening the pulse width of the first pulse signal to obtain a widened first pulse signal; subsequently, based on the widened first pulse signal, invalid signals in the second pulse signal are masked to obtain the signal to be sampled; finally, the signal to be sampled is sampled based on a clock signal. In this way, invalid signals are masked before signal sampling, avoiding additional power consumption caused by sampling invalid signals; simultaneously, the pulse width of the signal is widened to avoid sampling failure. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of an input sampling circuit provided in a related technical solution;

[0025] Figure 2 A schematic diagram of an input sampling circuit provided in an embodiment of this application. Figure 1 ;

[0026] Figure 3A A schematic diagram of the effect of an input sampling circuit provided in an embodiment of this application. Figure 1 ;

[0027] Figure 3B A schematic diagram of the effect of an input sampling circuit provided in an embodiment of this application. Figure 2 ;

[0028] Figure 4 A flowchart of an input sampling method provided in this application embodiment Figure 1 ;

[0029] Figure 5A A schematic diagram of the effect of an input sampling circuit provided in an embodiment of this application is shown in Figure 3.

[0030] Figure 5B A schematic diagram of the effect of an input sampling circuit provided in an embodiment of this application. Figure 4 ;

[0031] Figure 6 A schematic diagram of the effect of an input sampling circuit provided in an embodiment of this application is shown in Figure 5.

[0032] Figure 7 A flowchart of an input sampling method provided in this application embodiment Figure 2 ;

[0033] Figure 8 Flowchart 3 shows an input sampling method provided in this application embodiment;

[0034] Figure 9 A flowchart of an input sampling method provided in this application embodiment Figure 4 ;

[0035] Figure 10 A schematic diagram of an input sampling circuit provided in an embodiment of this application. Figure 2 ;

[0036] Figure 11 A schematic diagram of an input sampling circuit provided in this application embodiment is shown in Figure 3.

[0037] Figure 12 A schematic diagram of the structure of a memory provided in an embodiment of this application;

[0038] Figure 13 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0039] The following are explanations of some terms that appear in the embodiments of this application:

[0040] DRAM (Dynamic Random Access Memory): A type of semiconductor memory chip commonly used in RAM. It is a volatile memory, meaning that the information stored in it will be lost when power is off. DRAM works by using the amount of charge stored in a capacitor to represent whether a binary bit is 1 or 0.

[0041] DDR-DRAM (Double Data Rate - Dynamic Random Access Memory): DRAM that transmits data twice in one clock cycle, once during the rising phase and once during the falling phase of the clock, thus achieving a higher data transfer rate at the same bus frequency.

[0042] DRAM DIMM (Dual Inline Memory Module): A memory module with two slots, each transmitting signals independently, thus meeting the needs of transmitting more data signals.

[0043] Chip select signal: A signal used to select a specific integrated circuit chip. When multiple chips share the same bus, the chip select signal is used to determine which chip the data and address signals on the bus are transmitted to.

[0044] C / A signals: Command / Address signals, also known as control or address signals. Control signals are used to control computer signals. Address signals contain the address information to be read or written.

[0045] VREFCA signal: The reference voltage signal used for receiving control and address signals, which can effectively improve the signal-to-noise ratio of the system data bus.

[0046] Clock signal: A fixed-period square wave signal generated by the upstream clock generator. It is the reference basis for sequential logic in digital circuits and is used to determine when the state in the logic unit is updated.

[0047] Sampling: The process of measuring the sample value of an input signal and replacing the amplitude of the original input signal over a certain period of time with the sample value.

[0048] A latch is a logic element in digital circuits that has memory function. It is a storage unit circuit that is sensitive to pulse levels. It can change its state under the action of a specific input pulse level, control the input of data by level, and save the input state to the output.

[0049] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0050] In the current DRAM C / A input sampling system, the C / A signal and the clock signal enter the input sampling circuit through their respective receivers. Then, the C / A signal is sampled based on the clock signal, and the sampled C / A signal is output for subsequent logic operations.

[0051] Figure 1 This is a schematic diagram of the input sampling circuit in a current DRAM C / A input sampling system, as shown below. Figure 1 As shown, the input sampling circuit 10 includes: a C / A signal receiver 11, a clock signal receiver 12, and a sampling latch (i.e., C / A Latch) 13.

[0052] The C / A signal enters the input sampling circuit 10 through the C / A signal receiver 11. After receiving the C / A signal, the C / A signal receiver 11 outputs a synchronized C / A Input signal to the data input terminal (i.e., the D input terminal) of the sampling latch 13. The clock signal CKT / CKB enters the input sampling circuit through the clock signal receiver 12. After receiving the clock signal, the clock signal receiver 12 outputs a synchronized CKT / CKB Input signal to the control input terminal (i.e., the CK input terminal) of the sampling latch 13. The sampling latch 13 samples the C / A Input signal based on the CKT / CKB Input signal and then outputs the sampled C / A Output signal.

[0053] However, in DRAM DIMM designs, the C / A data bus is shared by multiple DRAMs. Each DRAM needs to determine the validity of a received C / A signal based on the chip select signal. In current C / A input sampling systems, the DRAM samples all received C / A signals. This results in invalid C / A signals being sampled, leading to unnecessary power consumption.

[0054] Figure 2 The input sampling circuit 20 is in Figure 1 A shielding unit 24 was added to the circuit, such as Figure 2 As shown, the input sampling circuit 20 includes: a chip select signal receiver 21, a C / A signal receiver 22, a clock signal receiver 23, a shielding unit 24, and a sampling latch (i.e., a C / A latch) 25.

[0055] The C / A signal enters the input sampling circuit through the C / A signal receiver 22. After receiving the C / A signal, the C / A signal receiver 22 outputs a synchronized C / A_1 signal to the second input terminal of the shielding unit 24. The CS_n signal (i.e., the chip select signal) enters the input sampling circuit through the chip select signal receiver 21. After receiving the chip select signal, the chip select signal receiver 21 outputs a synchronized CS_1 signal to the first input terminal of the shielding unit 24.

[0056] The shielding unit 24 performs logical operations on the received C / A_1 and CS_1 signals. The specific logical operation expression (1) is as follows:

[0057]

[0058] In expression (1), CS_1 represents the logical operation value of the CS_1 signal, C / A_1 represents the logical operation value of the C / A_1 signal, and C / A Input represents the logical operation value of the C / A Input signal output by the shielding unit 24; "+" represents the logical OR operation, and "" represents the logical NOT operation.

[0059] Then, the shielding unit 24 outputs the C / A Input signal to the data input terminal (i.e., the D input terminal) of the sampling latch 25. The clock signal CKT / CKB enters the input sampling circuit 20 through the clock signal receiver 23. After receiving the clock signal CKT / CKB, the clock signal receiver 23 outputs a synchronized CKT / CKB Input signal to the control input terminal (i.e., the CK input terminal) of the sampling latch 25. The sampling latch 25 samples the C / A Input signal based on the CKT / CKB Input signal and then outputs the sampled C / A Output signal.

[0060] In implementation, because a shielding unit 24 is added to the input sampling circuit 20, when the DRAM does not receive a chip select signal (i.e., the CS_n signal is 1), the shielding unit 24 will shield the C / A signal, making the C / A Input signal constant at 0. Thus, even if there is a C / A signal input outside the input sampling circuit 20 when no chip select signal is received, there is no data flipping inside the input sampling circuit 20, thereby saving power consumption.

[0061] It should be noted that since the chip select signal is usually a low-level active signal, the chip select signal is usually kept at 1. When the chip select signal changes to 0, it is a valid trigger signal. That is, when no chip select signal is received, the CS_n signal is 1. The C / A signal contains two signals with the same amplitude but opposite phase. When the two signals undergo data flipping, it is a valid trigger signal.

[0062] However, as DRAM operating frequencies continue to increase, the pulse widths of the C / A signal and the chip select signal (i.e., the CS_n signal) are continuously narrowing. In the aforementioned... Figure 2 In the input sampling circuit 20 shown, because the C / A signal and the CS_n signal follow different paths, the C / A signal may arrive earlier or later than the CS_n signal. Therefore, the C / A signal and the CS_n signal will skew, which may lead to sampling failure of the C / A signal. Figure 3A As shown in the Hold time violation diagram, insufficient hold time can lead to data flipping during sampling, resulting in inaccurate sampled data. Figure 3B As shown in the Setup time violation example, if the signal has not been successfully established at the time of sampling, it may still lead to the failure of C / A signal sampling.

[0063] Thus, due to the influence of offset, coupled with the effect of PVT (Process, Voltage, Temperature) variation, the pulse width of the C / A Input signal output by the shielding unit will narrow, potentially causing C / A sampling to fail. Therefore, how to widen the pulse width of the signal becomes a problem that needs to be solved.

[0064] Figure 4 This is an optional flowchart illustrating the input sampling method provided in the embodiments of this application, which will be combined with... Figure 4 The steps shown are explained.

[0065] S401, acquire the first pulse signal and the second pulse signal respectively.

[0066] In this embodiment of the application, the acquisition unit in the input sampling circuit will acquire the first pulse signal and the second pulse signal sent by the upper-level processing unit, respectively.

[0067] The first pulse signal can be a chip select signal; the second pulse signal can be a C / A signal, i.e., a control signal or an address signal. The chip select signal is typically active low; that is, the chip select signal receiver receives a 0 signal, indicating that the chip select signal has been acquired. The C / A signal contains two signals with the same amplitude but opposite phase, transmitted discretely as pulse signals. The C / A signal receiver receives a valid C / A signal when the C / A signal flips.

[0068] It's important to note that in DRAM DIMM designs, the C / A data bus is shared by multiple DRAMs. Therefore, the C / A signal received by the current DRAM might belong to another DRAM, making it invalid for that DRAM. Determining whether a C / A signal is valid or invalid depends on the chip select signal; the C / A signal is controlled by the chip select signal. Specifically, if the current DRAM receives both the C / A signal and the chip select signal simultaneously, then the C / A signal is valid.

[0069] S402. The pulse width of the first pulse signal is widened to obtain the widened first pulse signal.

[0070] In this embodiment, the widening unit in the input sampling circuit widens the pulse width of the first pulse signal to obtain a widened first pulse signal. Here, pulse width refers to the duration for which the pulse reaches its effective value; widening the pulse signal means extending the duration of the effective pulse value.

[0071] In this embodiment, when the first pulse signal to be widened is a chip select signal, since the chip select signal is active low, widening the pulse width requires pushing (delaying) the rising edge of the chip select signal, such as... Figure 5A The CS_A signal is shown; and / or, pull-in (advance) the falling edge of the chip select signal, as shown. Figure 5B The CS_B signal is shown below. This yields the widened chip select signal.

[0072] Figure 6 This is a schematic diagram illustrating the process of widening the chip select signal in an embodiment of this application, which will be combined with... Figure 6 The process of expanding the embodiments of this application will be described.

[0073] In this embodiment, the broadening unit can pass the first pulse signal through the delay unit to delay the first pulse signal, thereby obtaining a delayed first pulse signal. For example, Figure 6 The CS_2 signal in the input sampling circuit is the original CS_1 signal delayed. Simultaneously, the input sampling circuit can reduce the absolute delay of the first receiver used to receive the first pulse signal, or trigger the upper-level processing unit of the first receiver to send the first pulse signal to the first receiver in advance, thereby obtaining the advanced first pulse signal. For example, Figure 6 The CS_1 signal in the diagram is the original CS_1 signal after being advanced.

[0074] Then, the broadening unit can generate a broadened first pulse signal based on any two of the first pulse signal, the advanced first pulse signal, and the delayed first pulse signal. That is, the broadening unit can perform a first logical operation on the first pulse signal and the delayed first pulse signal; or, perform a first logical operation on the advanced first pulse signal and the first pulse signal; or, perform a first logical operation on the advanced first pulse signal and the delayed first pulse signal. In this way, the broadened first pulse signal is obtained. For example, Figure 6 The CS_3 signal is the broadened signal obtained by performing the first logic operation on the CS_1 and CS_2 signals.

[0075] It should be noted that the specific form of the first logic operation depends on the type of the first pulse signal. When the first pulse signal is a chip select signal, since the chip select signal is active low, the first logic operation is a logical AND operation. Figure 6 For example, for Figure 6 Performing a logical AND operation on the CS_1 and CS_2 signals yields the CS_3 signal. Specifically, the high-level region A of the CS_1 signal is a 1 signal. Performing a logical AND operation on this region with the corresponding 0 signal in the CS_1 signal results in the 0 signal in the corresponding region of the CS_3 signal. Similarly, the 1 signal in the high-level region B of the CS_2 signal, after a logical AND operation, results in the 0 signal in the corresponding region of the CS_3 signal. Thus, the falling edge of the CS_3 signal aligns with the falling edge of the CS_1 signal, and the rising edge of the CS_3 signal aligns with the rising edge of the CS_2 signal. This gives the CS_3 signal a wider pulse width compared to either the CS_1 or CS_2 signals, thereby widening the chip select signal pulse width.

[0076] If the first pulse signal is another type of signal, the first logical operation needs to be adjusted accordingly. For example, when the first pulse signal is active high, the first logical operation needs to be adjusted to a logical OR operation. No restrictions are imposed here.

[0077] Understandably, widening the pulse width of the chip select signal ensures that the pulse width of the chip select signal can still cover the pulse width of the C / A signal even when skew occurs between the chip select signal and the C / A signal. This avoids pulse width narrowing issues during subsequent processing, thus eliminating the risk of input sampling errors.

[0078] S403. Based on the broadened first pulse signal, the invalid signal in the second pulse signal is shielded to obtain the signal to be sampled.

[0079] In this embodiment, the shielding unit in the input sampling circuit will shield the invalid signal in the second pulse signal based on the broadened first pulse signal to obtain the signal to be sampled.

[0080] In this embodiment, the shielding unit can perform a second logical operation on the second pulse signal to obtain an intermediate signal of the second pulse signal; then, it performs a third logical operation on the broadened first pulse signal and the intermediate signal of the second pulse signal. In this way, the invalid signal in the second pulse signal is shielded, and the signal to be sampled is obtained.

[0081] It should be noted that the specific forms of the second and third logical operations are related to the types of the first and second pulse signals. When the first and second pulse signals are the chip select signal and the C / A signal, respectively, since the chip select signal is active low, the second logical operation is a logical NOT operation, and the third logical operation is a logical OR NOT operation. That is to say, the signal to be sampled, the broadened first pulse signal, and the second pulse signal satisfy the following logical operation expression (2):

[0082]

[0083] In expression (2), C / A Input represents the logical operation value of the signal to be sampled, CS_3 represents the logical operation value of the first pulse signal after widening, and C / A represents the logical operation value of the second pulse signal; "+" represents the logical OR operation, and "" represents the logical NOT operation.

[0084] Thus, when no chip select signal is received (i.e., CS_3 is 1), the value of C / A Input will always be 0, regardless of the value of C / A. This achieves the masking of invalid signals in the C / A signal based on the chip select signal.

[0085] If the first and second pulse signals are other types of signals, the second and third logical operations need to be adjusted accordingly. For example, when the first pulse signal is active high, the third logical operation needs to be adjusted to a logical AND operation. No restrictions are imposed here.

[0086] It should be noted that the pulse width of the signal to be sampled is related to the pulse widths of the broadened first pulse signal and the second pulse signal. When the first pulse signal and the second pulse signal are the chip select signal and the C / A signal, respectively, and satisfy the above logical operation formula (2), the pulse width of the signal to be sampled is the part where the pulse widths of the chip select signal and the C / A signal overlap. Therefore, when the pulse width of the chip select signal is broadened to be sufficient to cover the pulse width of the C / A signal, the signal to be sampled output by the shielding unit can maintain the same pulse width as the C / A signal. Figure 5A and Figure 5B The C / AInput signal can then maintain the same pulse width as the C / A signal. This ensures that subsequent input sampling is free from the risk of errors.

[0087] Understandably, if the C / A signal directly enters the sampling unit, the sampling unit will sample invalid signals in the C / A signal, resulting in unnecessary power consumption. Therefore, the shielding unit shields invalid signals in the C / A signal before it enters the sampling unit, thus preventing invalid signals from being sampled and saving power.

[0088] S404. Sample the signal to be sampled based on the clock signal.

[0089] In this embodiment of the application, the sampling unit in the input sampling circuit receives the signal to be sampled and the clock signal respectively, and then samples the signal to be sampled based on the clock signal.

[0090] In this embodiment, the sampling unit may include a C / A Latch (i.e., a sampling latch). The data input terminal (i.e., the D input terminal) and control input terminal (i.e., the CK input terminal) of the C / A Latch respectively receive the C / A Input signal (i.e., the signal to be sampled) and the CKT / CKB Input signal (i.e., the clock signal). When the C / A Latch detects that the clock signal has reached a specific rising edge or falling edge, it triggers the latching of the C / A Input signal, saving the level of the C / A Input signal at this time to the output C / AOutput signal, thereby completing the sampling of the signal to be sampled based on the clock signal.

[0091] It should be noted that since invalid signals in the C / A Input signal received by the C / A Latch have been masked, the sampling unit will not sample when the C / A signal acquired by the input sampling circuit is invalid; that is, no data toggling will occur inside the C / A Latch. This saves power consumption.

[0092] In some embodiments of this application, it can be achieved through Figure 7 The above is achieved by S701 to S702 shown. Figure 4 The S402 shown will be explained in conjunction with each step.

[0093] S701. Delay the first pulse signal to obtain the delayed first pulse signal.

[0094] In this embodiment, the widening unit in the input sampling circuit includes a delay unit. The delay unit can delay the first pulse signal, postponing the pulse of the first pulse signal on the time axis to obtain and output the delayed first pulse signal.

[0095] S702, Perform a first logical operation on the first pulse signal and the delayed first pulse signal to generate a broadened first pulse signal; the first logical operation is a logical AND operation.

[0096] In this embodiment, the widening unit in the input sampling circuit further includes a first logic unit. The first logic unit receives the first pulse signal and the delayed first pulse signal, performs a first logic operation on these signals to generate the widened first pulse signal.

[0097] It should be noted that the specific form of the first logic operation depends on the type of the first pulse signal. When the first pulse signal is a low-level active chip select signal, the first logic operation is a logical AND operation. However, if the first pulse signal is another type of signal, the first logic operation needs to be adjusted accordingly, but this is not restricted here.

[0098] In some embodiments of this application, it can be achieved through Figure 8 The above is achieved by S801 to S803 shown. Figure 4 The S402 shown will be explained in conjunction with each step.

[0099] S801. Delay the first pulse signal to obtain the delayed first pulse signal.

[0100] In this embodiment, the widening unit in the input sampling circuit includes a delay unit. The delay unit can delay the first pulse signal, postponing the pulse of the first pulse signal on the time axis to obtain and output the delayed first pulse signal.

[0101] S802, advance the first pulse signal to obtain the advanced first pulse signal.

[0102] In this embodiment of the application, the input sampling circuit can advance the first pulse signal by advancing the pulse of the first pulse signal on the time axis, so as to obtain and output the advanced first pulse signal.

[0103] S803. Perform a first logic operation on the first pulse signal after the advance and the first pulse signal after the delay to generate the widened first pulse signal.

[0104] In this embodiment, the widening unit in the input sampling circuit further includes a first logic unit. The first logic unit receives the advanced first pulse signal and the delayed first pulse signal, performs a first logic operation on these signals to generate the widened first pulse signal.

[0105] It should be noted that the specific form of the first logic operation depends on the type of the first pulse signal. When the first pulse signal is a low-level active chip select signal, the first logic operation is a logical AND operation. However, if the first pulse signal is another type of signal, the first logic operation needs to be adjusted accordingly, but this is not restricted here.

[0106] In some embodiments of this application, the above can be achieved through S8021-S8022. Figure 8 The S802 shown will be explained in conjunction with each step.

[0107] S8021. Reduce the absolute delay of the first receiver used to receive the first pulse signal to obtain the advanced first pulse signal.

[0108] In this embodiment of the application, the input sampling circuit can reduce the absolute delay of its own first receiver used to receive the first pulse signal in order to obtain the advanced first pulse signal.

[0109] It should be noted that the first receiver has an absolute delay due to its internal structure. This absolute delay can be reduced by changing its internal structure, thereby obtaining the advanced first pulse signal.

[0110] S8022, Trigger the upper-level processing unit of the first receiver to send the first pulse signal to the first receiver in advance, and obtain the advanced first pulse signal.

[0111] In this embodiment of the application, the input sampling circuit can trigger the upper-level processing unit of the first receiver to send the first pulse signal to the first receiver in advance, so as to obtain the first pulse signal after the advance.

[0112] It should be noted that the first pulse signal is sent by the upper-level processing unit. The first pulse signal can be sent in advance by adjusting the sending time of the upper-level processing unit.

[0113] In some embodiments of this application, it can be achieved through Figure 9 The S901-S902 shown implements the above. Figure 4 The S403 shown will be explained in conjunction with each step.

[0114] S901. Perform a second logic operation on the second pulse signal to obtain the intermediate signal of the second pulse signal; the second logic operation is a logical NOT operation.

[0115] In this embodiment, the shielding unit in the input sampling circuit includes a second logic unit. The second logic unit can perform a second logic operation on the second pulse signal to obtain and output an intermediate signal of the second pulse signal.

[0116] S902. Perform a third logical operation on the intermediate signal of the broadened first pulse signal and the second pulse signal to obtain the signal to be sampled; the third logical operation is a logical OR operation.

[0117] In this embodiment, the shielding unit in the input sampling circuit further includes a third logic unit. The third logic unit can receive the intermediate signal between the first pulse signal and the second pulse signal, and then perform a third logic operation on these signals to shield the invalid signal in the second pulse signal, thereby obtaining the signal to be sampled.

[0118] It should be noted that the specific forms of the second and third logical operations depend on the types of the first and second pulse signals. When the first and second pulse signals are a low-level active chip select signal and a C / A signal, respectively, the second logical operation is a logical NOT operation, and the third logical operation is a logical NOR operation. If the first and second pulse signals are other types of signals, the second and third logical operations need to be adjusted accordingly, but this is not restricted here.

[0119] Based on the aforementioned input sampling method, this application embodiment also provides an input sampling circuit, see [link to relevant documentation]. Figure 10 This illustrates a schematic diagram of an input sampling circuit 100 provided in an embodiment of this application. Figure 10 As shown, the input sampling circuit 100 includes: an acquisition unit 101, a widening unit 102, a shielding unit 103, and a sampling unit 104;

[0120] The first output terminal of the acquisition unit 101 is connected to the input terminal of the widening unit 102; the second output terminal of the acquisition unit 101 and the output terminal of the widening unit 102 are respectively connected to the first input terminal and the second input terminal of the shielding unit 103; the output terminal of the shielding unit 103 is connected to the data input terminal (i.e., the D input terminal) of the sampling unit 104; the clock signal is connected to the control input terminal (i.e., the CK input terminal) of the sampling unit 104.

[0121] The acquisition unit 101 is used to acquire a first pulse signal and a second pulse signal respectively; the widening unit 102 is used to widen the pulse width of the first pulse signal to obtain a widened first pulse signal; the shielding unit 103 is used to shield invalid signals in the second pulse signal based on the widened first pulse signal to obtain a signal to be sampled; and the sampling unit 104 is used to sample the signal to be sampled based on a clock signal.

[0122] In this embodiment of the application, the acquisition unit 101 can acquire a first pulse signal and a second pulse signal respectively. The first pulse signal is a chip select signal (i.e., the CS_n signal), and the second pulse signal is a C / A signal; the chip select signal is active low, and the C / A signal is controlled by the chip select signal.

[0123] Then, the widening unit 102 receives the first pulse signal (i.e., the CS_1 signal) output from the first output terminal of the acquisition unit 101; and widens the pulse width of the first pulse signal to obtain the widened first pulse signal (i.e., the CS_3 signal).

[0124] Then, the shielding unit 103 receives the broadened first pulse signal (i.e., CS_3 signal) output from the broadening unit 102 through the first input terminal, and receives the second pulse signal (i.e., CA_1 signal) output from the second output terminal of the acquisition unit 101 through the second input terminal; and then shields the invalid signal in the second pulse signal based on the broadened first pulse signal to obtain the signal to be sampled (i.e., CA_Input signal).

[0125] Finally, the sampling unit 104 receives the signal to be sampled (i.e., CA_Input signal) output by the shielding unit 103 through the data input terminal, and receives the clock signal (i.e. CKT / CKB signal) through the control input terminal; then it samples the signal to be sampled based on the clock signal to obtain and output the sampled signal (i.e., CA_Output signal).

[0126] In the input sampling circuit 100 of the above embodiment, the widening unit 102 includes: a delay unit 105 and a first logic unit 106; wherein, the first logic unit 106 can be an AND gate;

[0127] The first output terminal of the acquisition unit 101 is connected to the input terminal of the delay unit 105 and the first input terminal of the first logic unit 106, respectively; the output terminal of the first logic unit 106 and the second output terminal of the acquisition unit 101 are connected to the first input terminal and the second input terminal of the shielding unit 103, respectively.

[0128] The delay unit 105 is used to delay the first pulse signal to obtain a delayed first pulse signal; the first logic unit 106 is used to perform a first logic operation on the first pulse signal and the delayed first pulse signal to generate a broadened first pulse signal; the first logic operation can be a logical AND operation.

[0129] In this embodiment of the application, the delay unit 105 receives the first pulse signal (i.e., the CS_1 signal) output by the first output terminal of the acquisition unit 101; and then delays the first pulse signal to obtain the delayed first pulse signal (i.e., the CS_2 signal).

[0130] The first logic unit 106 receives the first pulse signal (i.e., CS_1 signal) output by the first output terminal of the acquisition unit 101 through the first input terminal, and receives the delayed first pulse signal (i.e., CS_2 signal) output by the delay unit 105 through the second input terminal; then performs a first logic operation on the first pulse signal and the delayed first pulse signal to generate the broadened first pulse signal (i.e., CS_3 signal).

[0131] It should be noted that the type of first logic unit 106 used depends on the type of the first pulse signal. When the first pulse signal is active low, such as... Figure 11 As shown, the first logic unit 106 is an AND gate, and the first logic operation is a logical AND operation. However, if the first pulse signal is another type of signal, the first logic unit 106 needs to be adjusted accordingly. For example, when the first pulse signal is active high, the first logic unit 106 needs to be adjusted to an OR gate. No restrictions are imposed here.

[0132] In the input sampling circuit 100 of the above embodiment, the shielding unit 103 includes: a second logic unit 107 and a third logic unit 108; the second logic unit 107 can be an NOT gate; the third logic unit 108 can be a NOR gate;

[0133] The output of the widening unit 102 is connected to the first input of the third logic unit 108; the second output of the acquisition unit 101 is connected to the input of the second logic unit 107; the output of the second logic unit 107 is connected to the second input of the third logic unit 108; and the output of the third logic unit 108 is connected to the data input of the sampling unit 104.

[0134] The second logic unit 107 is used to perform a second logic operation on the second pulse signal to obtain an intermediate signal of the second pulse signal; the second logic operation can be a logical NOT operation; the third logic unit 108 is used to perform a third logic operation on the broadened first pulse signal and the intermediate signal of the second pulse signal to obtain a signal to be sampled; the third logic operation can be a logical OR NOT operation.

[0135] In this embodiment of the application, the second logic unit 107 receives the second pulse signal (i.e., C / A_1 signal) output by the second output terminal of the acquisition unit 101; and then performs a logical NOT operation on the second pulse signal to obtain the intermediate signal of the second pulse signal.

[0136] The third logic unit 108 receives the broadened first pulse signal (i.e., the CS_3 signal) output by the output terminal of the broadening unit 102 through the first input terminal, and receives the intermediate signal output by the second logic unit 107 through the second input terminal; then performs a logical OR-NOT operation on the broadened first pulse signal and the intermediate signal to obtain the signal to be sampled.

[0137] It should be noted that the choice of which second logic unit 107 and third logic unit 108 to use depends on the type of the first pulse signal and the second pulse signal. When the first pulse signal is active low, such as Figure 11 As shown, the second logic unit 107 is a NOT gate, and the third logic unit 108 is a NOR gate. Correspondingly, the second logic operation is a logical NOT operation, and the third logic operation is a logical NOR operation. However, if the first pulse signal and the second pulse signal are other types of signals, the second logic unit 107 and the third logic unit 108 need to be adjusted accordingly. For example, when the first pulse signal is active high, the third logic unit 108 needs to be adjusted to an AND gate. This is not a restriction.

[0138] In the input sampling circuit 100 of the above embodiment, the acquisition unit 101 includes:

[0139] The first receiver 109 is used to acquire the first pulse signal; the output terminal of the first receiver 109 serves as the first output terminal of the acquisition unit 101.

[0140] The second receiver 110 is used to acquire the second pulse signal; the output terminal of the second receiver 110 serves as the second output terminal of the acquisition unit 101.

[0141] The third receiver 111 is used to acquire the clock signal and input the clock signal to the control input terminal of the sampling unit 104.

[0142] It should be noted that the first receiver 109 has an absolute delay, which can be reduced by changing its internal structure. By reducing the absolute delay of the first receiver 109, or by triggering the upstream processing unit of the first receiver 109 to send the first pulse signal to the first receiver 109 in advance, an advanced first pulse signal can be obtained. Then, the advanced first pulse signal can be input as the CS_1 signal to the widening unit 102. The widening unit 102 can then obtain a widened first pulse signal based on the advanced first pulse signal.

[0143] In the input sampling circuit 100 of the above embodiment, the sampling unit 104 includes a sampling latch 112; the output terminal of the shielding unit 103 is connected to the data input terminal (i.e., D input terminal) of the sampling latch 112; and the clock signal is connected to the control input terminal (i.e., CK input terminal) of the sampling latch.

[0144] In this embodiment, the data input terminal and control input terminal of the sampling latch 112 receive the C / AInput signal (i.e., the signal to be sampled) and the CKT / CKB Input signal (i.e., the clock signal), respectively. When the sampling latch 112 detects that the clock signal has reached a specific rising edge or falling edge, it triggers the latching of the C / A Input signal, saving the level of the C / A Input signal at this time to the output C / A Output signal, thereby completing the sampling of the signal to be sampled based on the clock signal.

[0145] It should be noted that the input sampling circuit 100 provided in this application embodiment is applied to a DRAM C / A input sampling system, but is not limited to this scope. This circuit design can be used for instruction acquisition in high-frequency systems and low-power systems.

[0146] It is understood that the design of the input sampling circuit 100 provided in this application embodiment optimizes the original low-power design, enabling the C / A input sampling system to maintain a sufficiently wide effective signal pulse at high frequencies, thereby increasing the reliability of the low-power design at high frequencies.

[0147] In some embodiments of this application, the original CS_1 signal is pulled in by reducing the absolute delay of the chip select signal receiver. Then, after a delay unit, the entire CS_1 pulse is postponed to the position of CS_2. Finally, an AND gate is used to perform a logical AND operation on the CS_1 and CS_2 signals to form the chip select signal CS_3, which is pulled in on the falling edge and pushed on the rising edge compared to the original CS_1.

[0148] The technical solution of this application embodiment pulls the CS chip select signal in and then pushes it with a delay on the rising edge. This ensures that even under the influence of PVT variation, the pulse width of the chip select signal can still cover the C / A signal throughout the entire cycle. Thus, the output of the shielding unit will not experience pulse width narrowing due to skew between the chip select signal and the C / A signal, thereby ensuring sufficient pulse width for the C / A signal at high frequencies and preventing errors in the next stage of input sampling. While solving the technical problem of pulse width narrowing, the embodiments of this application still retain the function of the chip select signal shielding the C / A signal of non-target DRAM, ensuring that the low-power design of the C / A input sampling system remains effective.

[0149] In another embodiment of this application, see [link to application]. Figure 12 This illustrates a schematic diagram of the structure of a memory provided in an embodiment of this application. Figure 12 As shown, the memory 120 includes at least the input sampling circuit 100 as described in any of the foregoing embodiments.

[0150] In this embodiment, the memory 120 may integrate an input sampling circuit 100, which can acquire a first pulse signal and a second pulse signal respectively; then, the pulse width of the first pulse signal is widened to obtain a widened first pulse signal; then, invalid signals in the second pulse signal are masked based on the widened first pulse signal to obtain the signal to be sampled; finally, the signal to be sampled is sampled based on the clock signal. In this way, invalid signals are masked before signal sampling, avoiding additional power consumption caused by sampling invalid signals; at the same time, the pulse width of the signal is widened to avoid sampling failure.

[0151] In another embodiment of this application, see [link to application]. Figure 13 This illustrates a structural schematic diagram of an electronic device 130 provided in an embodiment of this application. For example... Figure 13 As shown, the electronic device 130 includes at least the memory 120 described in the foregoing embodiments. By shielding invalid signals and widening the signal pulse width, invalid signals can be shielded before signal sampling, avoiding the extra power consumption caused by sampling invalid signals. At the same time, the pulse width of the signal is widened to avoid sampling failure.

[0152] It should be noted that, in this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0153] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this application can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined to obtain new method or device embodiments without conflict.

[0154] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. An input sampling method, characterized in that, The method includes: The first pulse signal and the second pulse signal are acquired respectively; The pulse width of the first pulse signal is widened to obtain the widened first pulse signal; Based on the broadened first pulse signal, the invalid signal in the second pulse signal is masked to obtain the signal to be sampled; The signal to be sampled is sampled based on the clock signal; The step of broadening the first pulse signal to obtain a broadened first pulse signal includes: The first pulse signal is delayed to obtain the delayed first pulse signal; A first logical operation is performed on the first pulse signal and the delayed first pulse signal to generate the broadened first pulse signal; the first logical operation is a logical AND operation.

2. The input sampling method according to claim 1, characterized in that, The step of broadening the first pulse signal to obtain the broadened first pulse signal further includes: The first pulse signal is advanced to obtain the advanced first pulse signal; The first logical operation is performed on the advanced first pulse signal and the delayed first pulse signal to generate the broadened first pulse signal.

3. The input sampling method according to claim 2, characterized in that, The step of advancing the first pulse signal to obtain the advanced first pulse signal includes: Reduce the absolute delay of the first receiver used to receive the first pulse signal to obtain the advanced first pulse signal; or, The upper-level processing unit of the first receiver is triggered to send the first pulse signal to the first receiver in advance, thereby obtaining the advanced first pulse signal.

4. The input sampling method according to any one of claims 1 to 3, characterized in that, The step of masking invalid signals in the second pulse signal based on the broadened first pulse signal to obtain the signal to be sampled includes: Perform a second logical operation on the second pulse signal to obtain an intermediate signal of the second pulse signal; the second logical operation is a logical NOT operation; A third logical operation is performed on the intermediate signal between the broadened first pulse signal and the second pulse signal to obtain the signal to be sampled; the third logical operation is a logical OR-NOT operation.

5. The input sampling method according to any one of claims 1 to 3, characterized in that, The first pulse signal is a chip select signal; The second pulse signal is a control signal or an address signal.

6. An input sampling circuit, characterized in that, The circuit includes: an acquisition unit, an expansion unit, a shielding unit, and a sampling unit; The first output terminal of the acquisition unit is connected to the input terminal of the widening unit; The second output terminal of the acquisition unit and the output terminal of the widening unit are respectively connected to the first input terminal and the second input terminal of the shielding unit; The output terminal of the shielding unit is connected to the data input terminal of the sampling unit; The clock signal is connected to the control input terminal of the sampling unit; in, The acquisition unit is used to acquire the first pulse signal and the second pulse signal respectively; The widening unit is used to widen the pulse width of the first pulse signal to obtain a widened first pulse signal. The shielding unit is used to shield invalid signals in the second pulse signal based on the broadened first pulse signal to obtain the signal to be sampled; The sampling unit is used to sample the signal to be sampled based on a clock signal.

7. The input sampling circuit according to claim 6, characterized in that, The widening unit includes: a delay unit and a first logic unit; the first logic unit is an AND gate; The first output terminal of the acquisition unit is connected to the input terminal of the widening unit, including: the first output terminal of the acquisition unit is respectively connected to the input terminal of the delay unit and the first input terminal of the first logic unit; The output terminal of the broadening unit and the second output terminal of the acquisition unit are respectively connected to the first input terminal and the second input terminal of the shielding unit, including: the output terminal of the first logic unit and the second output terminal of the acquisition unit are respectively connected to the first input terminal and the second input terminal of the shielding unit; in, The delay unit is used to delay the first pulse signal to obtain a delayed first pulse signal; The first logic unit is used to perform a first logic operation on the first pulse signal and the delayed first pulse signal to generate the broadened first pulse signal; the first logic operation is a logical AND operation.

8. The input sampling circuit according to claim 6, characterized in that, The shielding unit includes: a second logic unit and a third logic unit; the second logic unit is a NOT gate; the third logic unit is a NOR gate; The output terminal of the widening unit and the second output terminal of the acquisition unit are respectively connected to the first input terminal and the second input terminal of the shielding unit, and the system further includes: the output terminal of the widening unit is connected to the first input terminal of the third logic unit; the second output terminal of the acquisition unit is connected to the input terminal of the second logic unit; and the output terminal of the second logic unit is connected to the second input terminal of the third logic unit. The output terminal of the shielding unit is connected to the data input terminal of the sampling unit, including: the output terminal of the third logic unit is connected to the data input terminal of the sampling unit; in, The second logic unit is used to perform a second logic operation on the second pulse signal to obtain an intermediate signal of the second pulse signal; the second logic operation is a logical NOT operation; The third logic unit is used to perform a third logic operation on the intermediate signal between the broadened first pulse signal and the second pulse signal to obtain the signal to be sampled; the third logic operation is a logical OR operation.

9. The input sampling circuit according to claim 6, characterized in that, The acquisition unit includes: A first receiver is used to acquire the first pulse signal; the output terminal of the first receiver serves as the first output terminal of the acquisition unit. The second receiver is used to acquire the second pulse signal; the output terminal of the second receiver serves as the second output terminal of the acquisition unit.

10. The input sampling circuit according to claim 6, characterized in that, The sampling unit includes a sampling latch; The output terminal of the shielding unit is connected to the data input terminal of the sampling unit, including: the output terminal of the shielding unit is connected to the data input terminal of the sampling latch; The clock signal is connected to the control input terminal of the sampling unit, including: the clock signal is connected to the control input terminal of the sampling latch.

11. The input sampling circuit according to any one of claims 6 to 10, characterized in that, The first pulse signal is a chip select signal; The second pulse signal is a control signal or an address signal.

12. A memory, characterized in that, The memory includes at least the input sampling circuitry as described in any one of claims 6 to 11.

13. An electronic device, characterized in that, The electronic device includes at least the memory as described in claim 12.

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