An input sampling method, an input sampling circuit, and a semiconductor memory.

Abstract

This application provides an input sampling method, an input sampling circuit, and a semiconductor memory. The input sampling method includes: receiving a first pulse signal and a second pulse signal; performing logical operations on the first pulse signal and the second pulse signal to determine a signal to be sampled; wherein the signal to be sampled is obtained by masking invalid signals in the second pulse signal based on the result of the logical operation; and performing sampling processing on the signal to be sampled to obtain a target sampled signal. In this way, by performing logical operations on the first pulse signal and the second pulse signal, invalid signals in the second pulse signal can be masked, thus preventing the signal to be sampled from undergoing level state flips due to invalid signals in the first pulse signal, thereby reducing the functional loss of the input sampling circuit.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to an input sampling method, an input sampling circuit, and a semiconductor memory. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device in computers, consisting of many repeating memory cells. Currently, as DRAM is used in more and more fields, users have increasingly higher requirements for DRAM power consumption.

[0003] However, in current DRAM, invalid input signals can cause level state flips, leading to excessive power loss. Summary of the Invention

[0004] This application provides an input sampling method, an input sampling circuit, and a semiconductor memory, which can avoid level state flipping caused by invalid input signals, thereby reducing the functional loss of the data sampling circuit.

[0005] The technical solution of this application is implemented as follows:

[0006] In a first aspect, embodiments of this application provide an input sampling method, the method comprising:

[0007] Receive the first pulse signal and the second pulse signal;

[0008] Logical operations are performed on the first pulse signal and the second pulse signal to determine the signal to be sampled; wherein, the signal to be sampled is obtained by masking out invalid signals in the second pulse signal based on the result of the logical operation.

[0009] The signal to be sampled is processed to obtain the target sampled signal.

[0010] Secondly, embodiments of this application provide an input sampling circuit, which includes:

[0011] The first signal input terminal is used to receive the first pulse signal;

[0012] The second signal input terminal is used to receive the second pulse signal;

[0013] The logic unit performs logical operations on the first pulse signal and the second pulse signal to obtain the signal to be sampled; wherein, the signal to be sampled is obtained by masking out invalid signals in the second pulse signal based on the result of the logical operation.

[0014] The first sampling sub-circuit is used to sample the signal to be sampled to obtain the target sampled signal;

[0015] The logic unit has two input terminals connected to the first signal input terminal and the second signal input terminal, respectively, and its output terminal connected to the first sampling sub-circuit.

[0016] Thirdly, embodiments of this application provide a semiconductor memory, including the input sampling circuit as described in the second aspect.

[0017] This application provides an input sampling method, an input sampling circuit, and a semiconductor memory. The input sampling method includes: receiving a first pulse signal and a second pulse signal; performing logical operations on the first and second pulse signals to determine a signal to be sampled; wherein the signal to be sampled is obtained by masking invalid signals in the second pulse signal based on the logical operation result; and performing sampling processing on the signal to be sampled to obtain a target sampled signal. The input sampling circuit includes a first signal input terminal for receiving the first pulse signal; a second signal input terminal for receiving the second pulse signal; a logic operator for performing logical operations on the first and second pulse signals to obtain the signal to be sampled; wherein the signal to be sampled is obtained by masking invalid signals in the second pulse signal based on the logical operation result; and a first sampling sub-circuit for sampling the signal to be sampled to obtain the target sampled signal; wherein the two input terminals of the logic operator are respectively connected to the first and second signal input terminals, and the output terminal of the logic operator is connected to the first sampling sub-circuit. In this way, by performing logical operations on the first pulse signal and the second pulse signal, invalid signals in the second pulse signal can be shielded, so that the signal to be sampled will not flip its level state with the invalid signals in the first pulse signal, thereby reducing the functional loss of the input sampling circuit. Attached Figure Description

[0018] Figure 1 A schematic diagram of an input sampling circuit provided for related technologies;

[0019] Figure 2 A schematic diagram of signal variation in an input sampling circuit provided for related technologies;

[0020] Figure 3 A flowchart illustrating an input sampling method provided in an embodiment of this application;

[0021] Figure 4 This is a schematic diagram of an input sampling circuit provided in an embodiment of this application;

[0022] Figure 5 This is a schematic diagram of another input sampling circuit provided in an embodiment of this application;

[0023] Figure 6This is a schematic diagram of signal changes in an input sampling circuit provided in an embodiment of this application. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are merely for explaining the relevant application and not for limiting the application. Furthermore, it should be noted that, for ease of description, only the parts relevant to the application are shown in the accompanying drawings.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0026] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0027] It should be noted that the terms "first, second, and third" used in the embodiments of this application are only used to distinguish similar objects and do not represent a specific order of objects. It is understood that "first, second, and third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0028] The following are explanations of the technical terms used in the embodiments of this application and the correspondences of some terms:

[0029] Sampling: The amplitude of the input signal is measured at regular intervals to convert the time-continuous analog signal into a time-discrete, amplitude-continuous sampled signal.

[0030] DDR: Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM).

[0031] Command / Address input sampling system: also known as C / A input sampling system or input sampling circuit, it uses a standard clock signal to sample the C / A signal in order to facilitate instruction decoding.

[0032] DIMM (Dual Inline Memory Modules): Dual inline memory modules.

[0033] Decoder (DEC): A device code used for decoding processing.

[0034] A latch is a device that samples data at a certain time and holds the sampled result at the output.

[0035] The first pulse signal, also known as the CS_n signal, indicates the chip select (CS) signal, which is used to select whether the current device is the target device.

[0036] The second pulse signal, also known as the C / A signal, is used to indicate the Command / Address signal. The Command / Address signal is an input signal that contains information such as commands and addresses, and is used to control specific devices in the circuit.

[0037] Standard clock signal: A standard signal involved in signal processing, such as CKT signal or CKB signal;

[0038] The signal to be sampled, also known as the C / A Input signal, is used to indicate the signal after the first pulse signal and the second pulse signal have been processed.

[0039] Target sampling signal: also known as C / A output signal, used to indicate the signal obtained after the signal to be sampled has been sampled.

[0040] The first pulse signal after sampling: also known as the Cs_n Output signal, is used to indicate the signal obtained after sampling the first pulse signal.

[0041] Target signal: also known as CMD signal, is used to indicate the signal obtained after decoding the target sampled signal when the first pulse signal is valid.

[0042] Currently, in DRAM C / A input sampling systems, the C / A signal and the standard clock signal enter the input sampling circuit through receivers. The standard clock signal then samples the C / A signal, and a synchronized sampled C / A signal is output for subsequent instruction decoding. However, in DRAM DIMM designs, the C / A data bus is shared by multiple DRAMs, and the DRAM to which the C / A signal corresponds needs to be distinguished by a chip select signal.

[0043] In other words, a DRAM DIMM contains multiple DRAMs, each with its own corresponding input sampling circuit. For a specific DRAM's input sampling circuit, in addition to the C / A signal, the chip select signal also enters through the receiver and is sampled by the standard clock signal. Based on the chip select signal, it can be determined whether the C / A signal is a valid instruction for that DRAM; that is, it is necessary to determine whether the C / A signal is valid based on the chip select signal.

[0044] See Figure 1It shows a schematic diagram of an input sampling circuit 10 provided by related technologies. For example... Figure 1 As shown, the C / A signal and the standard clock signal (CKT signal / CKB signal) are sampled through the first latch 101 to obtain the C / A Output signal, and the CS_n signal and the standard clock signal are sampled through the second latch 102 to obtain the Cs_n Output signal. Then, the decoder 103 decodes the Cs_n Output signal according to the CS_n Output signal to finally obtain the CMD signal, which is then used to control the DRAM.

[0045] In other words, all received C / A signals are processed together with the CS chip select signal in the instruction decoding module. If the CS_n signal is 0, it means that the C / A signal is for this DRAM, so the C / A signal is decoded, and the instruction is successfully decoded, entering the subsequent execution process; if the CS_n signal is 1, it means that this DRAM is not the target DRAM, no instruction will be decoded, and no subsequent action will be taken.

[0046] However, even when the CS_n signal is 1 and the C / A signal is invalid for this DRAM, the input sampling circuit 10 will still sample the C / A signal. See Figure 2 It illustrates a schematic diagram of signal changes in an input sampling circuit provided by related technologies. For example... Figure 2 As shown by the dashed circle, even if the CS_n signal is 1 (this DRAM is not the target chip), the C / A Output signal will still change with the C / A signal. At this time, since the C / A signal is usually multi-bit and the C / A Output signal needs to change continuously with the C / A signal, a large amount of useless energy is consumed in the input sampling circuit.

[0047] Thus, for a DRAM DIMM containing multiple DRAMs, each specific DRAM will repeatedly sample the C / A signal, resulting in unnecessary energy consumption for many input sampling circuits.

[0048] Based on this, this application provides an input sampling method. The basic idea of ​​the method is as follows: the input sampling method includes: receiving a first pulse signal and a second pulse signal; performing logical operations on the first pulse signal and the second pulse signal to determine a signal to be sampled; wherein the signal to be sampled is obtained by masking invalid signals in the second pulse signal according to the result of the logical operation; and performing sampling processing on the signal to be sampled to obtain a target sampled signal. The input sampling circuit includes a first signal input terminal for receiving the first pulse signal; a second signal input terminal for receiving the second pulse signal; a logic operator for performing logical operations on the first pulse signal and the second pulse signal to obtain the signal to be sampled; wherein the signal to be sampled is obtained by masking invalid signals in the second pulse signal according to the result of the logical operation; and a first sampling sub-circuit for sampling the signal to be sampled to obtain the target sampled signal; wherein the two input terminals of the logic operator are respectively connected to the first signal input terminal and the second signal input terminal, and the output terminal of the logic operator is connected to the first sampling sub-circuit. In this way, by performing logical operations on the first pulse signal and the second pulse signal, invalid signals in the second pulse signal can be shielded, and the signal to be sampled will not undergo level state flipping with invalid input signals, thereby reducing the functional loss of the data sampling circuit.

[0049] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0050] In one embodiment of this application, see Figure 3 This illustrates a structural schematic diagram of an input sampling method provided in an embodiment of this application. Figure 3 As shown, the method may include:

[0051] S201: Receive the first pulse signal and the second pulse signal.

[0052] S202: Perform logical operations on the first pulse signal and the second pulse signal to determine the signal to be sampled.

[0053] It should be noted that the embodiments of this application are applied to the Command / Address input sampling system (i.e., input sampling circuit) in integrated circuits, such as the circuit system in a DRAM chip where a fixed clock CKT samples the C / A input.

[0054] For ease of explanation, the following description uses the C / A input sampling circuit of DRAM as an example to illustrate the embodiments of this application; however, this does not constitute a limitation on the embodiments of this application. The methods and circuits provided in the embodiments of this application can also be applied to any system involving instruction acquisition or low power consumption.

[0055] For the input sampling method, after receiving the first pulse signal and the second pulse signal, logical operations are performed on the first and second pulse signals to mask out invalid signals in the second pulse signal, ultimately obtaining the signal to be sampled. In other words, the signal to be sampled is obtained by masking out invalid signals in the second pulse signal based on the result of the logical operation.

[0056] Here, the first pulse signal can generally indicate whether the second pulse signal is valid, so a corresponding logic operation process can be designed to shield invalid signals in the second pulse signal.

[0057] Furthermore, in some embodiments, the method may further include:

[0058] If the result of the logical operation indicates that the second pulse signal is invalid, the level state of the signal to be sampled is determined to be masked to a preset value;

[0059] If the result of the logical operation indicates that the second pulse signal is valid, it is determined that the level state of the signal to be sampled is the same as that of the second pulse signal.

[0060] It should be noted that if the second pulse signal is invalid, the level of the signal to be sampled can be masked to a preset value; if the second pulse signal is valid, the level of the signal to be sampled must be the same as the level of the second pulse signal, so as to ensure that the valid signal in the second pulse signal can play a normal control role.

[0061] In this way, during the sampling process, the invalid signal of the second pulse signal is shielded to a preset value, so that the signal to be sampled will not flip its level state according to the invalid signal in the second pulse signal, thereby avoiding unnecessary energy loss.

[0062] Furthermore, in some embodiments, performing logical operations on the first pulse signal and the second pulse signal to determine the signal to be sampled may include:

[0063] Perform a logical NOT operation on the second pulse signal to obtain the processed second pulse signal;

[0064] The first pulse signal and the processed second pulse signal are subjected to a logical OR-NOT operation to obtain the signal to be sampled.

[0065] It should be noted that, in the embodiments of this application, the specific process of the logical operation is as follows: after receiving the first pulse signal and the second pulse signal, the second pulse signal is logically NOT processed to obtain the processed second pulse signal; then, the first pulse signal and the processed second pulse signal are ORed to obtain the signal to be sampled. It should be understood that the above is only one possible way of logical operation and does not constitute a limitation on the embodiments of this application.

[0066] The following explanation uses the input sampling circuit of DRAM as an example to illustrate the logic operation process.

[0067] In DRAM, the first pulse signal can be a chip select signal (Cs_n signal), and the second pulse signal can be a control signal or an address signal (C / A signal). According to DRAM industry standards, generally when the chip select signal is 0, the corresponding C / A signal is a valid signal; when the chip select signal is 1, the corresponding C / A signal is an invalid signal.

[0068] At this point, after receiving the chip select signal and the C / A signal, a NOT operation can be performed on the chip select signal to obtain the processed second pulse signal; a OR NOT operation can be performed on the C / A signal and the processed second pulse signal to obtain the signal to be sampled. Thus, when the chip select signal is 1, the signal to be sampled is always 0, meaning the signal to be sampled will not toggle with the C / A signal; when the chip select signal is 0, the level of the signal to be sampled will change following the first pulse signal.

[0069] Thus, for the logic operation process, when the chip select signal is high, the logic operation result can indicate that the second pulse signal is invalid; when the chip select signal is low, the logic operation result can indicate that the second pulse signal is valid.

[0070] In this way, the signal to be sampled will only be flipped along with the valid C / A signal, while the invalid C / A signal will be shielded, thus avoiding meaningless energy consumption.

[0071] S303: Perform sampling processing on the signal to be sampled to obtain the target sampled signal.

[0072] It should be noted that the signal to be sampled is processed to obtain the target sampled signal, which is then used to implement the subsequent control process.

[0073] Furthermore, in some embodiments, the sampling processing of the signal to be sampled to obtain the target sampled signal may include:

[0074] Receive standard clock signals;

[0075] The target sampled signal is obtained by sampling the signal to be sampled using a standard clock signal.

[0076] It should be noted that during the sampling process, a standard clock signal needs to be received. The standard clock signal is used to sample the signal to be sampled, and finally the target sampled signal is obtained.

[0077] Furthermore, in some embodiments, the method may further include:

[0078] The target sampled signal is decoded to obtain the target signal.

[0079] It should be noted that after obtaining the target sampling signal, it is necessary to decode the target sampling signal to obtain the target signal, which is specifically used to control the DRAM.

[0080] Specifically, in some embodiments, the decoding process of the target sampled signal to obtain the target signal may include:

[0081] The first pulse signal after sampling is determined; wherein, the first pulse signal after sampling is obtained by sampling the first pulse signal using a standard clock signal;

[0082] The target signal is obtained by decoding the target sampled signal based on the first pulse signal after sampling.

[0083] It should be noted that in the decoding process, the first pulse signal needs to be sampled using a standard clock signal to obtain the sampled first pulse signal; then, the target sampled signal is decoded based on the sampled first pulse signal to ensure the correctness of the decoding and finally obtain the target signal.

[0084] In summary, by utilizing the circuit design provided in the embodiments of this application, the input sampling circuit can reduce power consumption by shielding the sampling input when invalid C / A signals are continuously input.

[0085] This application provides an input sampling method, which includes: receiving a first pulse signal and a second pulse signal; performing logical operations on the first pulse signal and the second pulse signal to determine a signal to be sampled; wherein the signal to be sampled is obtained by masking invalid signals in the second pulse signal according to the result of the logical operation; and performing sampling processing on the signal to be sampled to obtain a target sampled signal. In this way, by performing logical operations on the first pulse signal and the second pulse signal, invalid signals in the second pulse signal can be masked, thus preventing the signal to be sampled from undergoing level state flips due to invalid signals in the first pulse signal, thereby reducing the functional loss of the input sampling circuit.

[0086] In another embodiment of this application, see Figure 4 This illustrates a schematic diagram of an input sampling circuit 30 provided in an embodiment of this application. Figure 4 As shown, the input sampling circuit 30 may include:

[0087] The first signal input terminal 301 is used to receive the first pulse signal;

[0088] The second signal input terminal 302 is used to receive the second pulse signal;

[0089] The logic unit 303 is used to perform logic operations on the first pulse signal and the second pulse signal to obtain the signal to be sampled; wherein, the signal to be sampled is obtained by masking the invalid signal in the second pulse signal according to the result of the logic operation.

[0090] The first sampling sub-circuit 304 is used to sample the signal to be sampled to obtain the target sampled signal.

[0091] It should be noted that this input sampling circuit is an integrated circuit, such as the Command / Address input sampling circuit of DRAM.

[0092] This application provides an input sampling circuit 30, which includes a first signal input terminal 301, a second signal input terminal 302, a logic unit 303, and a first sampling sub-circuit 304. The specific connection relationship of the above devices is as follows: the two input terminals of the logic unit 303 are respectively connected to the first signal input terminal 301 and the second signal input terminal 302, and the output terminal of the logic unit 303 is connected to the first sampling sub-circuit 304.

[0093] Here, signal input terminal 301 receives a first pulse signal and a second pulse signal; then, logic unit 303 performs logic operations on the first and second pulse signals to obtain the signal to be sampled; finally, the first sampling sub-circuit 304 samples the processed input signal to obtain the target sampled signal. In this way, since the signal to be sampled is obtained by masking invalid signals in the second pulse signal based on the logic operation result, the input sampling circuit can avoid meaningless level state switching, reducing DRAM power consumption.

[0094] Furthermore, in some embodiments, the logic unit 303 may include NOT gates and NOR gates; wherein,

[0095] The NOT gate is used to perform a logical NOT operation on the second pulse signal to obtain the processed second pulse signal.

[0096] The NOR gate is used to perform a logical OR-NOT operation on the first pulse signal and the processed second pulse signal to obtain the signal to be sampled.

[0097] It should be noted that the logic unit 303 includes NOT gates and NOR gates. The input terminal of the NOT gate is connected to the second signal input terminal, the first signal input terminal of the NOR gate is connected to the first signal input terminal, and the second signal input terminal of the NOR gate is connected to the output terminal of the NOT gate. In this way, by performing a NOT operation on the second pulse signal through the NOT gate, a processed second pulse signal can be obtained; then, by performing a NOR operation on the first pulse signal and the processed second pulse signal through the NOR gate, the signal to be sampled can be obtained.

[0098] Taking the aforementioned DRAM as an example, the first pulse signal refers to the chip select signal, and the second pulse signal refers to the C / A signal. If the chip select signal is 0, the C / A signal is valid. At this time, the level of the signal to be sampled is the same as that of the C / A signal, ensuring that the valid C / A signal can normally control the DRAM. If the chip select signal is 1, the C / A signal is invalid. At this time, the level of the signal to be sampled is constant at 0, meaning that the signal to be sampled will not flip with the invalid C / A signal, thereby reducing power loss.

[0099] Furthermore, in some embodiments, the first sampling sub-circuit may include a third signal input terminal and a first sampler, wherein the third signal input terminal is connected to the clock port of the first sampler, and the input terminal of the first sampler is connected to the output terminal of the logic unit; wherein,

[0100] The third signal input terminal is used to receive the standard clock signal;

[0101] The first sampler is used to sample the signal to be sampled using a standard clock signal to obtain the target sampled signal.

[0102] It should be noted that the sampling process requires a standard clock signal as a reference. Therefore, the first sampling sub-circuit 304 may include a third signal input terminal and a first sampler. In this case, the third signal input terminal is used to receive the standard clock signal; then, the first sampler uses the standard clock signal to sample the processed input signal to obtain the target sampled signal. Here, the first sampler can be a latch.

[0103] Furthermore, the input sampling circuit 30 may further include a second sampling sub-circuit, which may include a fourth signal input terminal and a second sampler. The fourth signal input terminal is connected to the clock port of the second sampler, and the input terminal of the second sampler is connected to the first signal input terminal.

[0104] The fourth signal input terminal is used to receive the standard clock signal;

[0105] The second sampler is used to sample the first pulse signal using a standard clock signal to obtain the sampled first pulse signal.

[0106] It should be noted that, for the input sampling circuit, in addition to sampling the second pulse signal, it is also necessary to sample the first pulse signal so that the first pulse signal can be correctly decoded based on the second pulse signal in the subsequent decoding process.

[0107] Therefore, the input sampling circuit 30 further includes a second sampling sub-circuit, which includes a fourth signal input terminal and a second sampler. The fourth signal input terminal is used to receive a standard clock signal, and the second sampler is used to sample the first pulse signal using the standard clock signal to obtain the sampled first pulse signal. Here, the second sampler can be a latch.

[0108] Generally, the first and second pulse signals need to be sampled based on a standard clock signal of the same frequency. Therefore, a single clock signal input can be used as both the third and fourth signal inputs.

[0109] After the above processing, when the second pulse signal is valid, the target sampled signal obtained after sampling the second pulse signal can be determined, as well as the sampled first pulse signal obtained after sampling the first pulse signal. Therefore, in some embodiments, the input sampling circuit 30 further includes a decoder, the two input terminals of which are respectively connected to the output terminals of the first sampling sub-circuit and the second sampling sub-circuit; wherein,

[0110] The decoder is used to decode the target sampled signal based on the first pulse signal after sampling to obtain the target signal.

[0111] It should be noted that the input sampling circuit 30 may also include a decoder, which decodes the target sampled signal according to the first pulse signal after sampling to obtain the target signal, so that the DRAM can complete the corresponding operation instructions according to the target signal.

[0112] In summary, in the input sampling circuit provided in this application embodiment, the signal to be sampled will only undergo state flipping following the first pulse signal when the first pulse signal is valid. That is, the input sampling circuit will only sample and consume energy from the valid second pulse signal, thereby avoiding meaningless energy consumption. It should be understood that the structure of the above logic unit is only an example. In fact, the logic unit 303 can utilize AND gates, OR gates, NOT gates, NAND gates, NOR gates, XNOR gates, XOR gates, etc., to achieve the aforementioned effect through various logical combinations. These logical combination methods are all within the protection scope of this application embodiment.

[0113] This application provides an input sampling circuit, which includes a first signal input terminal for receiving a first pulse signal; a second signal input terminal for receiving a second pulse signal; a logic operator for performing logical operations on the first and second pulse signals to obtain a signal to be sampled; wherein the signal to be sampled is obtained by masking invalid signals in the second pulse signal based on the result of the logical operation; and a first sampling sub-circuit for sampling the signal to be sampled to obtain a target sampled signal. In this way, by performing logical operations on the first and second pulse signals, invalid signals in the second pulse signal can be masked, thus preventing the signal to be sampled from undergoing level state flips due to invalid signals in the first pulse signal, thereby reducing the functional loss of the input sampling circuit.

[0114] In another embodiment of this application, the aforementioned method and circuit structure are specifically described using a C / A input sampling circuit in a DRAM as an example. See [link to documentation]. Figure 5 It shows a schematic diagram of another input sampling circuit 30 provided in an embodiment of this application.

[0115] like Figure 5 As shown, the input sampling circuit 30 includes a first signal input terminal 401, a second signal input terminal 402, a logic unit 403, a clock signal input terminal 404, a first latch 405, a second latch 406, and a decoder 407. The clock signal input terminal 404 and the first latch 405 constitute the aforementioned first sampling sub-circuit, and the clock signal input terminal 404 and the second latch 406 constitute the aforementioned second sampling sub-circuit.

[0116] The first signal input terminal 401, the second signal input terminal 102, and the clock signal input terminal 404 are all essentially receivers. Here, the first signal input terminal 401 receives the external CS_n signal and the reference (VREFCA) signal to obtain the received CS_n signal. The second signal input terminal 402 receives the external C / A signal and the reference (VREFCA) signal to obtain the received C / A signal. The clock signal input terminal 404 receives the standard clock signal (CKT signal / CKB signal). It should be understood that the "CS_n signal" is compared with the reference voltage to form the "received CS_n signal," meaning that the waveform and function of the CS_n signal and the received CS_n signal are essentially the same, both referring to the chip select signal. Therefore, similarly, the waveform and function of the C / A signal and the received C / A signal are essentially the same.

[0117] The logic unit 403 is connected to the first signal input terminal 401 and the second signal input terminal 402, and is used to perform logic operations on the CS_n signal and the received C / A signal to obtain the C / A Input signal.

[0118] The first latch 405 is connected to the first signal input terminal 401 and the clock signal input terminal 404. It uses a standard clock signal to sample the CS_n Input signal (i.e., the received CS_n signal) to obtain the CS_n Output signal. In other words, the received CS_n signal is directly sampled and processed as the CS_n Input signal.

[0119] The second latch 406 is connected to the logic unit 403 and the clock signal input terminal 404. It uses a standard clock signal to sample the C / A Input signal to obtain the C / A Output signal. In other words, the received C / A Input signal needs to be processed by performing operations on the received CS_n signal before being sampled.

[0120] Decoder 407 is connected to first latch 405 and second latch 406. It decodes C / AOutput signal based on CS_n Output signal to obtain CMD signal (equivalent to the aforementioned target signal).

[0121] In this embodiment, the C / A signal is valid when CS_n is 0 and invalid when CS_n is 1. Therefore, the logic unit 403 includes an NOT gate and a NOR gate to perform a NOT operation on the received CS_n signal, and then performs a NOR operation on the result and the received C / A signal to finally obtain the C / AInput signal. The logic operation formula is shown in equation (1).

[0122]

[0123] by Figure 6 For example, it shows a schematic diagram of signal changes in an input sampling circuit provided in an embodiment of this application. Figure 6 As shown, when the CS_n signal is 0 (this DRAM is the target chip), the C / A Input signal will follow the C / A signal. The decoded CMD signal can reflect the instruction content of the C / A signal. When CS_n is 1 (this DRAM is not the target chip), as shown by the dashed circle, the C / A Input is always 0 and will not toggle with the C / A signal, thus avoiding meaningless functional consumption.

[0124] In other words, by using the CS_n chip select signal to shield the C / A input signals of non-target DRAMs, the value of the C / A input signal of non-target DRAMs remains unchanged, thereby reducing the power consumption of the C / A sampling system. For the C / A signal of the target DRAM, a combinational logic is needed to select it from the CS_n chip select signal. Therefore, in the C / A input sampling system, if the DRAM does not receive a valid CS_n chip select signal, the C / A signal will be shielded, making the C / A signal constant at 0. Thus, even if there is an external C / A signal, the internal C / A sampling system will not perform data flipping when a valid CS_n chip select signal is not received, thereby saving power consumption of the C / A sampling system.

[0125] Thus, by utilizing the circuit design provided in this application embodiment, the input sampling circuit can reduce power consumption by shielding the sampling input when invalid C / A signals are continuously input. It should be understood that the DRAM C / A input sampling system is only one specific application scenario shown in this application embodiment, but this application embodiment is not limited to this scope; this circuit design can also be used in instruction acquisition and low-power systems.

[0126] In summary, the embodiments of this application provide an input sampling circuit. By inserting a control logic gate involving CS_n Input between the input of the C / A receiver and the C / A sampling circuit, when CS_n Input is 0, C / A Input is transmitted normally and sampled by the subsequent CKT signal; when CS_n Input is 1, C / A Input is masked to a constant value of 0, and the CKT signal will not undergo sampling inversion afterward.

[0127] Thus, when the CS_n chip select signal is 1 and the DRAM is not the target chip, the C / A input signal is shielded before being sampled by CKT, making it constant at 0, thereby reducing current consumption caused by signal flipping due to invalid inputs during C / A sampling. Since each DRAM in the C / A data bus has a separate input sampling circuit, i.e., there are many redundant sampling modules, the embodiments of this application can significantly reduce circuit power consumption.

[0128] This application provides an input sampling circuit. This embodiment elaborates on the specific implementation method of the aforementioned embodiments. It can be seen that by performing logical operations on the first pulse signal and the second pulse signal, invalid signals in the second pulse signal can be shielded. As a result, the signal to be sampled will not undergo level state flipping with the invalid signals in the first pulse signal, thereby reducing the functional loss of the input sampling circuit.

[0129] In another embodiment of this application, a semiconductor memory is provided, which includes at least the aforementioned input sampling circuit 30.

[0130] Since the semiconductor memory includes an input sampling circuit 30, by performing logical operations on the first pulse signal and the second pulse signal, invalid signals in the second pulse signal can be shielded, so that the signal to be sampled will not flip its level state with the invalid signals in the first pulse signal, thereby reducing the functional loss of the input sampling circuit.

[0131] Furthermore, the semiconductor memory can be DRAM.

[0132] The above are merely preferred embodiments of this application and are not intended to limit the scope of protection of this application.

[0133] It should be noted that, in this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0134] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0135] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0136] The features disclosed in the several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0137] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0138] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An input sampling method, characterized in that, The method includes: Receive the first pulse signal and the second pulse signal; Logical operations are performed on the first pulse signal and the second pulse signal to determine the signal to be sampled; wherein, the signal to be sampled is obtained by masking out invalid signals in the second pulse signal based on the result of the logical operation. The signal to be sampled is processed to obtain the target sampled signal; The method further includes: decoding the target sampled signal to obtain the target signal; The decoding process of the target sampled signal to obtain the target signal includes: The first pulse signal after sampling is determined; wherein, the first pulse signal after sampling is obtained by sampling the first pulse signal using a standard clock signal; The target sampled signal is decoded based on the first pulse signal after sampling to obtain the target signal.

2. The input sampling method according to claim 1, characterized in that, The step of performing logical operations on the first pulse signal and the second pulse signal to determine the signal to be sampled includes: Perform a logical NOT operation on the second pulse signal to obtain the processed second pulse signal; The first pulse signal and the processed second pulse signal are subjected to a logical OR-NOT operation to obtain the signal to be sampled.

3. The input sampling method according to claim 1, characterized in that, The sampling process of the signal to be sampled to obtain the target sampled signal includes: Receive standard clock signals; The target sampled signal is obtained by sampling the signal to be sampled using the standard clock signal.

4. The input sampling method according to claim 1, characterized in that, The method further includes: If the result of the logical operation indicates that the second pulse signal is invalid, the level state of the signal to be sampled is determined to be masked to a preset value; If the result of the logical operation indicates that the second pulse signal is valid, it is determined that the level state of the signal to be sampled is the same as that of the second pulse signal.

5. The input sampling method according to claim 4, characterized in that, The first pulse signal is a chip select signal; Accordingly, the method further includes: When the chip select signal is high, it is determined that the result of the logic operation indicates that the second pulse signal is invalid; When the chip select signal is low, the result of the logic operation indicates that the second pulse signal is valid.

6. The input sampling method according to any one of claims 1-5, characterized in that, The second pulse signal is a control signal or an address signal.

7. An input sampling circuit, characterized in that, The input sampling circuit includes: The first signal input terminal is used to receive the first pulse signal; The second signal input terminal is used to receive the second pulse signal; A logic arithmetic unit is used to perform logical operations on the first pulse signal and the second pulse signal to obtain a signal to be sampled; wherein, the signal to be sampled is obtained by masking out invalid signals in the second pulse signal based on the result of the logical operation; The first sampling sub-circuit is used to sample the signal to be sampled to obtain the target sampling signal; The two input terminals of the logic unit are respectively connected to the first signal input terminal and the second signal input terminal, and the output terminal of the logic unit is connected to the first sampling sub-circuit. The input sampling circuit further includes a second sampling sub-circuit, which includes a fourth signal input terminal and a second sampler. The fourth signal input terminal is connected to the clock port of the second sampler, and the input terminal of the second sampler is connected to the first signal input terminal. The fourth signal input terminal is used to receive a standard clock signal; The second sampler is used to sample the first pulse signal using the standard clock signal to obtain the sampled first pulse signal; The input sampling circuit further includes a decoder, the two input terminals of which are respectively connected to the output terminals of the first sampling sub-circuit and the second sampling sub-circuit; wherein... The decoder is used to decode the target sampled signal according to the first pulse signal after sampling to obtain the target signal.

8. The input sampling circuit according to claim 7, characterized in that, The logic unit includes NOT gates and NOR gates; wherein... The NOT gate is used to perform a logical NOT operation on the second pulse signal to obtain the processed second pulse signal. The NOR gate is used to perform a logical NOR operation on the first pulse signal and the processed second pulse signal to obtain the signal to be sampled. The input terminal of the NOT gate is connected to the second signal input terminal, the first input terminal of the NOR gate is connected to the first signal input terminal, and the second input terminal of the NOR gate is connected to the output terminal of the NOT gate.

9. The input sampling circuit according to claim 7, characterized in that, The first sampling sub-circuit includes a third signal input terminal and a first sampler. The third signal input terminal is connected to the clock port of the first sampler, and the input terminal of the first sampler is connected to the output terminal of the logic unit. The third signal input terminal is used to receive a standard clock signal; The first sampler is used to sample the signal to be sampled using the standard clock signal to obtain the target sampled signal.

10. A semiconductor memory, characterized in that, Includes the input sampling circuit as described in any one of claims 7 to 9.

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