A packaging method and a packaging structure thereof

Abstract

The embodiment of the present application provides a packaging method, comprising the following steps: providing a substrate with a groove on a surface, the substrate comprising at least one pad, and the groove exposing the pad; providing a chip, the chip having a first surface and a second surface opposite to each other, and at least one conductive bump arranged on the first surface of the chip; filling a first adhesive in the groove; applying a second adhesive on the first surface of the chip and the conductive bump; and mounting the chip to the substrate, the conductive bump being connected with the pad through the first adhesive and the second adhesive.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging, and in particular to a packaging method and a packaging structure thereof. Background Art

[0002] Flip chip technology is a chip interconnection technology. At present, flip chip technology has become a packaging form frequently used in the fields of high-end devices and high-density packaging.

[0003] In the existing flip chip technology, an adhesive is used to securely connect the chip and the substrate.

[0004] However, when there is a groove around the pad on the substrate, air is likely to remain in the groove during the flip-chip process, affecting the connection reliability between the chip and the substrate. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide a packaging method and a packaging structure thereof to solve at least one problem existing in the background technology.

[0006] To achieve the above object, the technical solution of the present invention is achieved as follows:

[0007] An embodiment of the present invention provides a packaging method, comprising: providing a substrate having a groove on a surface thereof, the substrate comprising at least one pad, the groove exposing the pad;

[0008] Providing a chip, the chip having a first surface and a second surface opposite to each other, at least one conductive bump being disposed on the first surface of the chip;

[0009] Filling the groove with a first adhesive;

[0010] applying a second adhesive on the first surface of the chip and the conductive bumps;

[0011] The chip is mounted on the substrate, and the conductive bumps are connected to the pads through the first adhesive and the second adhesive.

[0012] In the above solution, the first adhesive includes non-conductive paste (NCP), and the second adhesive includes non-conductive film (NCF).

[0013] In the above solution, the thickness of the second adhesive is greater than the thickness of the first adhesive.

[0014] In the above solution, filling the first adhesive in the groove includes:

[0015] The first adhesive is filled into the groove until the groove is filled, and the first adhesive is planarized so that the upper surface of the first adhesive is flush with the surface of the substrate.

[0016] In the above solution, the first adhesive is a non-conductive adhesive, and the first adhesive contains a thermosetting resin; the second adhesive is a non-conductive adhesive, and the second adhesive contains a thermosetting resin.

[0017] In the above scheme, the substrate also includes a carrier and a solder resist layer; the step of providing a substrate with a groove on the surface includes: providing a carrier, forming a solder resist layer with a first opening on the carrier, and the first opening constitutes the groove on the surface of the substrate.

[0018] In the above solution, after the first adhesive is filled in the groove, the packaging method further includes:

[0019] A second opening is formed in the first adhesive, the second opening exposing the pad.

[0020] In the above solution, after the chip is mounted on the substrate, the second adhesive is in contact and connected with the first adhesive and the surface of the substrate at the same time.

[0021] In the above solution, the step of mounting the chip on the substrate includes: providing a thermocompression bonding device, wherein the thermocompression bonding device contacts the second surface of the chip and heats and pressurizes the chip to mount the chip on the substrate.

[0022] In the above solution, the conductive bumps include solder; after the chip is mounted on the substrate, a reflow process is performed on the conductive bumps.

[0023] In the above solution, after the chip is mounted on the substrate, the packaging method further includes a step of curing the first adhesive and the second adhesive.

[0024] An embodiment of the present invention further provides a packaging structure, including:

[0025] A substrate having a groove on its surface, the substrate comprising at least one pad, the groove exposing the pad;

[0026] a first adhesive disposed in the groove;

[0027] A chip having a first surface and a second surface opposite to each other, and at least one conductive bump is provided on the first surface of the chip;

[0028] The second adhesive is located between the first surface of the chip and the first adhesive, and the conductive bump is connected to the pad through the second adhesive and the first adhesive.

[0029] In the above solution, the first adhesive includes non-conductive paste (NCP), and the second adhesive includes non-conductive film (NCF).

[0030] In the above solution, the surface where the first adhesive and the second adhesive are connected is flush with the surface of the substrate.

[0031] In the above solution, the first adhesive is a non-conductive adhesive, and the first adhesive contains a thermosetting resin; the second adhesive is a non-conductive adhesive, and the second adhesive contains a thermosetting resin.

[0032] In the above solution, the substrate further includes a carrier and a solder resist layer formed on the carrier, the solder resist layer has a first opening exposing the surface of the carrier, and the first opening constitutes the groove on the surface of the substrate.

[0033] In the above solution, the second adhesive covers the first surface of the chip and part of the side surface of the chip.

[0034] In the above solution, the second adhesive is in contact with and connected to the first adhesive and the surface of the substrate at the same time.

[0035] In the above solution, the conductive bump includes solder.

[0036] An embodiment of the present invention provides a packaging method and packaging structure thereof, wherein the packaging method includes: providing a substrate having a groove on its surface, the substrate including at least one solder pad, the groove exposing the solder pad; providing a chip, the chip having a first surface and a second surface opposite to each other, the first surface of the chip being provided with at least one conductive bump; filling the groove with a first adhesive; applying a second adhesive to the first surface of the chip and the conductive bump; and mounting the chip to the substrate, the conductive bump being connected to the solder pad through the first adhesive and the second adhesive. Filling the groove with the first adhesive before mounting the chip to the substrate can solve the problem of air not being completely discharged from the groove, resulting in gaps, when the chip is mounted to the substrate only with the second adhesive. This significantly reduces the probability of bridging between the conductive bumps in the subsequent reflow process and improves the reliability of the package.

[0037] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 A schematic diagram of a packaging method provided in the related art;

[0039] Figure 2 A flowchart of a packaging method according to an embodiment of the present invention;

[0040] Figures 3a-3g This is a process flow chart of the packaging method provided by an embodiment of the present invention.

[0041] Figure 4 A schematic diagram of a packaging structure provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0042] The following describes exemplary embodiments of the present invention in more detail with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0043] In the following description, numerous specific details are provided to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present invention; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0044] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0045] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there can be no intervening elements or layers. It should be understood that while the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another. Thus, without departing from the teachings of the present invention, a first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. Furthermore, when a second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part is present in the present invention.

[0046] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0047] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present invention. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0048] Figure 1This is a schematic diagram of a packaging method provided in the related art. As shown in the figure, a substrate 1 having a groove 14 on its surface is provided. The substrate 1 includes at least one pad 13 , and the groove 14 exposes the pad 13 .

[0049] A chip 2 is provided. The chip 2 includes a first surface 2 a and a second surface 2 b that are opposite to each other. At least one conductive bump 22 is formed on the first surface 2 a.

[0050] An adhesive 3 is applied on the first surface 2 a of the chip 2 and the conductive bumps 22 .

[0051] A hot pressing device 4 is provided on the second surface 2 b of the chip 2 , and the hot pressing device 4 mounts the chip 2 on the substrate 1 . The conductive bumps 22 pass through the adhesive 3 and are connected to the pads 13 .

[0052] However, in the above-mentioned packaging method, after the chip 2 is mounted on the substrate 1, the adhesive 3 cannot completely fill the groove 14, so that air often remains around the pad 13, resulting in the existence of gaps. During the subsequent reflow soldering process, the residual air can easily cause bridging between the pads 13, affecting the reliability of the package.

[0053] Based on this, the following technical solutions of the embodiments of the present invention are proposed.

[0054] The embodiment of the present invention provides a packaging method, such as Figure 2 As shown, the packaging method includes the following steps:

[0055] Step 201: providing a substrate having a groove on its surface, wherein the substrate includes at least one pad, and the groove exposes the pad;

[0056] Step 202: providing a chip, wherein the chip has a first surface and a second surface opposite to each other, and at least one conductive bump is provided on the first surface of the chip;

[0057] Step 203: Filling the groove with a first adhesive;

[0058] Step 204: applying a second adhesive on the first surface of the chip and the conductive bumps;

[0059] Step 205 : Mount the chip on the substrate, and connect the conductive bump to the pad through the first adhesive and the second adhesive.

[0060] In an embodiment of the present invention, before the chip is mounted on the substrate, the first adhesive is filled in the groove of the substrate. This can solve the problem that air cannot be completely discharged from the groove when the chip is mounted on the substrate only by the second adhesive, greatly reduce the probability of bridging between conductive bumps in the subsequent reflow process, and improve the reliability of the package.

[0061] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the following Figures 3a-3g The packaging method provided by the embodiment of the present invention is further described in detail.

[0062] First, execute step 201, such as Figure 3a , providing a substrate 1 having a groove 14 on its surface, wherein the substrate 1 includes at least one pad 13 , and the groove 14 exposes the pad 13 .

[0063] In one embodiment, the substrate 1 further includes a carrier 11 and a solder resist layer 12; the step of providing a substrate 1 having a surface having a groove 14 includes: providing a carrier 11, forming a solder resist layer 12 having a first opening on the carrier 11, and the first opening constituting the groove 14 on the surface of the substrate.

[0064] In one embodiment, the substrate may be a PCB board or a BT board, and the solder resist layer may be green paint.

[0065] Next, execute step 202, as Figure 3b As shown, a chip 2 is provided. The chip 2 has a first surface 2 a and a second surface 2 b opposite to each other. At least one conductive bump 22 is provided on the first surface 2 a of the chip 2 .

[0066] In one embodiment, an under bump metallurgy (UBM) layer 21 is further disposed on the first surface 2 a of the chip 2 . The under bump metallurgy layer 21 is located between the first surface 2 a and the conductive bumps 22 .

[0067] In one embodiment, the chip 2 is an active device, such as a dynamic random access memory (DRAM), but is not limited thereto, and the chip 2 may also be a passive device.

[0068] Then, execute step 203, as Figure 3c As shown, the groove 14 is filled with a first adhesive 31 .

[0069] In one embodiment, the first adhesive 31 includes a non-conductive paste (NCP) in a paste form, and the first adhesive 31 in a paste form fills the groove 14. In a specific embodiment, the first adhesive 31 includes a thermosetting resin.

[0070] In one embodiment, filling the first adhesive 31 in the groove 14 includes: filling the first adhesive 31 into the groove 14 until the groove 14 is filled, and planarizing the first adhesive 31 so that the upper surface of the first adhesive 31 is flush with the surface of the substrate 1 .

[0071] Before the chip 2 is mounted on the substrate 1, the first adhesive 31 is filled in the groove 14 of the substrate 1. This can solve the problem of air not being able to be completely discharged from the groove 14 and causing gaps, greatly reducing the probability of bridging between the conductive bumps 22 in the subsequent reflow process and improving the reliability of the package.

[0072] In one embodiment, after the first adhesive 31 is filled in the groove 14, the packaging method further includes: forming a second opening 311 in the first adhesive 31, wherein the second opening 311 exposes the pad 13, such as Figure 3d The second opening 311 can facilitate the flow of other adhesives (such as the second adhesive 32 described later) when the chip 2 is subsequently installed, and can increase the contact area between the first adhesive 31 and other adhesives, thereby increasing the bonding strength.

[0073] It should be noted that the second opening 211 can be formed selectively. In other embodiments, the step of forming the second opening 211 can be omitted.

[0074] Next, execute step 204, as Figure 3e As shown, a second adhesive 32 is applied on the first surface 2 a of the chip 2 and the conductive bumps 22 .

[0075] In one embodiment, the second adhesive 32 includes a non-conductive film (NCF), that is, the second adhesive 32 is in a film shape. In a specific embodiment, the second adhesive 32 includes a thermosetting resin.

[0076] In one embodiment, the thickness of the second adhesive 32 is greater than the thickness of the first adhesive 31. Thus, after the chip 2 is mounted on the substrate 1, the second adhesive 32 can cover part of the side surface of the chip 2, thereby reducing the contact area between the subsequent encapsulation material (EMC) and the side surface of the chip 2, thereby reducing the risk of delamination caused by a large difference in thermal expansion coefficient between the encapsulation material and the chip 2.

[0077] Then, execute step 205, as Figure 3f and Figure 3g As shown, the chip 2 is mounted on the substrate 1 , and the conductive bumps 22 are connected to the pads 13 through the first adhesive 31 and the second adhesive 32 .

[0078] In one embodiment, mounting the chip 2 on the substrate 1 includes:

[0079] A thermocompression bonding device (TCB) 4 is provided. The thermocompression bonding device 4 contacts the second surface 2 b of the chip 2 and applies heat and pressure to the chip 2 to mount the chip 2 on the substrate 1 .

[0080] like Figure 3g As shown, after the chip is mounted on the substrate 1 , the second adhesive 32 is in contact and connected with the first adhesive 31 and the surface of the substrate 1 at the same time.

[0081] In one embodiment, the conductive bumps 22 include solder, and after the chip 2 is mounted on the substrate 1, a reflow process is performed on the conductive bumps 22. However, the present invention is not limited thereto, and the conductive bumps may also be made of other suitable metal materials.

[0082] After the chip 2 is mounted on the substrate 1 , the packaging method further includes a step of curing the first adhesive 31 and the second adhesive 32 .

[0083] An embodiment of the present invention also provides a packaging structure, comprising: a substrate having a groove on its surface, the substrate including at least one solder pad, the groove exposing the solder pad; a first adhesive, the first adhesive being arranged in the groove; a chip, the chip having a first surface and a second surface relative to each other, at least one conductive bump being arranged on the first surface of the chip; a second adhesive, located between the first surface of the chip and the first adhesive, the conductive bump being connected to the solder pad through the second adhesive and the first adhesive.

[0084] The packaging structure provided by the embodiment of the present invention has a first adhesive disposed in the groove, which greatly improves the reliability of the packaging structure compared with the packaging structure in the related art that only includes a second adhesive.

[0085] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the following Figure 4 The packaging structure provided by the embodiment of the present invention is further described in detail.

[0086] like Figure 4As shown, the packaging structure includes a substrate 1, a first adhesive 31, a second adhesive 32, and a chip 2 mounted on the substrate 1 through the first adhesive 31 and the second adhesive 32, the surface of the substrate 1 has a groove 14, a pad 13 is provided on the substrate 1, the groove 14 exposes the pad 13, and the first adhesive 31 is provided in the groove 14; the chip 2 has a first surface 2a and a second surface 2b opposite to the first surface 2a, a conductive bump 22 is provided on the first surface 2a, and the conductive bump 22 is connected to the pad 13 through the first adhesive 31 and the second adhesive 32.

[0087] In one embodiment, the first adhesive 31 includes non-conductive paste (NCP); in a specific embodiment, the first adhesive 31 includes thermosetting resin.

[0088] In one embodiment, the first adhesive 31 is filled into the groove 14 before the chip 2 is mounted on the substrate 1. This solves the problem of air not being completely exhausted from the groove 14 when the chip 2 is mounted on the substrate 1 using only the second adhesive 32. This significantly reduces the probability of bridging between the conductive bumps 22 during the subsequent reflow process, thereby improving the reliability of the package.

[0089] In one embodiment, the surface where the first adhesive 31 and the second adhesive 32 are connected is flush with the surface of the substrate.

[0090] In one embodiment, the substrate 1 further includes a carrier 11 and a solder resist layer 12 formed on the carrier, wherein the solder resist layer 12 has a first opening exposing the surface of the carrier 11, and the first opening constitutes the groove 14 on the substrate surface. In a specific embodiment, the substrate 1 includes a PCB board, and the solder resist layer 12 includes green paint.

[0091] In one embodiment, the second adhesive 32 includes a non-conductive film (NCF). In a specific embodiment, the second adhesive 32 includes a thermosetting resin.

[0092] In one embodiment, the second adhesive 32 is applied to the first surface 2 a of the chip 2 and the conductive bumps 22 before the chip 2 is mounted on the substrate 1 .

[0093] In one embodiment, the second adhesive 32 covers the first surface 2a of the chip 2 and a portion of the side surface of the chip 2. The second adhesive 32 covers a portion of the side surface of the chip 2, which can reduce the contact area between the subsequent encapsulation material (EMC) and the side surface of the chip 2, thereby reducing the risk of delamination caused by a large difference in thermal expansion coefficient between the encapsulation material and the chip 2.

[0094] In one embodiment, the second adhesive 32 is in contact with and connected to the first adhesive 31 and the surface of the substrate at the same time.

[0095] In one embodiment, the conductive bumps 22 include solder, but are not limited thereto. The conductive bumps 22 may also include other metal materials.

[0096] In one embodiment, see Figure 4 The first surface 2 a of the chip 2 is further provided with an under bump metallurgy layer 21 , and the under bump metallurgy layer 21 is located between the first surface 2 a and the conductive bump 22 .

[0097] The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A packaging method, characterized in that: include: Providing a substrate having a groove on its surface, the substrate including at least one pad, wherein the groove exposes the pad; Providing a chip, the chip having a first surface and a second surface opposite to each other, at least one conductive bump being disposed on the first surface of the chip; filling the groove with a first adhesive; applying a second adhesive on the first surface of the chip and the conductive bumps; Mounting the chip on the substrate, wherein the conductive bump is connected to the pad through the first adhesive and the second adhesive; After the first adhesive is filled in the groove, the packaging method further comprises: A second opening is formed in the first adhesive, the second opening exposing the pad.

2. The packaging method according to claim 1, wherein: The first adhesive includes a non-conductive paste (NCP), and the second adhesive includes a non-conductive film (NCF).

3. The packaging method according to claim 1, wherein: The thickness of the second adhesive is greater than that of the first adhesive.

4. The packaging method according to claim 1, wherein: Filling the groove with a first adhesive comprises: The first adhesive is filled into the groove until the groove is filled, and the first adhesive is planarized so that the upper surface of the first adhesive is flush with the surface of the substrate.

5. The packaging method according to claim 1, wherein: The first adhesive is a non-conductive adhesive and contains a thermosetting resin; the second adhesive is a non-conductive adhesive and contains a thermosetting resin.

6. The packaging method according to claim 1, wherein: The substrate further comprises a carrier and a solder resist layer; the step of providing a substrate having a groove on its surface comprises: providing a carrier, forming a solder resist layer having a first opening on the carrier, wherein the first opening constitutes the groove on the surface of the substrate.

7. The packaging method according to claim 1, wherein: After the chip is mounted on the substrate, the second adhesive is in contact with and connected to the first adhesive and the surface of the substrate at the same time.

8. The packaging method according to claim 1, wherein: The step of mounting the chip on the substrate includes providing a thermocompression bonding device that contacts the second surface of the chip and applies heat and pressure to the chip to mount the chip on the substrate.

9. The packaging method according to claim 1, wherein: The conductive bumps include solder; after the chip is mounted on the substrate, a reflow process is performed on the conductive bumps.

10. The packaging method according to claim 1, wherein: After mounting the chip on the substrate, the packaging method further includes a step of curing the first adhesive and the second adhesive.

11. A packaging structure, characterized in that: The packaging structure is prepared by the packaging method according to claim 1, comprising: A substrate having a groove on its surface, the substrate comprising at least one pad, the groove exposing the pad; a first adhesive disposed in the groove; A chip having a first surface and a second surface opposite to each other, and at least one conductive bump is provided on the first surface of the chip; The second adhesive is located between the first surface of the chip and the first adhesive, and the conductive bump is connected to the pad through the second adhesive and the first adhesive.

12. The packaging structure according to claim 11, wherein: The first adhesive includes a non-conductive paste (NCP), and the second adhesive includes a non-conductive film (NCF).

13. The packaging structure according to claim 11, wherein: The surface where the first adhesive and the second adhesive are connected is flush with the surface of the substrate.

14. The packaging structure according to claim 11, wherein: The first adhesive is a non-conductive adhesive and contains a thermosetting resin; the second adhesive is a non-conductive adhesive and contains a thermosetting resin.

15. The packaging structure according to claim 11, wherein: The substrate further includes a carrier and a solder resist layer formed on the carrier. The solder resist layer has a first opening exposing the surface of the carrier. The first opening constitutes the groove on the surface of the substrate.

16. The packaging structure according to claim 11, wherein: The second adhesive covers the first surface of the chip and a portion of the side surface of the chip.

17. The packaging structure according to claim 11, wherein: The second adhesive is in contact with and connected to the first adhesive and the surface of the substrate at the same time.

18. The packaging structure according to claim 11, wherein: The conductive bumps include solder.

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