Test structures and methods of forming the same

Abstract

A test structure and a forming method thereof, the test structure comprising: a substrate, the substrate comprising a test region, a first lead region on one side of the test region, and a second lead region on the other side of the test region along a first direction, the first lead region and the second lead region both for loading a test signal; a dielectric layer on the substrate; a first metal structure in the dielectric layer, the first metal structure comprising a plurality of first metal lines extending along the first direction and arranged in parallel along a second direction, the second direction being perpendicular to the first direction; and a comb-shaped second metal structure comprising a plurality of comb-tooth-shaped second metal lines in the test region and a comb-handle-shaped metal plate in the second lead region, the second metal lines extending along the first direction and arranged in parallel along the second direction, the metal plate extending along the second direction, and the second metal lines and the first metal lines being alternately arranged along the second direction. The first metal lines and the second metal lines only coexist in the test region, thereby improving the accuracy of test results.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a test structure and a method for forming the same. Background Technology

[0002] In the semiconductor device manufacturing process, reliability testing is frequently required. Especially with the advancement of semiconductor process technology, semiconductor devices are becoming increasingly integrated, and their dimensions are shrinking proportionally. Their critical dimensions (CD) are also becoming smaller. For semiconductor devices with increasingly smaller CDs, the interlayer dielectric (ILD) in the back-end of line (BEOL) process is also becoming thinner, making performance testing of the circuit structure manufactured using BEOL crucial.

[0003] In this field, time-dependent dielectric breakdown (TDDB) testing is commonly used for reliability testing. It can be used to predict the lifespan of semiconductor devices. Typically, a constant voltage is applied to a metal line, causing the device to accumulate voltage; this is what is commonly referred to as TDDB. After a period of time, the dielectric material will break down. The time elapsed from the application of a constant voltage to the point where the dielectric material breaks down is the dielectric lifespan under that condition. Summary of the Invention

[0004] The problem solved by this invention is to provide a test structure and its formation method, which improves the accuracy of test results.

[0005] To address the aforementioned problems, embodiments of the present invention provide a test structure, comprising: a substrate, the substrate including a test area, a first lead area located on one side of the test area, and a second lead area located on the other side of the test area along a first direction, wherein both the first lead area and the second lead area are used to load test signals; a dielectric layer located on the substrate; a first metal structure located in the dielectric layer, the first metal structure including a plurality of first metal lines extending along the first direction and arranged parallel to each other along a second direction, the second direction being perpendicular to the first direction; and a comb-shaped second metal structure including a plurality of comb-tooth-shaped second metal lines and a comb-handle-shaped metal plate, the second metal lines being located in the test area, the second metal lines extending along the first direction and arranged parallel to each other along the second direction, the metal plate being located in the second lead area and extending along the second direction, the second metal lines and the first metal lines being alternately arranged in the second direction.

[0006] Accordingly, embodiments of the present invention also provide a method for forming a test structure, comprising: providing a substrate, wherein a first dielectric layer is formed on the substrate, the substrate including a test region, a first lead region located on one side of the test region, and a second lead region located on the other side of the test region along a first direction, wherein both the first lead region and the second lead region are used to load test signals; forming a core layer covering the first dielectric layer; modifying the core layer located in the first lead region to transform the core layer of the first lead region into a shielding layer, wherein the etching resistance of the shielding layer is greater than that of the core layer; after performing the modification treatment, forming a first trench in the shielding layer of the first lead region and the core layer of the test region, wherein the first trench extends along the first direction and is arranged parallel to a second direction, the second direction being perpendicular to the first direction; forming a sidewall on the sidewall of the first trench; and after forming the sidewall, removing the remaining core layer located in the test region and the second lead region to form a comb-shaped second trench. The first trench includes a comb tooth groove in the test area and a comb handle groove in the second lead area, the comb handle groove extending along the second direction, and the comb tooth groove and the first trench are alternately arranged in the second direction; using the sidewall and the shielding layer as a mask, the first dielectric layer at the bottom of the first trench and the second trench is etched to form an interconnection opening, the interconnection opening including a first interconnection opening corresponding to the first trench and a second interconnection opening corresponding to the second trench, the second interconnection opening including a first sub-opening in the test area and a second sub-opening in the second lead area; a first metal structure is formed in the first interconnection opening, and a second metal structure is formed in the second interconnection opening, the first metal structure including a plurality of first metal lines extending along the first direction and arranged parallel to the second direction, the second metal structure including a second metal line located in the first sub-opening and alternately arranged with the first metal lines, and a metal plate located in the second sub-opening.

[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0008] In the test structure provided by this embodiment of the invention, the first metal line and the second metal line only appear together in the test area. The first lead area contains only the first metal line, and the second lead area contains only the metal plate. When testing the time-dependent dielectric breakdown lifetime (TDDB) or the breakdown voltage (VBD), the dielectric breakdown lifetime of the minimum interval is used as the test lifetime. Therefore, when testing the test structure of this embodiment of the invention, there is no voltage difference between the first metal lines located in the first lead area, and the second lead area contains only the metal plate and no dielectric. Thus, the first lead area and the second lead area are not included in the test. Only the dielectric breakdown lifetime between adjacent first metal lines and second metal lines located in the test area is tested. The test structure typically uses a through-hole interconnect structure to load test signals onto the first metal line and the second metal line. This reduces the influence of the through-hole interconnect structure on the test structure when testing the dielectric breakdown lifetime between adjacent first metal lines and second metal lines, reduces the probability of test errors caused by the presence of the through-hole interconnect structure, and improves the accuracy of the test results.

[0009] In the method for forming the test structure provided in this embodiment of the invention, the first metal wire and the second metal wire appear together only in the test area. The first lead area contains only the first metal wire, and the second lead area contains only the metal plate. When testing the time-dependent dielectric breakdown lifetime (TDDB) or the breakdown voltage (VBD), the dielectric breakdown lifetime of the minimum interval is used as the test lifetime. Therefore, when testing the test structure of this embodiment of the invention, there is no voltage difference between the first metal wires located in the first lead area, and the second lead area contains only the metal plate and no dielectric. Thus, the first lead area and the second lead area are not included in the test. Only the dielectric breakdown lifetime between adjacent first metal wires and second metal wires located in the test area is tested. The test structure typically uses a through-hole interconnect structure to load test signals onto the first metal wires and second metal wires. This reduces the influence of the through-hole interconnect structure on the test structure when testing the dielectric breakdown lifetime between adjacent first metal wires and second metal wires, reduces the probability of test errors caused by the presence of the through-hole interconnect structure, and improves the accuracy of the test results. Attached Figure Description

[0010] Figure 1 A top view of a test structure;

[0011] Figures 2 to 4 This is a schematic diagram of one embodiment of the test structure of the present invention;

[0012] Figures 5 to 23 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming the test structure of the present invention. Detailed Implementation

[0013] Currently, with the continuous shrinking of technology nodes, improving the accuracy of reliability test results has become a challenge, resulting in a need to improve the accuracy of test results. This paper analyzes the reasons why the accuracy of test results needs improvement using a specific test structure.

[0014] Figure 1 It is a top view of the test structure.

[0015] The test structure includes: a dielectric layer 10, wherein the dielectric layer 10 is along a first direction (e.g., Figure 1 The test area 10T (in the X direction) includes a test area 10T, a first lead area 10V1 located on one side of the test area 10T, and a second lead area 10V2 located on the other side of the test area 10T. Both the first lead area 10V1 and the second lead area 10V2 are used to load test signals. Multiple metal wires (not shown) are formed in the dielectric layer 10, and the metal wires extend along a first direction and along a second direction (e.g., ...). Figure 1 The metal wires are arranged in parallel along the Y direction, with the second direction perpendicular to the first direction. The metal wires along the second direction include alternating and equally spaced first metal wires 21 and second metal wires 22. A first through-hole interconnect structure 31 is located on top of the first metal wire 21 in the first lead area 10V1 and is used as a test signal loading end for the first metal wire 21. A second through-hole interconnect structure 32 is located on top of the second metal wire 22 in the second lead area 10V2 and is used as a test signal loading end for the second metal wire 22.

[0016] Typically, when forming the first via interconnect structure 31 and the second via interconnect structure 32, the dimensions of the first via interconnect structure 31 and the second via interconnect structure 32 expand along the second direction, such that the spacing w1 between the first via interconnect structure 31 and the adjacent second metal line 22 is smaller than the spacing d1 between the adjacent first metal line 21 and the second metal line 22. Similarly, the spacing w2 between the second via interconnect structure 32 and the adjacent first metal line 21 is smaller than the spacing d1 between the adjacent first metal line 21 and the second metal line 22. When the test structure is used to test time-related dielectric breakdown lifetime or to test breakdown voltage, the dielectric breakdown lifetime of the minimum spacing is used as the test lifetime. Therefore, when testing the adjacent first metal line 21... When testing the dielectric layer 10 between the first metal line 21 and the second metal line 22, since the intervals w1 and w2 are both smaller than the interval d1 between the adjacent first metal line 21 and the second metal line 22, it is difficult to accurately detect the breakdown lifetime of the dielectric layer 10 between the adjacent first metal line 21 and the second metal line 22. Furthermore, the actual breakdown lifetime obtained may be the breakdown lifetime of the dielectric layer 10 between the first via interconnect structure 31 on the top of the first metal line 21 and the adjacent second metal line 22, or the breakdown lifetime of the dielectric layer 10 between the second via interconnect structure 32 on the second metal line 22 and the adjacent first metal line 21. This results in a large error in the test results and significantly affects the accuracy of the test results.

[0017] To address the aforementioned technical problem, embodiments of the present invention provide a test structure, comprising: a substrate, the substrate including a test area, a first lead area located on one side of the test area, and a second lead area located on the other side of the test area along a first direction, wherein both the first lead area and the second lead area are used to load test signals; a dielectric layer located on the substrate; a first metal structure located in the dielectric layer, the first metal structure including a plurality of first metal lines extending along the first direction and arranged parallel to each other along a second direction, the second direction being perpendicular to the first direction; and a comb-shaped second metal structure including a plurality of comb-tooth-shaped second metal lines and a comb-handle-shaped metal plate, the second metal lines being located in the test area, the second metal lines extending along the first direction and arranged parallel to each other along the second direction, the metal plate being located in the second lead area and extending along the second direction, the second metal lines and the first metal lines being alternately arranged in the second direction.

[0018] In the test structure provided by this embodiment of the invention, the first metal line and the second metal line only appear together in the test area. The first lead area contains only the first metal line, and the second lead area contains only the metal plate. When testing the dielectric breakdown lifetime or the breakdown voltage related to the test time, the dielectric breakdown lifetime of the minimum interval is used as the test lifetime. Therefore, when testing the test structure of this embodiment of the invention, there is no voltage difference between the first metal lines located in the first lead area, and the second lead area contains only the metal plate and no dielectric. Thus, the first lead area and the second lead area are not included in the test. Only the dielectric breakdown lifetime between adjacent first metal lines and second metal lines located in the test area is tested. The test structure typically uses a through-hole interconnect structure to load test signals onto the first metal line and the second metal line. This reduces the influence of the through-hole interconnect structure on the test structure when testing the dielectric breakdown lifetime between adjacent first metal lines and second metal lines, reduces the probability of test errors caused by the presence of the through-hole interconnect structure, and improves the accuracy of the test results.

[0019] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0020] Figures 2 to 4 This is a schematic diagram of an embodiment of the test structure of the present invention, wherein, Figure 2 It is a top view. Figure 3 yes Figure 2 Cross-sectional view along the AA direction. Figure 4 a is Figure 2 Cross-sectional view along the BB direction. Figure 4 b is Figure 2 A sectional view along the CC direction.

[0021] The test structure includes: a substrate 101, the substrate 101 being arranged along a first direction (e.g., ...). Figure 2 (As shown in the X direction) includes a test area 101T, a first lead area 101V1 located on one side of the test area 101T, and a second lead area 101V2 located on the other side of the test area 101T. Both the first lead area 101V1 and the second lead area 101V2 are used to load test signals; a dielectric layer 201 is located on the substrate 101; a first metal structure (not shown) is located in the dielectric layer 201, the first metal structure including a structure extending along the first direction and along the second direction (e.g., ...). Figure 2Multiple first metal wires 611 are arranged in parallel in the Y direction, and the second direction is perpendicular to the first direction; a comb-shaped second metal structure (not shown) includes multiple comb-shaped second metal wires 631 and a comb-handle-shaped metal plate 641. The second metal wires 631 are located in the test area 101T. The second metal wires 631 extend along the first direction and are arranged in parallel in the second direction. The metal plate is located in the second lead area 101V2 and extends along the second direction. The second metal wires 631 and the first metal wires 611 are alternately arranged in the second direction.

[0022] In this embodiment, the test structure includes a TDDB test structure or a VBD test structure.

[0023] The TDDB test structure, or Time Dependent Dielectric Breakdown (TDDB) test structure, is used to predict the lifetime of semiconductor devices. Typically, the breakdown lifetime of the dielectric material is determined by detecting the breakdown time. A constant voltage is applied to the metal line, causing the device to accumulate voltage. After a period of time, the dielectric material will break down. The time elapsed from the application of the constant voltage to the end of the breakdown is the lifetime of the dielectric material under that condition.

[0024] The VBD test structure is a breakdown voltage (VBD) test structure. The VBD test is a pre-test of the TDDB test. It is used to determine the breakdown life of the dielectric material by detecting the breakdown voltage. The voltage is increased in a stepped manner on the metal wire. After a certain voltage is reached, the dielectric material will break down. The voltage applied when the dielectric material breaks down is the breakdown voltage of the dielectric material.

[0025] As an example, the test structure is the TDDB test structure.

[0026] In this embodiment, the test structure includes a substrate 101, which includes a substrate structure layer (not shown) and a substrate (not shown). Taking a planar semiconductor structure as an example, the substrate is a planar substrate. Specifically, the substrate is a silicon substrate. In other embodiments, the substrate material can also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate, etc., and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, etc. In other embodiments, when the test structure is a three-dimensional semiconductor structure, the substrate can also be a substrate with fins.

[0027] The substrate structure layer may also include other structures, such as gate structures, doped regions, shallow trench isolation (STI) structures, and dielectric layers, in which devices (e.g., MOS transistors or SRAM devices) are formed. Specifically, the substrate structure layer also includes an interlayer dielectric layer (not shown) formed on the substrate and contact (CT) plugs (not shown) formed in the interlayer dielectric layer.

[0028] In this embodiment, the substrate 101 includes a test area 101T, a first lead area 101V1 located on one side of the test area 101T, and a second lead area 101V2 located on the other side of the test area 101T along the first direction. Both the first lead area 101V1 and the second lead area 101V2 are used to load test signals. When testing using this test structure, test signals are loaded onto the first metal line 611 of the first lead area 101V1 and the metal plate 641 of the second lead area 101V2, respectively, to detect the dielectric breakdown lifetime between adjacent first metal lines 611 and second metal lines 231 located in the test area 101T, thereby achieving reliability testing.

[0029] In this embodiment, a dielectric layer 201 is formed on the substrate 101.

[0030] In this embodiment, the dielectric layer 201 is an inter-metal dielectric (IMD) layer, which is used to achieve electrical isolation between metal interconnect structures in the back end of line (BEOL) process.

[0031] Therefore, the dielectric layer 201 is made of a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) or an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative permittivity less than 2.6). In this embodiment, the dielectric layer 201 is made of one or more of SiOC, SiOCH, SiC, SiCN, SiO2, SiN, and SiON. In this embodiment, the dielectric layer 201 is made of an ultra-low-k dielectric material, thereby reducing the parasitic capacitance between the subsequent metal interconnect structures and thus reducing the subsequent RC delay. Specifically, the ultra-low-k dielectric material can be SiOCH.

[0032] Accordingly, in this embodiment, the first metal structure and the second metal structure are located in the dielectric layer 201, and along the second direction, adjacent first metal lines 611 and second metal lines 631 are separated by the dielectric layer 201, and the first metal line 611 and the metal plate 641 are separated by the dielectric layer 201.

[0033] It should be noted that the first metal line 611, the second metal line 631, and the metal plate 641 are metal interconnects on the same layer.

[0034] In the test structure provided in this embodiment, the first metal wire 611 and the second metal wire 631 appear together only in the test area 101T, the first lead area 101V1 contains only the first metal wire 611, and the second lead area 100V2 contains only the metal plate 641. When testing the dielectric breakdown lifetime or testing the breakdown voltage, the dielectric breakdown lifetime of the minimum interval is used as the test lifetime. Therefore, when testing the test structure of this embodiment, there is no voltage difference between the first metal wires 611 located in the first lead area 101V1, and the second lead area 101V2 contains only the metal plate 641 without... Because a dielectric material is present, the first lead region 101V1 and the second lead region 101V2 will not be included in the test. Only the dielectric breakdown lifetime between adjacent first metal lines 611 and second metal lines 631 located in the test region 101T will be tested. The test structure typically uses a through-hole interconnect structure to apply a test signal to the first metal lines 611 and second metal lines 631. This reduces the influence of the through-hole interconnect structure on the test structure when testing the dielectric breakdown lifetime between adjacent first metal lines 611 and second metal lines 631, reduces the probability of test errors caused by the presence of the through-hole interconnect structure, and improves the accuracy of the test results.

[0035] In this embodiment, in the test area 101T, in the second direction, the interval between adjacent first metal line 611 and second metal line 631 is equal, and the interval is a first interval S1. Here, the interval refers to the interval size.

[0036] Since the minimum interval dielectric breakdown lifetime is used as the TDDB test lifetime when the test structure is used to test the time-related dielectric breakdown lifetime, in this embodiment, in the test area 101T, the interval between adjacent first metal lines 611 and second metal lines 631 is equal in the second direction. Therefore, when performing the TDDB test, the dielectric breakdown lifetime between adjacent first metal lines 611 and second metal lines 631 can be detected more accurately, and the situation of large error in the detection result caused by different interval sizes between adjacent first metal lines 611 and second metal lines 631 can be avoided to a large extent.

[0037] In this embodiment, in the first direction, the distance between the end of each first metal wire 611 near the second lead area 101V2 and the metal plate 641 is equal, and the distance is the second distance S2.

[0038] Therefore, when performing TDDB testing, the dielectric breakdown lifetime between adjacent first metal lines 611 and metal plates 641 can be detected more accurately, and the error in the test results can be avoided to a large extent due to the different spacing sizes between adjacent first metal lines 611 and metal plates 641.

[0039] In this embodiment, the first interval S1 is equal to the second interval S2.

[0040] Therefore, in the test structure, the interval between adjacent positions of the first metal structure and the second metal structure is equal everywhere. Thus, when performing TDDB testing, the dielectric breakdown lifetime between the first metal structure and the second metal structure can be detected more accurately, and the situation of large error in the test results caused by the different interval sizes between adjacent positions of the first metal structure and the second metal structure can be avoided to a large extent.

[0041] In this embodiment, the material of the first metal structure includes one or more of copper, aluminum, and copper alloys, and the material of the second metal structure includes one or more of copper, aluminum, and copper alloys, thereby enabling the first metal structure and the second metal structure to achieve better conductivity.

[0042] In this embodiment, the first metal structure and the second metal structure are metal structures in the same layer, therefore, the first metal structure and the second metal structure are made of the same material.

[0043] In this embodiment, the dielectric layer 201 is defined as the first dielectric layer 201, and a second dielectric layer 701 covering the first metal structure and the second metal structure is also formed on the first dielectric layer 201.

[0044] The second dielectric layer 701 is also used to achieve electrical isolation between via interconnect structures in the later stages of the manufacturing process.

[0045] Therefore, the material of the second dielectric layer 701 is a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) or an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative permittivity less than 2.6). In this embodiment, the material of the second dielectric layer 701 includes one or more of SiOC, SiOCH, SiC, SiCN, SiO2, SiN, and SiON. In this embodiment, the material of the second dielectric layer 701 is an ultra-low-k dielectric material, thereby reducing the parasitic capacitance between the subsequent metal interconnect structures and thus reducing the subsequent RC delay. Specifically, the ultra-low-k dielectric material can be SiOCH.

[0046] In this embodiment, the test structure further includes: a first through-hole interconnect structure 711, located in the first lead area 101V1 and on top of the first metal wire 611, and electrically connected to the first metal wire 611, the first through-hole interconnect structure 711 serving as a test signal loading end of the first metal wire 611; and a second through-hole interconnect structure 721, located in the second lead area 101V2 and on top of the metal plate 641, and electrically connected to the metal plate 641, the second through-hole interconnect structure 721 serving as a test signal loading end of the second metal wire 631.

[0047] Correspondingly, the first via interconnect structure 711 and the second via interconnect structure 721 are located in the second dielectric layer 701.

[0048] The first through-hole interconnect structure 711 is used as the test signal loading end of the first metal line 611, and the second through-hole interconnect structure 721 is used as the test signal loading end of the second metal line 631, so that the test signal is loaded onto the first metal line 611 through the first through-hole interconnect structure 711 and the test signal is loaded onto the second metal line 631 through the second through-hole interconnect structure 721.

[0049] In this embodiment, the second through-hole interconnect structure 721 is located on the extension line of the second metal line 631, thereby not changing the formation position of the second through-hole interconnect structure 721 in the existing process and improving the process compatibility of forming the second through-hole interconnect structure 721.

[0050] Typically, when forming the first through-hole interconnect structure 711 and the second through-hole interconnect structure 721, the dimensions of the first through-hole interconnect structure 711 and the second through-hole interconnect structure 721 will expand along the second direction.

[0051] Therefore, in this embodiment, along the second direction, the width w1 of the first through-hole interconnect structure 711 is greater than the width d1 of the first metal line 611. Similarly, along the second direction, the width w2 of the second through-hole interconnect structure 721 is greater than the width d2 of the second metal line 631.

[0052] In other words, along the second direction, the interval between the first through-hole interconnect structure 711 at the top of the first metal line 611 and the adjacent second metal line 631 is smaller than the interval S1 between the adjacent first metal line 611 and the second metal line 631. Similarly, the interval between the second through-hole interconnect structure 721 on the metal plate 641 and the adjacent first metal line 611 is smaller than the interval S1 between the adjacent first metal line 611 and the second metal line 631.

[0053] Since there is no voltage difference between the first metal lines 611 in the first lead area 101V1 and no dielectric in the second lead area 101V2 when testing the test structure described in this embodiment, the first lead area 101V1 and the second lead area 101V2 will not be included in the test. Accordingly, even if the width w1 of the first via interconnect structure 711 is greater than the width d1 of the first metal line 611, or the width w2 of the second via interconnect structure 721 is greater than the width d2 of the second metal line 631, that is, even if there is a situation where the interval is smaller than the interval S1 between adjacent first metal lines 611 and second metal lines 631 due to the larger width w1 of the first via interconnect structure 711 or the width w2 of the second via interconnect structure 721, the probability of test error caused by the existence of an interval smaller than the interval S1 between adjacent first metal lines 611 and second metal lines 631 is still reduced when testing the dielectric breakdown lifetime between adjacent first metal lines 611 and second metal lines 631 using TDDB.

[0054] It should be noted that the number of first via interconnect structures 711 at the top of each first metal wire 611 should not be too many or too few. If the number of first via interconnect structures 711 is too many, and the feature size of the test structure is decreasing, it will easily increase the difficulty of forming the first via interconnect structure 711 and cause unnecessary process waste; if the number of first via interconnect structures 711 is too few, it will easily increase the probability of the first via interconnect structure 711 failing to connect. Therefore, in this embodiment, the number of first via interconnect structures 711 at the top of each first metal wire 711 is 2 to 5.

[0055] In this embodiment, there are 3 first through-hole interconnect structures 711 on the top of each first metal wire 611. As long as the forming process is simple, the first metal wire 611 is successfully electrically connected as long as one of the first through-hole interconnect structures 711 is successfully electrically connected. Therefore, by using 3 first through-hole interconnect structures 711, the test signal loading of the first metal wire 611 can be guaranteed to a large extent.

[0056] In this embodiment, the material of the first through-hole interconnect structure 711 is a metallic material. The metallic material has good conductivity, which is beneficial to improving the electrical connection performance between the first metal line 611 and the external interconnect structure, and correspondingly, it is beneficial to improve the accuracy of the test results.

[0057] In this embodiment, the material of the first through-hole interconnect structure 711 includes one or more of copper, aluminum, and copper alloys.

[0058] In this embodiment, on the top of the metal plate 641, on the extension line of each of the second metal wires 631, the number of the second through-hole interconnection structures 721 is 2 to 5.

[0059] In this embodiment, on the top of the metal plate 641, on the extension line of each of the second metal wires 631, there are 3 second through-hole interconnect structures 721.

[0060] Specifically, the second through-hole interconnect structure 721 is similar to the first through-hole interconnect structure 211 described above, and will not be repeated here.

[0061] Figures 5 to 23 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming the test structure of the present invention.

[0062] refer to Figure 5 A substrate 100 is provided, on which a first dielectric layer 200 is formed, the substrate 100 being disposed along a first direction (e.g., ...). Figure 5 (As shown in the X direction) includes a test area 100T, a first lead area 100V1 located on one side of the test area 100T, and a second lead area 100V2 located on the other side of the test area 100T. Both the first lead area 100V1 and the second lead area 100V2 are used to load test signals.

[0063] In this embodiment, the test structure includes a TDDB test structure or a VBD test structure.

[0064] As an example, the test structure is the TDDB test structure.

[0065] In this embodiment, the substrate 100 includes a substrate structure layer (not shown), and the substrate structure layer includes a substrate (not shown). Taking a planar semiconductor structure as an example, the substrate is a planar substrate. Specifically, the substrate is a silicon substrate. In other embodiments, the substrate material can also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate, etc., and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, etc. In other embodiments, when the test structure is a three-dimensional semiconductor structure, the substrate can also be a substrate with fins.

[0066] The substrate structure layer may also include other structures, such as gate structures, doped regions, shallow trench isolation structures, and dielectric layers, in which devices (e.g., MOS transistors or SRAM devices) are formed. Specifically, the substrate structure layer also includes an interlayer dielectric layer (not shown) formed on the substrate and contact hole plugs (not shown) formed in the interlayer dielectric layer.

[0067] In this embodiment, a first dielectric layer 200 is formed on the substrate 100.

[0068] In this embodiment, the first dielectric layer 200 is a metal interlayer dielectric layer, and the first dielectric layer 200 is used to achieve electrical isolation between metal interconnect structures in the back-end process.

[0069] Therefore, the material of the first dielectric layer 200 is a low-k dielectric material or an ultra-low-k dielectric material. In this embodiment, the material of the first dielectric layer 200 includes one or more of SiOC, SiOCH, SiC, SiCN, SiO2, SiN, and SiON. In this embodiment, the material of the first dielectric layer 200 is an ultra-low-k dielectric material, thereby reducing the parasitic capacitance between the subsequent metal interconnect structures and thus reducing the subsequent RC delay. Specifically, the ultra-low-k dielectric material can be SiOCH.

[0070] The test area 100T serves as the TDDB test area, and both the first lead area 100V1 and the second lead area 100V2 are used to load test signals.

[0071] Specifically, metal lines are subsequently formed in the first dielectric layer 200. During the TDDB test, a test signal is applied to the metal lines of the first lead region 100V1 and the second lead region 100V2, and the dielectric breakdown lifetime between adjacent metal lines in the test region 100T is tested.

[0072] In this embodiment, a hard mask material layer 300 is also formed on the first dielectric layer 200.

[0073] The hard mask material layer 300 is used to subsequently form a hard mask layer, thereby transferring patterns to the first dielectric layer 200 using the hard mask layer.

[0074] The hard mask material layer 300 is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, titanium oxide, and titanium nitride, meaning the hard mask material layer 300 can be a single-layer structure or a multilayer structure. As an example, the hard mask material layer 300 is made of silicon nitride, meaning the hard mask material layer 300 is a single-layer structure.

[0075] Continue to refer to Figure 5 This forms a core layer 400 covering the first dielectric layer 100.

[0076] Specifically, the core layer 400 covers the hard mask material layer 300.

[0077] The core layer 400 provides a process platform for the subsequent formation of the first trench and the second trench, thereby transmitting the pattern downwards using the graphical core layer 400. The first trench defines the pattern and location of the subsequently formed first interconnect opening, and the second trench defines the pattern and location of the subsequently formed second interconnect opening, which correspondingly improves the pattern accuracy of the first and second interconnect openings.

[0078] In addition, sidewalls will be formed on the side walls of the first trench, and the core layer 400 will also provide support for the formation of the sidewalls.

[0079] The core layer 400 will be removed subsequently. Therefore, the material of the core layer 400 is one that is easy to remove, thereby reducing the difficulty of removing the core layer 400 and minimizing damage to other films located below the core layer 400. Therefore, the material of the core layer 400 includes one or more of amorphous silicon, polycrystalline silicon, monocrystalline silicon, silicon oxide, advanced patterning film (APF) materials, spin-on carbon (SOC), and silicon carbide. In this embodiment, the core layer 400 is amorphous silicon (a-Si).

[0080] Reference Figure 6 and Figure 7 , Figure 6 This is a cross-sectional view along the first direction. Figure 7 yes Figure 6 The top view shows that the core layer 400 located in the first lead area 100V1 is modified to transform the core layer 400 of the first lead area 100V1 into a shielding layer 410, wherein the etching resistance of the shielding layer 410 is greater than that of the core layer 400.

[0081] If the etching resistance of the shielding layer 410 is greater than that of the core layer 400, then when the core layer 400 is removed in the future, the shielding layer 410 can be retained, and the retained shielding layer 410 can be used as an etching mask for etching the first dielectric layer 200.

[0082] In this embodiment, the modification treatment is performed using an ion implantation process.

[0083] It should be noted that the ion implantation process has advantages such as the ability to uniformly implant ions over a large area, precisely control the doping concentration and distribution of ions, and have good control over the penetration depth of solid materials. In this embodiment, in order to control the position and area of ​​the formed shielding layer 410 and the uniformity of its surface, an ion implantation process is used to form the shielding layer 410 in the core layer 400.

[0084] In this embodiment, the implanted ions used in the ion implantation process include one or more of P, C, B and Ge.

[0085] By implanting one or more ions from P, C, B and Ge, the core layer 400 can be effectively modified into a shielding layer 410 with high etch resistance, so that the shielding layer 410 and the core layer 400 can form a high etch selectivity ratio.

[0086] Reference Figure 8 and Figure 9 , Figure 8 Based on Figure 7 Top view, Figure 9 yes Figure 8 Based on the cross-sectional view along the AA direction, after the modification process, a first trench 420 is formed in the shielding layer 410 of the first lead region 100V1 and the core layer 400 of the test region 100T. The first trench 420 is along the first direction (e.g., Figure 8 Extending along the X direction (as shown in the middle) and along the second direction (as shown in the middle X direction) Figure 8 The two directions are arranged in parallel (as shown in the Y direction), and the second direction is perpendicular to the first direction.

[0087] The first trench 420 is used to define the pattern and position of the subsequently formed first interconnect opening, which helps to improve the pattern accuracy of the first interconnect opening.

[0088] In this embodiment, a dry etching process is used to etch the shielding layer 410 of the first lead area 100V1 and the core layer 400 of the test area 100T to form the first trench 420.

[0089] The shielding layer 410 and the core layer 400 have different etching resistance. The dry etching process can simultaneously etch the shielding layer 410 and the core layer 400, which have different etching resistance. Furthermore, the dry etching process is more directional, which can improve the dimensional accuracy and sidewall quality of the first trench 420.

[0090] Reference Figures 10 to 12 , Figure 10 Based on Figure 9 sectional view, Figure 11 It is a top view. Figure 12 yes Figure 11 Based on the sectional view along the AA direction, a sidewall 500 is formed on the sidewall of the first trench 420.

[0091] The sidewall 500 is used to subsequently isolate the second trench from the first trench 420, preventing the second trench from becoming connected to the first trench 420, and ensuring that the spacing between adjacent second trenches and first trenches 420 meets the designed minimum space. Furthermore, when the patterns of the second trench and first trench 420 are subsequently transferred to the first dielectric layer 200, the sidewall 500 serves as a mask for etching the first dielectric layer 200. In addition, the sidewall 500 is used to adjust the spacing between the second trench and first trench 420 in the second direction.

[0092] The sidewall 500 is made of a material that has etching selectivity with the core layer 400. The material of the sidewall 500 includes one or more of titanium oxide, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide. In this embodiment, the material of the sidewall 500 is titanium oxide.

[0093] It should be noted that this embodiment only illustrates the length of the sidewall 500 along the first direction and the number of the first trench 420 along the second direction. In reality, the second direction may also include... Figure 11 The core layer 400 and sidewalls 500 extend in the Y direction.

[0094] refer to Figure 10 The step of forming the sidewall 500 includes: forming a sidewall material layer 510 covering the top of the core layer 400, the sidewall of the first trench 420, and the bottom of the first trench 420.

[0095] The sidewall material layer 510 is used to form the sidewall 500.

[0096] In this embodiment, the sidewall material layer 510 is formed using atomic layer deposition (ALD).

[0097] The sidewall material layer 510 formed by atomic layer deposition has good thickness uniformity and good step coverage, which enables the sidewall material layer 510 to cover the top of the core layer 400, as well as the bottom and sidewall of the first trench 420 in good shape preservation.

[0098] In this embodiment, the material of the sidewall material layer 510 includes one or more of titanium oxide, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide, and is used to directly form the sidewall 500.

[0099] Reference Figure 11 and Figure 12 Remove the sidewall material layer 510 located at the top of the core layer 400 and the bottom of the first trench 420, and retain the sidewall material layer 510 located on the sidewall of the first trench 420 as the sidewall 500.

[0100] Removing the sidewall material layer 510 located at the top of the core layer 400 and the bottom of the first trench 420 can better expose the top surface of the core layer 400, thereby reducing the difficulty of the subsequent removal of the core layer 400 and preparing for the subsequent transfer of patterns using the sidewall 500 as an etching mask.

[0101] In this embodiment, a dry etching process is used to remove the sidewall material layer 510 located at the top of the core layer 400 and the bottom of the first trench 420.

[0102] The dry etching process has the characteristics of anisotropic etching. Therefore, by selecting the dry etching process, it is beneficial to reduce the damage to the sidewall 500 and the first dielectric layer 200. At the same time, the dry etching is more directional, which is beneficial to improve the sidewall morphology quality and dimensional accuracy of the sidewall 500.

[0103] Reference Figure 13 and Figure 14 , Figure 13 It is a top view. Figure 14 yes Figure 13 Based on the sectional view along the AA direction, after forming the sidewall 500, the remaining core layer 400 located in the test area 100T and the second lead area 100V2 is removed to form a comb-shaped second groove 450. The second groove 450 includes a comb tooth groove 430 located in the test area 100T and a comb handle groove 440 located in the second lead area 100V2. The comb handle groove 440 extends along the second direction, and the comb tooth groove 430 and the first groove 420 are alternately arranged in the second direction.

[0104] Subsequently, a first metal line, a second metal line, and a metal plate are formed in the first dielectric layer 200. The first metal line is formed at the corresponding position of the first trench 420, the second metal line is formed at the corresponding position of the comb tooth groove 430, and the metal plate is formed at the corresponding position of the comb handle groove 440. In the method for forming the test structure provided in this embodiment, the first metal line and the second metal line only appear together in the test area 100T, the first lead area 100V1 only contains the first metal line, and the second lead area 100V2 only contains the metal plate. When testing the dielectric breakdown lifetime or the breakdown voltage related to the test time, the dielectric breakdown lifetime of the minimum interval is used as the test lifetime. Then, the test structure described in this embodiment is tested. At this time, there is no voltage difference between the first metal lines located in the first lead area 100V1, and the second lead area 100V2 only has a metal plate and no dielectric. Therefore, the first lead area 100V1 and the second lead area 100V2 will not be included in the test. Only the dielectric breakdown lifetime between adjacent first metal lines and second metal lines located in the test area will be tested. The test structure usually uses a through-hole interconnect structure to load the test signal on the first metal lines and second metal lines. In this way, when testing the dielectric breakdown lifetime between adjacent first metal lines and second metal lines, the influence of the through-hole interconnect structure on the test structure is reduced, the probability of test error caused by the presence of the through-hole interconnect structure is reduced, and the accuracy of the test results is improved.

[0105] Furthermore, in this embodiment, the core layer 400 of the first lead region 100V1 is modified to obtain a shielding layer 410 with a higher etch resistance than the core layer 400. When the core layer 400 is removed, the shielding layer 410 can be retained, and only the remaining core layer 400 located in the test region 100T and the second lead region 100V2 is removed. The retained shielding layer 410 and the sidewall 500 together serve as an etching mask for etching the first dielectric layer 200, thereby forming a comb-shaped second trench 450.

[0106] The second trench 450 is used to define the shape, size, and position of the second interconnect opening subsequently formed in the first dielectric layer 200. This embodiment improves the pattern accuracy of the first trench 420 and the second trench 450 by first forming the first trench 420 in the core layer 400 and then using the sidewalls 500 to form the second trench 450. This, in turn, improves the pattern accuracy of the subsequently formed first interconnect opening and second interconnect opening, and consequently improves the accuracy of pattern transfer.

[0107] Furthermore, the formation of the first trench 420 and the second trench 450 in this embodiment is beneficial to improving the process window for forming the first trench 420 and the second trench 450 (e.g., improving the optical proximity effect or alleviating the limitation of photolithography process resolution), ensuring the pattern accuracy of the first trench 420 and the second trench 450, and reducing the spacing between adjacent first trenches 420 and second trenches 450.

[0108] In this embodiment, a maskless etching process is used to remove the core layer 400. The etching selectivity ratios between the core layer 400, the sidewalls 500, the shielding layer 410, and the first dielectric layer 200 are all relatively high. Therefore, the damage to other film layers is minimal during the removal of the core layer 400. Consequently, a maskless etching process can be used to remove the core layer 400, thereby simplifying the process steps and reducing costs. Furthermore, by selecting a maskless etching process, the process window for forming the second trench 450 is significantly increased.

[0109] In this embodiment, a wet etching process is used to remove the remaining core layer 400 located in the test area 100T and the second lead area 100V2. The wet etching process removes the core layer 400 through a chemical reaction, which helps reduce damage to the sidewalls 500 and the first dielectric layer 200, and also helps to completely remove the core layer 400. In this embodiment, the material of the core layer 400 is amorphous silicon, and the etching solution used in the wet etching process is a mixed solution of Cl2 and HBr or a TMAH solution.

[0110] Reference Figures 15 to 18 Using the sidewall 500 and the shielding layer 410 as a mask, the first dielectric layer 200 at the bottom of the first trench 420 and the second trench 450 is etched to form an interconnection opening 260. The interconnection opening 260 includes a first interconnection opening 220 corresponding to the first trench 420 and a second interconnection opening 250 corresponding to the second trench 450. The second interconnection opening 250 includes a first sub-opening 230 located in the test area 100T and a second sub-opening 240 located in the second lead area 100V2.

[0111] Compared with the scheme of forming interconnect openings directly in the first dielectric layer, this scheme is easier to form sidewalls 500 with smaller dimensions in the second direction, and the size and position of the sidewalls 500 are more accurate. This is beneficial to accurately control the pattern accuracy of the interconnect openings 260 and improves the accuracy of pattern transfer.

[0112] The first interconnection opening 220 and the second interconnection opening 250 are used to provide spatial locations for the formation of the first metal structure and the second metal structure, respectively.

[0113] In this embodiment, the first trench 420 and the second trench 450 have high morphological quality, dimensional accuracy and positional accuracy, thereby improving the accuracy of pattern transmission and correspondingly improving the pattern accuracy of the interconnection opening 260. This ensures that the morphology and layout of the subsequently formed metal structure meet the design requirements and improves the performance of the metal structure.

[0114] In this embodiment, a dry etching process is used to etch the first dielectric layer 200 at the bottom of the first trench 420 and the second trench 450 to form an interconnect opening 260.

[0115] The dry etching process has the characteristics of anisotropic etching. Therefore, the dry etching is more directional, which is beneficial to improving the sidewall morphology quality and dimensional accuracy of the interconnect opening 260.

[0116] Specifically, in conjunction with reference Figure 15 and Figure 16 , Figure 15 It is a top view. Figure 16 yes Figure 15 In the step of etching the first dielectric layer 200 at the bottom of the first trench 420 and the second trench 450 using the sidewall 500 and the shielding layer 410 as masks, based on the cross-sectional view along the AA direction, the hard mask material layer 300 is etched using the sidewall 500 and the shielding layer 410 as masks to form the hard mask layer 310.

[0117] Using the sidewall 500 and the shielding layer 410 as masks, the hard mask material layer 300 is etched to form a hard mask layer 310. Compared with the scheme of directly etching the first dielectric layer to form interconnect openings, this scheme achieves pattern transfer by forming a hard mask layer 310, which improves the accuracy of pattern transfer and is beneficial for accurately controlling the pattern accuracy of interconnect openings 260.

[0118] In this embodiment, the hard mask material layer 300 is etched to form a first mask opening 320 corresponding to the first trench 420 and a second mask opening 350 corresponding to the second trench 450. The second mask opening 350 includes a first sub-mask opening 330 located in the test area 100T and a second sub-mask opening 340 located in the second lead area 100V2.

[0119] In this embodiment, the hard mask material layer 300 is etched using a dry etching process to form a hard mask layer 310, which is beneficial to improving the sidewall morphology quality and dimensional accuracy of the first mask opening 320 and the second mask opening 350.

[0120] Reference Figure 17 and Figure 18 , Figure 17 It is a top view. Figure 18 yes Figure 17 Based on the cross-sectional view along the AA direction, using the hard mask layer 310 as a mask, the first dielectric layer 200 is etched to form interconnect openings 260.

[0121] Specifically, the first interconnect opening 220 corresponds to the first mask opening 320, the second interconnect opening 250 corresponds to the second mask opening 350, the first sub-opening 230 corresponds to the first sub-mask opening 330, and the second sub-opening 240 corresponds to the second sub-mask opening 340.

[0122] Reference Figure 19 and Figure 20 , Figure 19 It is a top view. Figure 20 yes Figure 19 A cross-sectional view along the AA direction shows a first metal structure (not shown) formed in the first interconnection opening 220 and a second metal structure (not shown) formed in the second interconnection opening 250. The first metal structure includes a plurality of first metal lines 610 extending in a first direction and arranged parallel to each other in a second direction. The second metal structure includes a second metal line 630 located in the first sub-opening 230 and arranged alternately with the first metal lines 610, and a metal plate 640 located in the second sub-opening 240.

[0123] In this embodiment, the material of the first metal structure includes one or more of copper, aluminum, and copper alloys to achieve good electrical conductivity, and the material of the second metal structure includes one or more of copper, aluminum, and copper alloys to achieve good electrical conductivity.

[0124] In this embodiment, the first metal structure and the second metal interconnect structure are metal structures in the same layer, therefore, the first metal structure and the second metal structure are made of the same material.

[0125] In this embodiment, in the test area 100T, in the second direction, the first dielectric layer 200 retained between adjacent first metal lines 610 and second metal lines 630 is transmitted through the sidewall 500, and the interval between adjacent first metal lines 210 and second metal lines 220 is equal, and the interval is the first interval S1.

[0126] Since the minimum interval dielectric breakdown lifetime is used as the TDDB test lifetime when the test structure is used to test the time-related dielectric breakdown lifetime, in this embodiment, in the test area 100T, the interval between adjacent first metal lines 610 and second metal lines 630 is equal in the second direction. Therefore, when performing the TDDB test, the dielectric breakdown lifetime between adjacent first metal lines 610 and second metal lines 630 can be detected more accurately, and the situation of large error in the detection result caused by different interval sizes between adjacent first metal lines 610 and second metal lines 630 can be avoided to a large extent.

[0127] In this embodiment, in the first direction, the first dielectric layer 200 retained between the end of each first metal wire 610 near the second lead area 100V2 and the metal plate 640 is also transmitted through the sidewall 500. Therefore, the interval between the end of each first metal wire 610 near the second lead area 100V2 and the metal plate 640 is equal, and the interval is the second interval S2.

[0128] Therefore, when performing TDDB testing, the dielectric breakdown lifetime between adjacent first metal lines 610 and metal plates 640 can be detected more accurately, and the error in the test results caused by different spacing sizes between adjacent first metal lines 610 and metal plates 640 can be largely avoided.

[0129] In this embodiment, the first interval S1 is equal to the second interval S2.

[0130] Therefore, in the test structure, the interval between adjacent positions of the first metal structure and the second metal structure is equal everywhere. Thus, when performing TDDB testing, the dielectric breakdown lifetime between the first metal structure and the second metal structure can be detected more accurately, and the situation of large error in the test results caused by the different interval sizes between adjacent positions of the first metal structure and the second metal structure can be avoided to a large extent.

[0131] Reference Figures 21 to 23 , Figure 21 It is a top view. Figure 22 yes Figure 21 Cross-sectional view along the AA direction. Figure 23 a is Figure 21 Cross-sectional view along the BB direction. Figure 23 b is Figure 21 A cross-sectional view along the CC direction shows that after the first metal structure and the second metal structure are formed, a second dielectric layer 700 is formed covering the first dielectric layer 200, the first metal structure, and the second metal structure.

[0132] For ease of illustration, Figure 21The second dielectric layer 700 is not shown.

[0133] The second dielectric layer 700 is used to achieve electrical isolation between metal interconnect structures in the back-end process.

[0134] The description of the material of the second dielectric layer 700 can be found in the foregoing description of the first dielectric layer 200, and will not be repeated here.

[0135] Continue to refer to Figures 21 to 23 A first via interconnect structure 710 is formed in the second dielectric layer 700 of the first lead region 100V1. The first via interconnect structure 710 is located on top of the first metal line 610 and electrically connected to the first metal line 610. The first via interconnect structure 710 is used as a test signal loading terminal of the first metal line 610. A second via interconnect structure 720 is formed in the second dielectric layer 700 of the second lead region 100V2. The second via interconnect structure 720 is located on top of the metal plate 640 and electrically connected to the metal plate 640. The second via interconnect structure 720 is used as a test signal loading terminal of the second metal line 630.

[0136] In this embodiment, the first through-hole interconnect structure 710 and the second through-hole interconnect structure 720 are formed in the same step, which simplifies the process steps and improves the process efficiency.

[0137] In this embodiment, during the formation of the second via interconnect structure 720 in the second dielectric layer 700 of the second lead region 100V2, the second via interconnect structure 720 is located on the extension line of the second metal line 630, thereby not changing the formation position of the second via interconnect structure 720 in the existing process and improving the process compatibility of forming the second via interconnect structure 720.

[0138] Typically, when the first through-hole interconnect structure 710 and the second through-hole interconnect structure 720 are formed, the dimensions of the first through-hole interconnect structure 710 and the second through-hole interconnect structure 720 will expand along the second direction.

[0139] Therefore, in this embodiment, along the second direction, the width w1 of the first through-hole interconnect structure 710 is greater than the width d1 of the first metal line 610. Similarly, along the second direction, the width w2 of the second through-hole interconnect structure 720 is greater than the width d2 of the second metal line 630.

[0140] In other words, the distance between the first through-hole interconnect structure 710 at the top of the first metal line 610 and the adjacent second metal line 630 is less than the distance S1 between the adjacent first metal line 610 and the second metal line 630. Similarly, the distance between the second through-hole interconnect structure 720 on the metal plate 640 and the adjacent first metal line 610 is less than the distance S1 between the adjacent first metal line 610 and the second metal line 630.

[0141] Since there is no voltage difference between the first metal lines 610 in the first lead area 100V1 and no dielectric in the second lead area 100V2 when testing the test structure described in this embodiment, the first lead area 100V1 and the second lead area 100V2 will not be included in the test. Therefore, even if the width w1 of the first via interconnect structure 710 is greater than the width d1 of the first metal line 610, or the width w2 of the second via interconnect structure 720 is greater than the width d2 of the second metal line 630, that is, even if there is a gap smaller than the gap S1 between adjacent first metal lines 610 and second metal lines 630, the probability of test error caused by the gap being smaller than the gap S1 between adjacent first metal lines 610 and second metal lines 630 is still reduced when testing the dielectric breakdown lifetime between adjacent first metal lines 610 and second metal lines 630 using TDDB.

[0142] In this embodiment, the number of first through-hole interconnect structures 710 at the top of each first metal wire 610 is 2 to 5. For an analysis of the number of first through-hole interconnect structures 710, please refer to the corresponding descriptions in the preceding embodiments, which will not be repeated here.

[0143] In this embodiment, there are 3 first through-hole interconnect structures 710 on the top of each first metal wire 610. As long as the forming process is simple, the first metal wire 610 is successfully connected as long as one of the first through-hole interconnect structures 710 is successfully connected. Therefore, by using 3 first through-hole interconnect structures 710, the test signal loading of the first metal wire 610 can be guaranteed to a large extent.

[0144] In this embodiment, the material of the first through-hole interconnect structure 710 is a metallic material. The metallic material has good conductivity, which is beneficial for improving the electrical connection performance between the first metal line 610 and the external interconnect structure, and consequently, for improving the accuracy of the test results.

[0145] In this embodiment, the material of the first through-hole interconnect structure 710 includes one or more of copper, aluminum, and copper alloys.

[0146] Accordingly, in this embodiment, on the top of the metal plate 640, on the extension line of each of the second metal wires 630, the number of the second through-hole interconnection structures 720 is 2 to 5.

[0147] In this embodiment, on the top of the metal plate 640, on the extension line of each of the second metal wires 630, there are 3 second through-hole interconnect structures 720.

[0148] In this embodiment, the second through-hole interconnect structure 720 is similar to the first through-hole interconnect structure 710 described above, and will not be repeated here.

[0149] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A test structure, characterized in that, include: The substrate includes a test area, a first lead area located on one side of the test area, and a second lead area located on the other side of the test area along a first direction, wherein both the first lead area and the second lead area are used to load test signals; A dielectric layer is located on the substrate; A first metal structure is located in the dielectric layer. The first metal structure includes a plurality of first metal lines extending along the first direction and arranged parallel to the second direction, wherein the second direction is perpendicular to the first direction. The comb-shaped second metal structure includes multiple comb-tooth-shaped second metal wires and a comb-handle-shaped metal plate. The second metal wires are located in the test area, extending along the first direction and arranged parallel to each other along the second direction. The metal plate is located in the second lead area and extends along the second direction. The second metal wires and the first metal wires are alternately arranged in the second direction. The first metal wires and the second metal wires only appear together in the test area. Only the first metal wires exist in the first lead area, and only the metal plate exists in the second lead area. The test structure further includes: a first through-hole interconnect structure located in the first lead area and on top of the first metal wire, and electrically connected to the first metal wire, wherein the first through-hole interconnect structure is used as a test signal loading end of the first metal wire; The second through-hole interconnect structure is located in the second lead area and on the top of the metal plate, and is electrically connected to the metal plate. The second through-hole interconnect structure is used as the test signal loading end of the second metal wire. The first metal line, the second metal line, and the metal plate are metal interconnects on the same layer; the dielectric layer includes a first dielectric layer and a second dielectric layer covering the first metal structure and the second metal structure, and the first via interconnect structure and the second via interconnect structure are located in the second dielectric layer.

2. The test structure as described in claim 1, characterized in that, In the test area, in the second direction, the spacing between adjacent first metal lines and second metal lines is equal, and the spacing is a first spacing; In the first direction, the interval between the end of each first metal wire near the second lead area and the metal plate is equal, and the interval is the second interval; The first interval is equal to the second interval.

3. The test structure as described in claim 1, characterized in that, The second through-hole interconnect structure is located on the extension of the second metal line.

4. The test structure as described in claim 3, characterized in that, At the top of each of the first metal wires, the number of the first through-hole interconnect structures is 2 to 5; On the top of the metal plate, on the extension line of each of the second metal wires, the number of the second through-hole interconnect structures is 2 to 5.

5. The test structure as described in claim 1, characterized in that, Along the second direction, the width dimension of the first through-hole interconnect structure is greater than the width dimension of the first metal line; Along the second direction, the width dimension of the second through-hole interconnect structure is greater than the width dimension of the second metal line.

6. The test structure as described in claim 1, characterized in that, The dielectric layer material includes one or more of SiOC, SiOCH, SiC, SiCN, SiO2, SiN, and SiON.

7. The test structure as described in claim 1, characterized in that, The material of the first metal structure includes one or more of copper, aluminum, and copper alloys, and the material of the second metal structure includes one or more of copper, aluminum, and copper alloys.

8. The test structure as described in claim 1, characterized in that, The test structure includes either the TDDB test structure or the VBD test structure.

9. A method for forming a test structure, characterized in that, include: A substrate is provided on which a first dielectric layer is formed. The substrate includes a test region, a first lead region located on one side of the test region, and a second lead region located on the other side of the test region along a first direction. Both the first lead region and the second lead region are used to load test signals. A core layer covering the first dielectric layer is formed; The core layer located in the first lead region is modified to transform the core layer of the first lead region into a shielding layer. The etch resistance of the shielding layer is greater than that of the core layer. In the step of modifying the core layer located in the first lead region, the modification is performed using an ion implantation process. After the modification process is performed, a first trench is formed in the shielding layer of the first lead area and the core layer of the test area. The first trench extends along the first direction and is arranged parallel to the second direction, which is perpendicular to the first direction. A sidewall is formed on the sidewall of the first trench; wherein, an atomic layer deposition process is used to form a sidewall material layer covering the top of the core layer, the sidewall of the first trench, and the bottom of the first trench; After the sidewalls are formed, the remaining core layer located in the test area and the second lead area is removed by a maskless etching process and a wet etching process to form a comb-shaped second trench. The second trench includes a comb tooth groove located in the test area and a comb handle groove located in the second lead area. The comb handle groove extends along the second direction, and the comb tooth groove and the first trench are alternately arranged in the second direction. Using the sidewall and shielding layer as a mask, the first dielectric layer at the bottom of the first trench and the second trench is etched to form an interconnection opening. The interconnection opening includes a first interconnection opening corresponding to the first trench and a second interconnection opening corresponding to the second trench. The second interconnection opening includes a first sub-opening located in the test area and a second sub-opening located in the second lead area. A first metal structure is formed in the first interconnection opening, and a second metal structure is formed in the second interconnection opening. The first metal structure includes a plurality of first metal lines extending in a first direction and arranged in parallel in a second direction. The second metal structure includes a second metal line located in the first sub-opening and arranged alternately with the first metal lines, and a metal plate located in the second sub-opening. Wherein, after the first metal structure and the second metal structure are formed, a second dielectric layer is formed covering the first dielectric layer, the first metal structure and the second metal structure. A first via interconnect structure is formed in the second dielectric layer of the first lead area. The first via interconnect structure is located on the top of the first metal wire and is electrically connected to the first metal wire. The first via interconnect structure is used as a test signal loading end of the first metal wire. A second via interconnect structure is formed in the second dielectric layer of the second lead region. The second via interconnect structure is located on the top of the metal plate and is electrically connected to the metal plate. The second via interconnect structure is used as a test signal loading terminal for the second metal wire.

10. The method for forming the test structure as described in claim 9, characterized in that, The step of forming the sidewall includes: forming a sidewall material layer covering the top of the core layer, the sidewall of the first trench, and the bottom of the first trench; Remove the sidewall material layer located at the top of the core layer and the bottom of the first trench, and retain the sidewall material layer located on the sidewall of the first trench as the sidewall.

11. The method for forming the test structure as described in claim 9, characterized in that, The ion implantation process uses one or more of P, C, B, and Ge as implanted ions.

12. The method for forming the test structure as described in claim 9, characterized in that, The first trench is formed by etching the core layer of the first lead area and the test area using a dry etching process.

13. The method for forming the test structure as described in claim 9, characterized in that, During the formation of the second via interconnect structure in the second dielectric layer of the second lead region, the second via interconnect structure is located on the extension line of the second metal line.

14. The method for forming the test structure as described in claim 9, characterized in that, In the step of providing the substrate, a hard mask material layer is also formed on the first dielectric layer; In the step of etching the first dielectric layer at the bottom of the first trench and the second trench using the sidewall and shielding layer as a mask, the hard mask material layer is etched using the sidewall and shielding layer as a mask to form a hard mask layer. Using the hard mask layer as a mask, the first dielectric layer is etched to form interconnect openings.

15. The method for forming the test structure as described in claim 9, characterized in that, The first dielectric layer at the bottom of the first trench and the second trench is etched using a dry etching process to form the interconnect opening.

16. The method for forming the test structure as described in claim 9, characterized in that, The sidewall material includes one or more of titanium oxide, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide.

17. The method for forming a test structure as described in claim 9, wherein the test structure includes a TDDB test structure or a VBD test structure.

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