Method for manufacturing semiconductor structure and semiconductor structure

Abstract

An embodiment of the present invention provides a method for manufacturing a semiconductor structure and a semiconductor structure. The method includes: providing a substrate having a first contact layer and a second contact layer therein; forming an initial electrical connection layer; forming a lower mask layer, the lower mask layer including adjacent first pattern areas and a second pattern area; on the upper surface of the substrate, the orthographic projections of the two first contact layers fall within the orthographic projection of a first pattern area, and the orthographic projection of a second contact layer falls within the orthographic projection of a second pattern area; patterning the first pattern area to form two mutually discrete first sub-pattern areas; and etching the initial electrical connection layer to form mutually discrete first and second electrical connection layers, the first electrical connection layer corresponding to the first sub-pattern area, and the second electrical connection layer corresponding to the second pattern area. The embodiments of the present invention can reduce the risk of short circuits within the semiconductor structure.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductors, and in particular to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Art

[0002] Memory is a common semiconductor structure. It is a memory component used to store programs and various data information. It typically includes structures such as active areas, bit lines, and word lines. These structures must be connected to the control circuit through contact layers and electrical connection layers.

[0003] However, during the process steps of forming the contact layer and the electrical connection layer, a short circuit problem may easily occur inside the semiconductor structure. Summary of the Invention

[0004] Embodiments of the present invention provide a method for manufacturing a semiconductor structure and a semiconductor structure, so as to reduce the risk of short circuits occurring inside the semiconductor structure.

[0005] To solve the above problems, an embodiment of the present invention provides a method for manufacturing a semiconductor structure, comprising: providing a substrate having at least two mutually separate first contact layers and at least one second contact layer therein; forming an initial electrical connection layer, the initial electrical connection layer being electrically connected to the first contact layer and the second contact layer; forming a lower mask layer, the lower mask layer comprising at least one mutually separate first pattern area and at least one second pattern area, the first pattern area being adjacent to the second pattern area; on the upper surface of the substrate, the orthographic projections of two first contact layers fall within the orthographic projection of one first pattern area, and the orthographic projection of one second contact layer falls within the orthographic projection of one second pattern area; patterning the first pattern area to form two mutually separate first sub-pattern areas, wherein one first sub-pattern area is located between the second pattern area and another first sub-pattern area; on the upper surface of the substrate, the orthographic projection of one first contact layer falls within the orthographic projection of one first sub-pattern area; and etching the initial electrical connection layer to form mutually separate first and second electrical connection layers, each first electrical connection layer corresponding to one first sub-pattern area, and each second electrical connection layer corresponding to one second pattern area.

[0006] In addition, the step of forming the lower mask layer includes: forming an initial lower mask layer on the initial electrical connection layer; forming a number of separate upper mask layers on the initial lower mask layer, the upper mask layer including an initial first pattern area; forming a sidewall layer on the sidewall of the upper mask layer; forming a sacrificial layer between adjacent upper mask layers, the sacrificial layer also contacting the sidewall layer, the sacrificial layer including an initial second pattern area; removing the sidewall layer; using the upper mask layer and the sacrificial layer as masks, etching the initial lower mask layer to form the lower mask layer, wherein the first pattern area corresponds to the initial first pattern area, and the second pattern area corresponds to the initial second pattern area.

[0007] In addition, the steps of forming the side wall layer and the sacrificial layer include: forming an initial side wall layer on the surface of the upper mask layer and the upper surface of the initial lower mask layer between the adjacent upper mask layers; forming an initial sacrificial layer covering the initial side wall layer; removing the initial sacrificial layer and the initial side wall layer above the upper mask layer, and the remaining initial sacrificial layer serves as the sacrificial layer, and the remaining initial side wall layer serves as the side wall layer; removing the side wall layer, specifically including: removing the side wall layer located on the side wall of the upper mask layer, and retaining the side wall layer located on the upper surface of the initial lower mask layer; the side wall layer located on the upper surface of the initial lower mask layer and the sacrificial layer form a stacked structure; etching the initial lower mask layer using the upper mask layer and the sacrificial layer as masks, specifically including: etching the initial lower mask layer using the upper mask layer and the stacked structure as masks.

[0008] In addition, the method of forming the initial spacer layer includes an atomic layer deposition process.

[0009] In addition, the step of forming the lower mask layer includes: forming an initial lower mask layer on the initial electrical connection layer; etching the initial lower mask layer to form a plurality of mutually separate first lower mask layers; forming a second lower mask layer on the side wall of the first lower mask layer, and the second lower mask layer and the first lower mask layer constitute the lower mask layer.

[0010] In addition, the material of the second lower mask layer is the same as that of the initial lower mask layer.

[0011] In addition, the step of truncating the first pattern area includes: forming a middle mask layer covering the lower mask layer; patterning the middle mask layer to form an isolation trench located in the middle mask layer; and truncating the first pattern area along the isolation trench to form the first sub-pattern area.

[0012] In addition, the distance between adjacent first sub-pattern areas is 30 nm to 50 nm.

[0013] In addition, the distance between adjacent first pattern areas and second pattern areas is 20 nm to 30 nm.

[0014] In addition, before forming the lower mask layer, the method further includes: forming a bottom mask layer on the initial electrical connection layer, and the lower mask layer is also located on the bottom mask layer.

[0015] An embodiment of the present invention also provides a semiconductor structure, comprising: a substrate, wherein the substrate has at least two first contact layers and at least one second contact layer separated from each other; the substrate has at least two first electrical connection layers and at least one second electrical connection layer separated from each other; a first electrical connection layer is located between a second electrical connection layer and between another first electrical connection layer; on the upper surface of the substrate, the orthographic projection of each first contact layer falls within the orthographic projection of a first electrical connection layer, and the orthographic projection of each second contact layer falls within the orthographic projection of a second electrical connection layer; and each first electrical connection layer is electrically connected to a first contact layer; and each second electrical connection layer is electrically connected to a second contact layer.

[0016] In addition, the distance between two adjacent first electrical connection layers is 30 nm to 50 nm.

[0017] In addition, the distance between the adjacent first electrical connection layer and the second electrical connection layer is 20 nm to 30 nm.

[0018] In addition, in the arrangement direction of the first electrical connection layers, the distance between adjacent first electrical connection layers and the second contact layers is 20 nm to 55 nm.

[0019] In addition, in the arrangement direction of the first electrical connection layers, the widths of the two first electrical connection layers are the same.

[0020] Compared with the prior art, the technical solution provided by the embodiment of the present invention has the following advantages:

[0021] In an embodiment of the present invention, a lower mask layer including a first pattern area and a second pattern area is formed; the first pattern area is truncated to form two separate first sub-pattern areas; on the upper surface of the substrate, the orthographic projection of a first contact layer falls within the orthographic projection of one of the first sub-pattern areas; and using the lower mask layer as a mask, the initial electrical connection layer is etched to form a first electrical connection layer and a second electrical connection layer, with the first electrical connection layer corresponding to the first sub-pattern area and the second electrical connection layer corresponding to the second pattern area. That is, a first pattern area is first formed to combine the patterns of the two first electrical connection layers. Compared to patterns corresponding to only one first electrical connection layer, the first pattern area has a larger process window, reserving sufficient space for the first electrical connection layer, which is prone to short circuits, thereby increasing the distance between the first electrical connection layer and the adjacent second contact layer.

[0022] In addition, the distance between the adjacent first pattern area and the second pattern area is 20nm to 30nm. When the distance between the first pattern area and the second pattern area is within the above range, the distance between the second contact layer and the subsequently formed first electrical connection layer can be increased, thereby avoiding short circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0024] Figures 1-4 It is a structural schematic diagram corresponding to each step in a method for manufacturing a semiconductor structure;

[0025] Figure 5-Figure 19 This is a schematic structural diagram corresponding to each step in the method for manufacturing a semiconductor structure provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0026] As known from the background art, during the process steps of forming the contact layer and the electrical connection layer, there is a problem that short circuits are easily generated inside the semiconductor structure. Figures 1-4 A schematic diagram of the structure corresponding to each step in a method for manufacturing a semiconductor structure, referring to Figure 1 The semiconductor structure includes a substrate 100, a first contact layer 121 and a second contact layer 122 located within the substrate 100, and an initial electrical connection layer 130 located on the surface of the substrate 100. A portion of the initial electrical connection layer 130 will be etched later. Specifically, a patterned mask layer can be formed on the initial electrical connection layer 130, and the initial electrical connection layer 130 is etched using the patterned mask layer as a mask. Typically, two patterning steps are performed to form the final patterned mask layer.

[0027] Further, refer to Figure 2 , Figure 2 FIG. 1 is a top view of the semiconductor structure after the first patterning process, wherein the first patterning process forms at least two mutually separated first pattern areas 111 . Each first contact layer 121 corresponds to one first pattern area 111 .

[0028] refer to Figure 3 , Figure 3 This is a top view of the semiconductor structure after the second patterning process. The second patterning process forms a third pattern area 113 between the two first pattern areas 111 and forms a second pattern area 112 adjacent to the first pattern area 111. Each second contact layer 122 corresponds to a second pattern area 112.

[0029] It is understandable that since the design size of the first pattern area 111 and the second pattern area 112 is relatively small, the process window is correspondingly small. During the photolithography process, interference problems are likely to occur due to the small light spacing, and alignment errors are also likely to occur, thereby causing the actual size or actual position of the first pattern area 111 and the second pattern area 112 to change.

[0030] refer to Figure 4 , Figure 4 is a local cross-sectional view, and the cross-sectional direction is Figure 3 In the B-B1 direction shown, the initial electrical connection layer 130 is etched using the patterned mask layer as a mask (refer to Figure 1 ) to form a first electrical connection layer 131, a second electrical connection layer 132 and a third electrical connection layer 133, the first electrical connection layer 131 corresponds to the first pattern area 111 (reference Figure 3 ), the second electrical connection layer 132 corresponds to the second pattern area 112 (reference Figure 3 ), the third electrical connection layer 133 corresponds to the third pattern area 113 (reference Figure 3 The portion of the third electrical connection layer 133 that is not in use may be removed later.

[0031] Since the actual size or actual position of the first pattern area 111 and the second pattern area 112 is easy to change, the size and position of the adjacent first electrical connection layer 131 and the second electrical connection layer 132 are also easy to change. For example, the distance between the first electrical connection layer 131 and the adjacent second contact layer 122 is too close, which makes it easy for a short circuit to occur. In addition, in the process of etching the initial electrical connection layer 130, it is also easy to remove part of the second contact layer 122, that is, on the upper surface of the substrate 100, the orthographic projection of the second contact layer 122 does not completely fall within the orthographic projection of the second electrical connection layer 132, thereby reducing the contact area between the second contact layer 122 and the second electrical connection layer 132 and increasing the contact resistance.

[0032] To address the aforementioned issues, an embodiment of the present invention provides a method for manufacturing a semiconductor structure, comprising: forming a lower mask layer, the lower mask layer comprising a first pattern region and a second pattern region that are mutually separate; truncating the first pattern region to form two mutually separate first sub-pattern regions; positioning an orthographic projection of a first contact layer on the upper surface of the substrate so that the orthographic projection of the first sub-pattern region falls within the orthographic projection of the first sub-pattern region; and etching an initial electrical connection layer to form a first electrical connection layer and a second electrical connection layer that are mutually separate, wherein the first electrical connection layer corresponds one-to-one with the first sub-pattern region, and the second electrical connection layer corresponds one-to-one with the second pattern region. That is, the first pattern region combines the two first sub-pattern regions. Therefore, the first pattern region has a larger process window, which can reduce the impact of interference or alignment errors on pattern size and position. It also reserves sufficient space for the first electrical connection layer, which is prone to short circuits, thereby increasing the distance between the second contact layer and the adjacent first electrical connection layer. Furthermore, patterning the first pattern region can form two independent first electrical connection layers. In other words, in this embodiment of the present invention, the pattern design and formation method of the first electrical connection layer are optimized, thereby reducing the risk of short circuits within the semiconductor structure.

[0033] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more apparent, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the embodiments of the present invention to help readers better understand the present application. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0034] An embodiment of the present invention provides a method for manufacturing a semiconductor structure. Figure 5-Figure 19 The structural schematic diagrams corresponding to each step in the method for manufacturing the semiconductor structure provided in this embodiment will be described in detail below with reference to the accompanying drawings.

[0035] refer to Figure 5 , providing a substrate 200 having at least two first contact layers 221 and at least one second contact layer 222 separated from each other.

[0036] In this embodiment, the substrate 200 has a two-layer structure, including a substrate 201 and a cover layer 202. The materials of the substrate 201 and the cover layer 202 can be insulating materials. For example, the substrate 201 can be made of silicon oxide, and the cover layer 202 can be made of silicon nitride. In other embodiments, the substrate can also have a single-layer structure, or a structure with three or more layers. The substrate 200 can also have structures such as active regions, word lines, or bit lines. The active regions, word lines, or bit lines are electrically connected to the first contact layer 221, the second contact layer 222, or other contact layers.

[0037] It is worth mentioning that Figure 5 is a partial cross-sectional view of a semiconductor. Figure 5 The cross section shown has only one first contact layer 221, and other cross sections may have additional first contact layers 221. The first contact layer 221 and the second contact layer 222 are also connected to a control circuit formed subsequently to control structures such as active areas, word lines, or bit lines within the substrate 200.

[0038] In this embodiment, the material of the first contact layer 221 and the material of the second contact layer 222 are conductive materials, and the two materials are the same, such as tungsten, copper, or polysilicon, etc. In other embodiments, the materials of the first contact layer and the second contact layer may also be different.

[0039] Continue to refer Figure 5 , an initial electrical connection layer 230 is formed on the substrate 200 , and the initial electrical connection layer 230 is electrically connected to the first contact layer 221 and the second contact layer 222 .

[0040] The initial electrical connection layer 230 can be formed in the same process step as the first contact layer 221 and the second contact layer 222, or can be formed in two separate process steps. In this embodiment, the initial electrical connection layer 230 is formed by physical vapor deposition. In other embodiments, the initial electrical connection layer can also be formed by chemical vapor deposition.

[0041] The material of the initial electrical connection layer 230 is a conductive material. In this embodiment, the material of the initial electrical connection layer 230 is the same as the material of the first contact layer 221 and the second contact layer 222, such as tungsten, copper, or polysilicon. In other embodiments, the material of the initial electrical connection layer may be different from the material of the first contact layer and the second contact layer.

[0042] refer to Figure 5-Figure 14 A lower mask layer 21 is formed on the initial electrical connection layer, and the lower mask layer 21 includes at least one first pattern area 211 and at least one second pattern area 212 that are separate from each other, and the first pattern area 211 is adjacent to the second pattern area 212; on the upper surface of the substrate 200, the orthographic projections of the two first contact layers 221 fall within the orthographic projection of one first pattern area 211, and the orthographic projection of one second contact layer 222 falls within the orthographic projection of one second pattern area 212.

[0043] The lower mask layer 21 serves as a mask for subsequently etching the initial electrical connection layer 230 to form a first electrical connection layer and a second electrical connection layer. Furthermore, the first pattern area 211 will subsequently be divided into two first sub-pattern areas, each corresponding to the two first electrical connection layers to be formed. The second pattern area 212 corresponds to the second electrical connection layer. In other words, in this embodiment, the patterns of the two first electrical connection layers are merged. This increases the process window for the first electrical connection layers, thereby facilitating a larger distance between the second contact layer and the adjacent first electrical connection layer, thereby preventing short circuits between the two layers.

[0044] In this embodiment, the lower mask layer 21 is formed by a double patterning process. The steps of forming the lower mask layer 21 will be described in detail below.

[0045] refer to Figure 5 , a bottom mask layer 240 , a stop layer 250 and an initial lower mask layer 210 are stacked and formed on the initial electrical connection layer 230 .

[0046] The bottom mask layer 240 and the stop layer 250 help improve pattern transfer accuracy. The bottom mask layer 240 can be made of silicon carbide, silicon carbonitride, or silicon oxycarbide, among others. The stop layer 250 can be made of silicon nitride or silicon oxynitride, among others. The initial lower mask layer 210 can be made of silicon oxide or silicon oxycarbide, among others. The bottom mask layer 240, the stop layer 250, and the initial lower mask layer 210 can be formed using chemical vapor deposition.

[0047] In other embodiments, the bottom mask layer and the stop layer may not be formed.

[0048] Combined with reference Figure 6 and Figure 8 A plurality of upper mask layers 26 separated from each other are formed on the initial lower mask layer 210. The upper mask layer 26 includes an initial first pattern area 261. The initial first pattern area 261 has the same shape as the first pattern area formed subsequently.

[0049] Specifically, refer to Figure 6 , an initial upper mask layer 260 is formed on the initial lower mask layer 210 to cover the entire surface.

[0050] In this embodiment, initial upper mask layer 260 has a dual-layer structure, including a stacked initial first upper mask layer 262 and an initial second upper mask layer 263. Initial first upper mask layer 262 can resist reflection and standing waves, thereby improving pattern accuracy. In other embodiments, the initial upper mask layer can have a single-layer structure, for example, including only the initial first upper mask layer or the initial second upper mask layer.

[0051] The material of the initial first upper mask layer 262 can be silicon carbide, silicon carbonitride, or silicon oxycarbide, etc. The material of the initial second upper mask layer 263 can be silicon nitride or silicon oxynitride, etc. The initial first upper mask layer 262 and the initial second upper mask layer 263 can be formed by chemical vapor deposition.

[0052] refer to Figure 7-Figure 8 , Figure 8 Top view, Figure 7 for Figure 8 The local cross-sectional view in the A-A1 direction shows that a portion of the initial upper mask layer 260 is etched (refer to Figure 6 ), the remaining initial upper mask layer 260 serves as the upper mask layer 26. The upper mask layer 26 includes a first upper mask layer 264 and a second upper mask layer 265.

[0053] The upper mask layer 26 includes an initial first pattern area 261. In this embodiment, the upper mask layer 26 also includes an initial third pattern area 266, and the space between the initial first pattern area 261 and the initial third pattern area 266 can be used to subsequently form the initial second pattern area. In other embodiments, the upper mask layer may only have the initial first pattern area, or may also have other pattern areas in addition to the initial first pattern area and the initial third pattern area.

[0054] Further references Figure 8 The orthographic projections of the two first contact layers 221 on the upper surface of the substrate 200 fall within the orthographic projection of one initial first pattern area 261 on the upper surface of the substrate 200 . In other words, one initial first pattern area 261 corresponds to two first contact layers 221 .

[0055] refer to Figures 9-11 A spacer layer 27 is formed on the sidewall of the upper mask layer 26 ; a sacrificial layer 28 is formed between adjacent upper mask layers 26 , the sacrificial layer 28 is also in contact with the spacer layer 27 , and the sacrificial layer 28 includes an initial second pattern area 282 .

[0056] The steps of forming the sidewall layer 27 and the sacrificial layer 28 will be described in detail below.

[0057] refer to Figure 9 Initial spacers 270 are formed on the surface of the upper mask layer 26 and the upper surface of the initial lower mask layer 210 between adjacent upper mask layers 26. That is, initial spacers 270 are formed on the upper mask layer 26 and the initial lower mask layer 210 to conformally cover the initial spacers.

[0058] In this embodiment, the method for forming the initial spacer layer 270 includes an atomic layer deposition process. The atomic layer deposition process can ensure that the initial spacer layer 270 has a uniform thickness, thereby ensuring the pattern accuracy of the subsequently formed first pattern area and second pattern area. The material of the initial spacer layer 270 is different from that of the upper mask layer 26. For example, the material of the initial spacer layer 261 can be silicon oxide.

[0059] refer to Figure 10 , forming an initial sacrificial layer 280 covering the initial spacer layer 270. The initial sacrificial layer 280 may be formed by chemical vapor deposition. The material of the initial sacrificial layer 280 is different from that of the initial spacer layer 270, for example, the material of the initial sacrificial layer 280 may be silicon carbide or silicon nitride.

[0060] As can be seen from the foregoing, in this embodiment, the initial spacer layer 270 is not etched before forming the initial sacrificial layer 280, thereby simplifying the production process. In other embodiments, the initial spacer layer may be etched before forming the initial sacrificial layer to remove the initial spacer layer located on the upper surface of the initial lower mask layer and the upper surface of the upper mask layer, thereby retaining the initial spacer layer located on the sidewall of the upper mask layer, and the retained initial spacer layer serves as the spacer layer.

[0061] refer to Figure 11 , remove the initial sacrificial layer 280 and the initial sidewall layer 270 above the upper mask layer 26, and the remaining initial sacrificial layer 280 (reference Figure 10 ) as the sacrificial layer 28, the remaining initial spacer layer 270 (reference Figure 10 ) as the spacer layer 27. At this time, the spacer layer 27 and the sacrificial layer 28 located on the upper surface of the initial lower mask layer 210 form a stacked structure.

[0062] In this embodiment, dry etching is used to remove a portion of the initial sacrificial layer 280 and a portion of the initial spacer layer 270 .

[0063] The sacrificial layer 28 includes an initial second pattern area 282, and the initial second pattern area 282 is adjacent to the initial first pattern area 261. In this embodiment, the initial second pattern area 282 is also located between the initial first pattern area 261 and the initial third pattern area 266. The orthographic projection of the second contact layer 222 on the upper surface of the substrate 200 falls within the orthographic projection of the initial second pattern area 282 on the upper surface of the substrate 200.

[0064] In this embodiment, the sacrificial layer 28 further includes other pattern areas in addition to the initial second pattern area 282 . In other embodiments, the sacrificial layer may only include the initial second pattern area.

[0065] refer to Figure 12-13 , Figure 13 For top view, Figure 12 for Figure 13 The local cross-sectional view in the A-A1 direction removes the upper mask layer 26 (refer to Figure 11 ) sidewall layer 27 (reference Figure 11 ); spacer layer 27 and sacrificial layer 28 located on the upper surface of initial lower mask layer 210 form a stacked structure; using upper mask layer 26 and the stacked structure as a mask, initial lower mask layer 210 is etched to form lower mask layer 21. After lower mask layer 21 is formed, upper mask layer 26 and the stacked structure are removed.

[0066] It can be understood that in other embodiments, since the initial sidewall layer located on the upper surface of the initial lower mask layer can be removed before the initial sacrificial layer is formed, only the initial sidewall layer located on the side wall of the upper mask layer is retained as the sidewall layer; accordingly, the entire sidewall layer is subsequently removed, and the initial lower mask layer is etched using the upper mask layer and the sacrificial layer as masks.

[0067] In this embodiment, the sidewall spacer 27 located on the sidewall of the upper mask layer 26 may be removed by wet etching. In other embodiments, dry etching may also be used to remove part of the sidewall spacer.

[0068] It is understood that after removing the sidewall layer 27 located on the sidewall of the upper mask layer 26, the initial lower mask layer 210 (refer to Figure 11 ), that is, the initial first pattern area 261 (reference Figure 11 ), the initial second pattern area 282 (reference Figure 11 ) and the pattern of the initial third pattern area 266 are transferred to the initial lower mask layer 210 (reference Figure 11 ).

[0069] Continue to refer Figure 13 The lower mask layer 21 includes at least a first pattern area 211 and a second pattern area 212, wherein the first pattern area 211 corresponds to the initial first pattern area 261 (refer to Figure 11 ), the second pattern area 212 corresponds to the initial second pattern area 282 (reference Figure 11 In this embodiment, due to the upper mask layer 26 (refer to Figure 11 ) also includes an initial third pattern area 266 (reference Figure 11 ), accordingly, after etching the initial lower mask layer 210, a third pattern area 213 is also formed.

[0070] The two first contact layers 221 are completely located directly below the first pattern area 211, and the second contact layer 222 is completely located directly below the second pattern area 212. It is understood that when the first contact layer 221 is completely located directly below the first pattern area 211 and the second contact layer 222 is completely located directly below the second pattern area 212, the contact area between the first contact layer 221 and the subsequently formed first electrical connection layer is maximized, and the contact area between the second contact layer 222 and the subsequently formed second electrical connection layer is maximized, thereby reducing contact resistance.

[0071] Continue to refer Figure 13 In this embodiment, because the first pattern area 211 is the combined area of ​​two subsequently formed first sub-pattern areas, the process window of the first pattern area 211 is larger than that of a single first sub-pattern area. This allows for more space to be reserved for the second pattern area 212. Specifically, the area of ​​the second pattern area 212 adjacent to the adjacent first pattern area 211 can be appropriately increased. In other words, the second pattern area 212 can be closer to the first pattern area 211 than the second contact layer 222; that is, the distance between the second pattern area 212 and the first pattern area 211 can be smaller than the distance between the second contact layer 222 and the first pattern area 211. This increases the volume of the subsequently formed second electrical connection layer, thereby reducing resistance, and also maintains a relatively large distance between the subsequently formed first electrical connection layer and the adjacent second contact layer 222, thereby reducing the risk of short circuits.

[0072] Furthermore, the spacing between adjacent first pattern areas 211 and second pattern areas 212 is 20 nm to 30 nm, for example, 22 nm, 25 nm, or 27 nm. When the spacing between the first pattern area 211 and the second pattern area 212 is within the above range, the spacing between the second contact layer 222 and the subsequently formed first electrical connection layer can be increased, thereby preventing short circuits.

[0073] It is worth noting that in this embodiment, the positions of the initial first pattern area 261 and the initial second pattern area 282 are sequentially defined by the upper mask layer 26 and the sacrificial layer 28. In other embodiments, the approximate positions of the first pattern area and the second pattern area can be defined at once, and a thin mask layer can be formed on the sidewalls of the first pattern area and the second pattern area, thereby more accurately adjusting the sizes of the first pattern area and the second pattern area.

[0074] Specifically, refer to Figure 14The step of forming the lower mask layer 21 includes: forming an initial lower mask layer on the initial electrical connection layer 240; etching the initial lower mask layer to form a plurality of mutually separate first lower mask layers 214; and forming a second lower mask layer 215 on the sidewalls of the first lower mask layer 214. The second lower mask layer 215 and the first lower mask layer 214 constitute the lower mask layer 21. In other embodiments, the second lower mask layer may also be located on the upper surface of the first lower mask layer and the upper surface of the stop layer.

[0075] It is worth noting that, since the second lower mask layer 215 is used to fine-tune the sizes of the first pattern area 211 and the second pattern area 212 , the thickness of the second lower mask layer 215 should not be too large.

[0076] In this embodiment, to ensure that the subsequent etching rate can remain relatively consistent and thus improve the accuracy of the pattern, the material of the second lower mask layer 215 is the same as that of the first lower mask layer 214. In other embodiments, the material of the second lower mask layer can also be different from that of the initial lower mask layer.

[0077] refer to Figures 15-18 , patterning the first pattern area 211, that is, truncating the first pattern area 211 to form two separate first sub-pattern areas 2111, wherein one first sub-pattern area 2111 is located between the second pattern area 212 and the other first sub-pattern area 2111; on the upper surface of the substrate 200, the orthographic projection of a first contact layer 221 falls within the orthographic projection of one first sub-pattern area 2111.

[0078] The shape of the first sub-pattern area 2111 is the same as the shape of the first electrical connection layer to be formed subsequently. That is, after the first pattern area 211 is cut off, two separate first electrical connection layers can be formed subsequently using the first sub-pattern area 2111 as a mask.

[0079] The steps of forming the first sub-pattern area 2111 will be described in detail below.

[0080] refer to Figure 15 , forming a middle mask layer 290 covering the lower mask layer. In this embodiment, the middle mask layer 290 has a two-layer structure, including a first middle mask layer 291 and a second middle mask layer 292. The material of the first middle mask layer 291 can be silicon carbide, silicon carbonitride, or silicon oxycarbide. The material of the second middle mask layer 292 can be silicon nitride or silicon oxynitride. In other embodiments, the middle mask layer can also have a single-layer structure.

[0081] refer to Figure 16The middle mask layer 290 is patterned to form an isolation trench 293 in the middle mask layer 290. In this embodiment, the isolation trench 293 is formed by photolithography and etching processes.

[0082] refer to Figure 17-18 , Figure 18 For top view, Figure 17 for Figure 18 The local cross section in the A-A1 direction is along the isolation trench 273 (reference Figure 16 ) cuts off the first pattern area 211 (reference Figure 16 ) to form a first sub-pattern area 2111.

[0083] In this embodiment, dry etching can be used to remove a portion of the first pattern area 211. The removed portion of the first pattern area 211 corresponds to a portion of the initial electrical connection layer 230, which will be removed later. Since this portion of the initial electrical connection layer 230 does not function, its removal does not affect the performance of the semiconductor structure.

[0084] Further, refer to Figure 18 Each first contact layer 221 is formed on the substrate 200 (refer to Figure 17 ) falls within a first sub-pattern area 2111. That is, a first contact layer 221 is completely located directly below a first sub-pattern area 2111.

[0085] The spacing between adjacent first sub-pattern areas 2111 is 30 nm to 50 nm, for example, 32 nm, 46 nm, or 57 nm. When the spacing between two first sub-pattern areas 2111 is within this range, it can ensure that the spacing between the two subsequently formed first electrical connection layers remains within a larger range, thereby preventing short circuits between the two layers. It can also avoid removing too much of the initial electrical connection layer, thereby ensuring that the first electrical connection layer has an appropriate volume to reduce resistance.

[0086] refer to Figure 19 , the shapes of the first sub-pattern area 2111 and the second sub-pattern area 212 are transferred to the initial electrical connection layer 230 (refer to Figure 17 Specifically, the following mask layer 21 (refer to Figure 17 ) is a mask, and the stop layer 250 is etched in sequence (refer to Figure 17 ), bottom mask layer 240 (reference Figure 17 ) and the initial electrical connection layer 230 to form a first electrical connection layer 231 and a second electrical connection layer 232 separated from each other. Each first electrical connection layer 231 corresponds to a first sub-pattern area 2111 (refer to Figure 18 ), each second electrical connection layer 232 corresponds to a second pattern area 212 (reference Figure 18); remove the lower mask layer 21, the stop layer 250 and the bottom mask layer 240. In this embodiment, a third electrical connection layer 233 is also formed.

[0087] Each first electrical connection layer 231 is electrically connected to a first contact layer 221, and each second electrical connection layer 232 is electrically connected to a second contact layer 222. Figure 19 It is a partial cross-sectional view. Figure 19 The other first contact layer 221 is not shown schematically. In other cross sections, the other first contact layer 221 is electrically connected to the first electrical connection layer 231 .

[0088] Furthermore, due to the large spacing between the second contact layer 222 and the adjacent first electrical connection layer 231, a short circuit is less likely to occur between the two. Furthermore, because the spatial position occupied by the second electrical connection layer 232 can be appropriately increased, the second electrical connection layer 232 can completely cover the top surface of the second contact layer 222, thereby avoiding the removal of part of the second contact layer 222 during the etching process, thereby preventing an increase in the contact resistance between the second contact layer 222 and the second electrical connection layer 232.

[0089] To sum up, in this embodiment, the patterns of the two first electrical connection layers 231 are first merged to form a first pattern area 211. Since the first pattern area 211 has a larger process window, some space can be reserved to facilitate the subsequent adjustment of the size and position of the first electrical connection layer 231, thereby avoiding a short circuit between the second contact layer 222 and the adjacent first electrical connection layer 231.

[0090] Another embodiment of the present invention provides a semiconductor structure. The semiconductor structure provided by this embodiment can be manufactured by the manufacturing method of the semiconductor structure provided by the previous embodiment. Figure 19 A partial cross-sectional view of the semiconductor structure provided in this embodiment, referring to Figure 19 The semiconductor structure includes: a substrate 200 having at least two first contact layers 221 and at least one second contact layer 222 separated from each other within the substrate 200; at least two first electrical connection layers 231 and at least one second electrical connection layer 232 separated from each other on the substrate 200; a first electrical connection layer 221 is located between a second electrical connection layer 232 and between another first electrical connection layer 231; on the top surface of the substrate 200, the orthographic projection of each first contact layer 221 falls within the orthographic projection of a first electrical connection layer 231, and the orthographic projection of each second contact layer 222 falls within the orthographic projection of a second electrical connection layer 232; and each first electrical connection layer 231 is electrically connected to a first contact layer 221, and each second electrical connection layer 232 is electrically connected to a second contact layer 222. For the same or similar portions of this embodiment to the previous embodiment, please refer to the detailed description of the previous embodiment, and no further description is given here.

[0091] The following is a detailed description with reference to the accompanying drawings.

[0092] In this embodiment, the base 200 is a double-layer structure, including a substrate 201 and a cover layer 202 .

[0093] The first contact layer 221 is completely located directly below the first electrical connection layer 231, and the second contact layer 222 is completely located directly below the second electrical connection layer 232. In this case, the contact area between the first contact layer 221 and the first electrical connection layer 231 is the entire upper surface area of ​​the first contact layer 221, which is the largest contact area between the two. The contact area between the second contact layer 222 and the second electrical connection layer 232 is the entire upper surface area of ​​the second contact layer 222, which is the largest contact area between the two. This reduces contact resistance.

[0094] In this embodiment, the semiconductor structure further includes a third electrical connection layer 233. In other embodiments, it may also include only the first electrical connection layer and the second electrical connection layer.

[0095] In this embodiment, the two first electrical connection layers 231 have the same width in the arrangement direction of the first electrical connection layers 231, i.e., in the horizontal direction. In other embodiments, the widths of the two first electrical connection layers 231 may be different. When the difference in width between the two first electrical connection layers 231 is kept within a small range, the resistance of the two first electrical connection layers 231 is close, and the difference in electrical performance between the two first electrical connection layers is also small.

[0096] The distance between two adjacent first electrical connection layers 231 is 30 nm to 50 nm, for example, 35 nm, 48 nm, or 56 nm. When the distance between adjacent first electrical connection layers 231 is kept within the above range, it can ensure that there is a sufficient distance between the two first electrical connection layers 231 to avoid short circuit between the two.

[0097] The distance between adjacent first electrical connection layers 231 and second electrical connection layers 232 is 20 nm to 30 nm, for example, 22 nm, 24 nm, or 29 nm. When the distance between adjacent first electrical connection layers 231 and second electrical connection layers 232 is maintained within the above range, sufficient distance between the first electrical connection layers 231 and the second electrical connection layers 232 can be ensured to prevent a short circuit between the two layers.

[0098] In this embodiment, the distance between adjacent first electrical connection layers 231 and second electrical connection layers 232 is less than the spacing between adjacent first electrical connection layers 231 and second contact layers 222. In other words, the spacing between adjacent first electrical connection layers 231 and second contact layers 222 is larger, further reducing the risk of a short circuit between the two. In other embodiments, the distance between adjacent first electrical connection layers and second electrical connection layers can also be equal to the spacing between adjacent first electrical connection layers and second contact layers. Specifically, in the arrangement direction of the first electrical connection layers 231, i.e., the horizontal direction, the spacing between adjacent first electrical connection layers 231 and second contact layers 222 is 20 nm to 55 nm, for example, 27 nm, 36 nm, or 45 nm. In summary, in this embodiment, the orthographic projection of each first contact layer 221 falls within the orthographic projection of a first electrical connection layer 231, and the orthographic projection of each second contact layer 222 falls within the orthographic projection of a second electrical connection layer 232. This results in low contact resistance. Furthermore, the distance between the second contact layer 222 and the first electrical connection layer 231 is larger, reducing the risk of a short circuit between the two.

[0099] Those skilled in the art will appreciate that the above-described embodiments are specific examples of the present invention, and that in actual applications, various changes in form and detail may be made thereto without departing from the spirit and scope of the present invention. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope defined in the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate having at least two first contact layers and at least one second contact layer separated from each other; forming an initial electrical connection layer, wherein the initial electrical connection layer is electrically connected to the first contact layer and the second contact layer; forming a lower mask layer on the initial electrical connection layer, wherein the lower mask layer includes at least one first pattern area and at least one second pattern area separated from each other, wherein the first pattern area is adjacent to the second pattern area; An orthographic projection of the second contact layer on the upper surface of the substrate falls within an orthographic projection of the second pattern area; Patterning the first pattern area of ​​the lower mask layer to form at least two mutually separated first sub-pattern areas, wherein one of the first sub-pattern areas is located between the second pattern area and another of the first sub-pattern areas; and on the upper surface of the substrate, an orthographic projection of the first contact layer falls within an orthographic projection of one of the first sub-pattern areas; Using the lower mask layer as a mask, the initial electrical connection layer is etched to form at least two first electrical connection layers and at least one second electrical connection layer that are separate from each other, each first electrical connection layer corresponds one-to-one to each first sub-pattern area and is electrically connected to the corresponding first contact layer, and each second electrical connection layer corresponds one-to-one to each second pattern area and is electrically connected to the corresponding second contact layer.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: The step of forming the lower mask layer includes: forming an initial lower mask layer on the initial electrical connection layer; forming a plurality of upper mask layers separated from each other on the initial lower mask layer, wherein the upper mask layers include an initial first pattern area; forming a sidewall spacer layer on the sidewall of the upper mask layer; forming a sacrificial layer between adjacent upper mask layers, wherein the sacrificial layer is in contact with the sidewall layer, and the sacrificial layer includes an initial second pattern area; removing the sidewall layer; The initial lower mask layer is etched using the upper mask layer and the sacrificial layer as masks to form the lower mask layer, wherein the first pattern area corresponds to the initial first pattern area, and the second pattern area corresponds to the initial second pattern area.

3. The method for manufacturing a semiconductor structure according to claim 2, wherein: The step of forming the spacer layer and the sacrificial layer includes: forming an initial spacer layer on the surface of the upper mask layer and the upper surface of the initial lower mask layer between the adjacent upper mask layers; forming an initial sacrificial layer covering the initial spacer layer; removing the initial sacrificial layer and the initial spacer layer above the upper mask layer, and the remaining initial sacrificial layer serves as the sacrificial layer, and the remaining initial spacer layer serves as the spacer layer; Removing the sidewall layer specifically includes: removing the sidewall layer located on the sidewall of the upper mask layer, retaining the sidewall layer located on the upper surface of the initial lower mask layer; the sidewall layer located on the upper surface of the initial lower mask layer and the sacrificial layer form a stacked structure; Using the upper mask layer and the sacrificial layer as masks to etch the initial lower mask layer specifically includes: using the upper mask layer and the stacked structure as masks to etch the initial lower mask layer.

4. The method for manufacturing a semiconductor structure according to claim 3, wherein: The method of forming the initial spacer layer includes an atomic layer deposition process.

5. The method for manufacturing a semiconductor structure according to claim 1, wherein: The steps of forming the lower mask layer include: forming an initial lower mask layer on the initial electrical connection layer; etching the initial lower mask layer to form a plurality of mutually separate first lower mask layers; forming a second lower mask layer on the side wall of the first lower mask layer, the second lower mask layer and the first lower mask layer constituting the lower mask layer.

6. The method for manufacturing a semiconductor structure according to claim 5, wherein: The material of the second lower mask layer is the same as that of the initial lower mask layer.

7. The method for manufacturing a semiconductor structure according to claim 1, wherein: Patterning the first pattern area specifically includes: forming a middle mask layer covering the lower mask layer; patterning the middle mask layer to form an isolation trench located in the middle mask layer; and cutting off the first pattern area along the isolation trench to form the first sub-pattern area.

8. The method for manufacturing a semiconductor structure according to claim 1, wherein: The distance between adjacent first sub-pattern areas is 30 nm to 50 nm.

9. The method for manufacturing a semiconductor structure according to claim 1, wherein: The distance between adjacent first pattern areas and second pattern areas is 20 nm to 30 nm.

10. The method for manufacturing a semiconductor structure according to claim 1, wherein: Before forming the lower mask layer, the method further includes: forming a bottom mask layer on the initial electrical connection layer, and the lower mask layer is also located on the bottom mask layer.

11. A semiconductor structure obtained by the manufacturing method according to any one of claims 1 to 10, characterized in that: include: a substrate having at least two first contact layers and at least one second contact layer separated from each other; The substrate has at least two first electrical connection layers and at least one second electrical connection layer separated from each other; A first electrical connection layer is located between a second electrical connection layer and between another first electrical connection layer; On the upper surface of the substrate, the orthographic projection of each first contact layer falls within the orthographic projection of a first electrical connection layer, and the orthographic projection of each second contact layer falls within the orthographic projection of a second electrical connection layer; and each first electrical connection layer is electrically connected to the corresponding first contact layer; and each second electrical connection layer is electrically connected to the corresponding second contact layer.

12. The semiconductor structure according to claim 11, wherein: The distance between two adjacent first electrical connection layers is 30 nm to 50 nm.

13. The semiconductor structure according to claim 11, wherein: The distance between adjacent first electrical connection layers and second electrical connection layers is 20 nm to 30 nm.

14. The semiconductor structure according to claim 11, wherein: In the arrangement direction of the first electrical connection layers, the distance between adjacent first electrical connection layers and the second contact layers is 20 nm to 55 nm.

15. The semiconductor structure according to claim 11, wherein: In the arrangement direction of the first electrical connection layers, the widths of the two first electrical connection layers are the same.

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