A method and apparatus for photoresist lift-off with improved efficiency

Abstract

The application discloses a photoresist etching back method and device for improving efficiency, which combines the first etching back step and the second etching back step in the original photoresist etching back process which need to be respectively performed in two etching cavities with different pollution levels in the same etching cavity, and a new process menu of a complete photoresist etching back process including the first etching back step and the second etching back step is established, so that the complete photoresist etching back process can be completed in the same etching cavity according to the new process menu, the step of measuring the remaining photoresist thickness between the first etching back step and the second etching back step can be omitted on the basis of ensuring the etching result stability of the original first etching back step, the wafer conveying time can be saved, the risk of the super waiting time which may occur between the first etching back step and the second etching back step can be avoided, the process flow is obviously shortened, and the overall efficiency of the photoresist etching back is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit technology, and in particular to a photoresist etching method and apparatus for improving efficiency. Background Technology

[0002] In metal gate fabrication, a post-metal gate process is typically employed. This involves first using a polysilicon dummy gate to form the gate dielectric layer, channel region, and source / drain regions of the device. Then, the polysilicon dummy gate is removed, and the site is filled with gate metal to form the metal gate. Before removing the polysilicon dummy gate, multiple layers, including silicon nitride and oxide hard mask layers, are usually formed on top of it. Therefore, all the layers above the polysilicon dummy gate must also be removed before its removal.

[0003] To avoid damaging other areas such as the active region outside the polysilicon dummy gate during the removal of the various film layers above the polysilicon dummy gate, a photolithography process is generally used to protect the active region and other areas. Then, a photoresist etch-back process is used to correct the structural height difference between the NFET and PFET in the central and peripheral regions (input and output regions) caused by the previous epitaxial germanium-silicon source and drain fabrication. This allows the polysilicon dummy gates with different heights in the central and peripheral regions to be opened, thereby improving the overall uniformity of the wafer surface.

[0004] The photoresist etch-back process is generally divided into two independent steps: a first etch and a second etch. The first etch involves etching the photoresist, specifically etching the entire photoresist downwards after photolithography to open the polysilicon dummy gates located in the central and peripheral regions. The main purpose of the second etch is to etch the layers above the polysilicon dummy gates. This typically requires completely removing the oxide hard mask layer above the polysilicon dummy gates, stopping at either the silicon nitride hard mask layer or the polysilicon dummy gates, depending on the product requirements. Afterwards, residual photoresist can be removed using a resist stripping process, and residual silicon nitride material can be removed during the silicon nitride trimming etching process using wet etching.

[0005] In existing processes, since the first and second etching cycles have different contamination levels, two etching machines with different contamination levels are required to complete the two independent steps of the photoresist etching process. Wafer transfer boxes with different contamination levels are also required to transfer the wafers after photoresist etching. That is, the wafers after the first etching cycle need to be transferred from one etching machine for the first etching cycle through a wafer transfer box with one contamination level, and then transferred to a wafer transfer box with another contamination level before they can be further transferred to another etching machine for the second etching cycle.

[0006] Meanwhile, in order to avoid insufficient or excessive photoresist etching during the first etching cycle, the thickness of the remaining photoresist on the wafer needs to be measured before the wafer is sent to the etching equipment for the second etching cycle.

[0007] The existing process described above requires two etching devices with different contamination levels to complete the first and second etching steps of the photoresist etch-back process, respectively. Furthermore, a measurement step for the remaining photoresist thickness is required between the first and second etching steps, and wafer transfer boxes with different contamination levels are also needed for wafer transfer. This results in a long overall process cycle and low efficiency. Summary of the Invention

[0008] The purpose of this invention is to overcome the above-mentioned defects in the prior art and provide a photoresist back etching method and apparatus with improved efficiency.

[0009] To achieve the above objectives, the technical solution of the present invention is as follows:

[0010] This invention provides an efficient photoresist etching back method, comprising:

[0011] A process menu with complete control over the photoresist etch-back process is established using an etching cavity, wherein the etching cavity has a second contamination level;

[0012] The substrate with completed photoresist etch-back lithography is fed into the etching chamber with a second contamination level by a photoresist lithography device with a first contamination level, and the complete photoresist etch-back process is continuously completed. A dummy gate structure and a photoresist covering at least part of the dummy gate structure are formed on the substrate with completed photoresist etch-back lithography. The complete photoresist etch-back process includes a first etch-back step for etching the photoresist and a second etch-back step for etching the oxide hard mask layer in the dummy gate structure. The first contamination level is lower than the second contamination level.

[0013] Furthermore, during the first etching step, O2 gas and H2 gas are introduced into the etching cavity to partially etch the photoresist covering the substrate, thereby exposing the top surface of the dummy gate structure.

[0014] Furthermore, by reducing the ratio between the O2 gas and the H2 gas, the etching rate of the photoresist is reduced to counteract the accelerating effect of the etching cavity of the second contamination level on the etching rate of the photoresist.

[0015] Furthermore, during the second etching step, the oxide hard mask layer in the pseudo gate structure is removed by stopping the introduction of O2 and H2 gases into the etching chamber, introducing CF4 and CHF3 gases into the etching chamber, and bombarding with argon gas.

[0016] Furthermore, before performing the photolithography, the method further includes: first covering the substrate, including the dummy gate structure, with an etch stop layer, and then covering the photoresist on the etch stop layer before performing the photolithography.

[0017] Furthermore, after completing the second etching step, a reverse verification is performed by measuring the remaining thickness of the etching stop layer to check whether the remaining thickness of the photoresist after completing the first etching step meets the standard.

[0018] The present invention also provides an efficient photoresist back etching apparatus, comprising:

[0019] An etching chamber with a second level of contamination;

[0020] The control module has a process menu for performing a complete photoresist etch-back process;

[0021] In this process, after the substrate that has been photolithographically lithographically completed before photoresist etch-back is sent into the etching cavity of the second contamination level by a photolithography device of the first contamination level, the control module controls the etching cavity to continuously complete the complete photoresist etch-back process according to the process menu.

[0022] Wherein, a dummy gate structure and a photoresist covering at least a portion of the dummy gate structure are formed on the substrate before photoresist etch-back; the complete photoresist etch-back process includes a first etch-back step for etching the photoresist and a second etch-back step for etching the oxide hard mask layer in the dummy gate structure, wherein the first contamination level is lower than the second contamination level.

[0023] Furthermore, it also includes:

[0024] The process gas input pipeline includes a first pipeline, a second pipeline, a third pipeline, and a fourth pipeline connected to the etching chamber. A first control valve is provided on the first pipeline, a second control valve is provided on the second pipeline, a third control valve is provided on the third pipeline, and a fourth control valve is provided on the fourth pipeline. The first control valve to the fourth control valve are connected to the control module.

[0025] Furthermore, by executing the process menu, the control module controls the closure of the third and fourth control valves and the opening of the first and second control valves during the first etch-back step. This allows O2 gas and H2 gas with a first flow ratio to be introduced into the etching chamber through the first and second pipelines, respectively, to partially etch the photoresist covering the substrate, exposing the top surface of the dummy gate structure. During the second etch-back step, the control module controls the closure of the first and second control valves and the opening of the third and fourth control valves. This allows CF4 gas and CHF3 gas with a second flow ratio to be introduced into the etching chamber through the third and fourth pipelines, respectively, and controls argon bombardment to remove the oxide hard mask layer in the dummy gate structure.

[0026] As can be seen from the above technical solution, the present invention integrates the photoresist etch-back process, combining the first and second etch-back steps, which were originally performed separately in two etching cavities with different contamination levels, into a single etching cavity for continuous completion. A new process menu is established that includes both the first and second etch-back steps, enabling the complete photoresist etch-back process to be completed in the same etching cavity according to the new process menu. This ensures the stability of the etching results in the original first etch-back step, eliminates the step of measuring the remaining photoresist thickness between the first and second etch-back steps, saves wafer transfer time, and avoids the risk of excessive waiting time that might occur between the first and second etch-back steps. This significantly shortens the process flow and thus improves the overall efficiency of photoresist etch-back. Attached Figure Description

[0027] Figure 1 This is a flowchart of a preferred embodiment of the photoresist etching method for improving efficiency.

[0028] Figures 2-7 According to a preferred embodiment of the present invention Figure 1 A schematic diagram of the relevant process steps for photoresist back etching using the method;

[0029] Figure 8 This is a schematic diagram of the structural principle of a photoresist back etching device for improving efficiency, according to a preferred embodiment of the present invention. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, but does not exclude other elements or objects.

[0031] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0032] Please see Figure 1 , Figure 1 This is a flowchart illustrating a preferred embodiment of the photoresist etching method for improving efficiency. Figure 1 As shown, the present invention provides an efficient photoresist etching method, comprising:

[0033] Using an etching chamber, a process menu with complete control over the photoresist etch-back process is established, and the etching chamber has a second level of contamination;

[0034] The substrate that has undergone photolithography before photoresist etch-back is sent from a first-level contamination photolithography device into a second-level contamination etching chamber to continuously complete the entire photoresist etch-back process.

[0035] In this process, a pseudo-gate structure and a photoresist covering at least part of the pseudo-gate structure are formed on the substrate before photoresist etch-back. The complete photoresist etch-back process includes a first etch-back step for etching the photoresist and a second etch-back step for etching the oxide hard mask layer in the pseudo-gate structure. The first contamination level is lower than the second contamination level.

[0036] The following example illustrates a method for fabricating a metal gate structure, combined with... Figures 2-7 The implementation process of the above-mentioned photoresist back etching method for improving efficiency will be described in detail below.

[0037] Please see Figure 2 First, a dummy gate structure 11, used in the fabrication of a metal gate, can be formed on a semiconductor substrate 10, such as a silicon substrate 10. Specifically, this may include:

[0038] An isolation structure 20 is formed on the silicon substrate 10 to isolate the active regions, including the active regions in the central region and the active regions in the peripheral region. The isolation structure 20 may be, for example, a shallow trench isolation structure 20.

[0039] A pseudo-gate structure 11 is fabricated on the active region of the central region to form an n-type field-effect transistor (nFET) and a p-type field-effect transistor (pFET) in the central region, and a pseudo-gate structure 11 is fabricated on the active region of the peripheral region to form an n-type field-effect transistor (nFET) and a p-type field-effect transistor (pFET) in the peripheral region.

[0040] Each field-effect transistor's dummy gate structure 11 includes a polysilicon dummy gate layer 16, a silicon nitride hard mask layer 15, and an oxide hard mask layer 14. Sidewalls are formed on the outer side of the dummy gate structure 11, and the sidewalls may include a first sidewall 19 located on the inner side and a second sidewall 18 located on the outer side of the first sidewall 19. The sidewall material may be, for example, silicon nitride.

[0041] Active and drain regions are formed on the active regions on both sides of the dummy gate structure 11 of each field-effect transistor. Among them, an epitaxial germanium-silicon layer 13 is formed in the source or drain region of the p-type field-effect transistor (pFET) in the central region, thus causing a height difference between the dummy gate structures 11 of each field-effect transistor during the etching process of forming germanium-silicon source and drain.

[0042] Furthermore, the size of the pseudo-gate structure 11 of the two field-effect transistors in the central region is significantly different from that of the two field-effect transistors in the peripheral region. That is, the size of the pseudo-gate structure 11 of the two field-effect transistors in the peripheral region is significantly larger than that of the pseudo-gate structure 11 of the two field-effect transistors in the central region.

[0043] In order to protect the active region other than the pseudo gate structure 11 during photoresist etch-back, a silicon nitride etch stop layer 17 can be coated on the surface of the formed device structure.

[0044] Then, photoresist 12 can be coated on the surface of the formed device structure, and photolithography before photoresist back etching can be performed.

[0045] Please see Figure 3 After completing the photolithography before photoresist back etching, a photoresist opening window 21 is formed above the pseudo-gate structure 11 of the two field-effect transistors in the peripheral region, exposing the surface of the silicon nitride etch stop layer 17 on the top surface of the pseudo-gate structure 11.

[0046] The silicon substrate 10, after photolithography before photoresist etch-back, is transferred out of the photolithography equipment of the first contamination level through a wafer transfer cassette. Then, the thickness of the photoresist 12 on the silicon substrate 10 after photoresist etch-back is measured.

[0047] Subsequently, the silicon substrate 10 after photolithography before photoresist etch-back is transferred to a wafer transfer box of the second contamination level through a wafer transfer box of the first contamination level. Then, the silicon substrate 10 after photolithography before photoresist etch-back is sent into an etching cavity 201 of the present invention of the second contamination level through the wafer transfer box of the second contamination level, and the complete photoresist etch-back process is carried out in the etching cavity 201.

[0048] The second contamination level can be, for example, a higher contamination level containing metal ion contamination, while the first contamination level can be a lower contamination level without metal ion contamination. Existing photoresist etch-back processes include a first etch-back step for etching the photoresist 12 and a second etch-back step for etching the oxide hard mask layer 14 in the dummy gate structure 11. The first etch-back step has a first contamination level and needs to be performed independently in an etching chamber with the first contamination level; the second etch-back step has a second contamination level and needs to be performed independently in another etching chamber with the second contamination level. This invention integrates the existing photoresist etch-back process, combining the first and second etch-back steps, which previously required separate etching chambers with different contamination levels, into a single etching chamber 201 for continuous completion, thus establishing a new process menu for a complete photoresist etch-back process that includes both the first and second etch-back steps.

[0049] Please see Figure 4 In a preferred embodiment, when the first etching step is performed in the same etching cavity 201 of the present invention, O2 gas and H2 gas are introduced into the etching cavity 201 to partially etch the photoresist 12 covered on the substrate 10 after photolithography, so that the top surface of the pseudo gate structure 11 of each field-effect transistor is opened and the surface of the silicon nitride etching stop layer 17 on the top surface of the pseudo gate structure 11 is exposed.

[0050] The remaining photoresist 12 can be used to protect the surface of the active region other than the pseudo-gate structure 11.

[0051] In a preferred embodiment, since there is metal ion contamination in the second contamination level etching cavity 201, it will accelerate the original etching rate when etching the photoresist 12. Therefore, in this step, the etching rate of the photoresist 12 can be reduced by decreasing the ratio between O2 gas and H2 gas, so as to counteract the accelerating effect of the second contamination level etching cavity 201 on the etching rate of the photoresist 12.

[0052] In a preferred embodiment, the ratio of O2 gas to H2 gas can satisfy:

[0053] O2:H2 < 1:10

[0054] Please see Figure 5 After completing the first etching step, the process menu will directly proceed to the second etching step. At this time, the introduction of O2 and H2 gases into the etching chamber 201 is stopped, and CF4 and CHF3 gases are introduced into the etching chamber 201. At the same time, argon bombardment is performed to open the silicon nitride etch stop layer 17 on the top surface of each pseudo-gate structure 11, and the removal etching of the oxide hard mask layer 14 in the pseudo-gate structure 11 below the silicon nitride etch stop layer 17 is completed.

[0055] In a preferred embodiment, the ratio of CF4 gas to CHF3 gas can satisfy:

[0056] CF4:CHF3 = 1:1

[0057] This invention integrates the previously separate, low-contamination first etch-back step and high-contamination second etch-back step in existing photoresist etch-back processes. By adding the second etch-back step to the existing etching chamber used only for the first etch-back step, a new etching process menu with a complete photoresist etch-back process is formed. This enables a new process system that can continuously complete two etching steps with different contamination levels within the same etching chamber, expanding the new process route of incorporating the high-contamination process into the low-contamination process. Furthermore, during the first etch-back step, by reducing the ratio of O2 to H2 gas to decrease the etching rate of the photoresist 12, the accelerated etching rate of the new etching chamber 201 with its second contamination level is successfully offset. Simultaneously, by supplementing the second etch-back step with argon bombardment, the opening effect of the silicon nitride etch stop layer 17 is improved, and the removal rate of the oxide hard mask layer 14 is accelerated. This overcomes the limitations of traditional process routes that can only perform processes of the same contamination level in one etching chamber.

[0058] Therefore, by adjusting and optimizing the existing first and second etch process menus, the present invention forms a new process menu that includes the first and second etch steps, thus ensuring the stability of the measurement data and pseudo-gate structure morphology after the second etch step.

[0059] After completing the second etch step, i.e., the entire photoresist etch-back process, the original height difference between the two dummy gate structures 11 of the two field-effect transistors in the central region and the two dummy gate structures 11 in the peripheral region is effectively reduced. Furthermore, the silicon nitride etch stop layer 17 covering the active region surface outside the remaining photoresist 12 and the dummy gate structures 11 below it provides good protection for the active region surface outside the dummy gate structures 11.

[0060] In the second etching step, the oxide hard mask layer 14 above the polysilicon dummy gate can be completely removed, and depending on different product requirements, the etching can stop on the silicon nitride hard mask layer 15 or the polysilicon dummy gate layer 16. The figure shows an example when the etching stops on the polysilicon dummy gate layer 16.

[0061] Please see Figure 6 After the complete photoresist etch-back process is completed in the same etching chamber 201, the silicon substrate 10 with the above-mentioned devices can be transferred to another process chamber for resist removal. The resist removal process removes the residual photoresist 12 after the photoresist etch-back process.

[0062] In a preferred embodiment, an ashing process and a wet cleaning process can be used to remove the residual photoresist 12 after the photoresist re-etching process.

[0063] After removing the residual photoresist 12, the remaining silicon nitride etch stop layer 17 covering the area outside the polysilicon pseudo gate layer 16 is fully exposed.

[0064] Next, the standard procedure of measuring the remaining thickness of the silicon nitride etch stop layer 17 can be used to reverse verify whether the remaining thickness of the photoresist 12 after the first etch step meets the standard. That is, if the measured remaining thickness of the silicon nitride etch stop layer 17 is within the set range of the remaining thickness of the etch stop layer, it indicates that the remaining thickness of the photoresist 12 after the first etch step also meets the requirements of the photoresist remaining thickness standard.

[0065] Furthermore, when measuring the remaining thickness of the silicon nitride etch stop layer 17, the measurement may also include measuring the height (horn height) of the protrusion 22 above the top surface of the polysilicon dummy gate at the top of the sidewall. If the measured remaining thickness of the silicon nitride etch stop layer 17 is within the set range for the remaining thickness of the etch stop layer, and the measured height of the protrusion 22 above the top surface of the polysilicon dummy gate at the top of the sidewall is also within the set range for the horn height, it indicates that the remaining thickness of the photoresist 12 after the first etch step also meets the requirements of the photoresist remaining thickness standard. This further ensures the effectiveness of the reverse verification.

[0066] Please see Figure 7After the residual photoresist 12 is removed, the silicon substrate 10 after the residual photoresist 12 is removed can be transferred to the next process chamber to continue the silicon nitride trimming etching process after the photoresist back etching process.

[0067] In a preferred embodiment, a wet etching process can be used to remove the silicon nitride etch stop layer 17, as well as the residual silicon nitride hard mask layer 15 and silicon nitride second sidewall 18 on the dummy gate structure 11, while retaining the silicon nitride first sidewall 19.

[0068] This step also eliminates the horn height generated in the previous step, resulting in a pseudo-gate structure 11 with a good morphology.

[0069] Subsequently, conventional processes can be used to remove the polysilicon pseudo-gate layer 16 in the pseudo-gate structure 11, and gate metal can be filled into the cavity generated after removing the polysilicon pseudo-gate layer 16 to form a metal gate.

[0070] In the process of fabricating the metal gate described above, it can be seen that by adopting the method of the present invention, a process cavity originally used for the second etch-back step of the photoresist etch-back process can be saved, a step of transferring the wafer substrate 10 between wafer transfer boxes of different contamination levels can be reduced, and the remaining photoresist thickness measurement step originally performed between the first and second etch-back steps of the photoresist etch-back process can be eliminated, thereby significantly saving process time and improving efficiency.

[0071] The following detailed description of an efficiency-enhancing photoresist etching apparatus of the present invention, with reference to specific embodiments and accompanying drawings, will be provided in detail.

[0072] Please see Figure 8 The present invention provides an efficiency-enhancing photoresist etching-back apparatus 200, which can be used to implement the efficiency-enhancing photoresist etching-back method of the present invention described above, for application in the fabrication of a metal gate. The apparatus 200 may include several main structural components such as an etching chamber 201, a process gas input pipeline, and a control module 210.

[0073] There is one etching cavity 201. The etching cavity 201 has a second contamination level. The etching cavity 201 is used to perform a complete photoresist etch-back process on the substrate 10, which has formed a dummy gate structure 11 and has completed photoresist etch-back before photoresist etch-back, and is fed in by a photolithography device of a first contamination level lower than the second contamination level.

[0074] The process gas input pipeline is used to supply various process gases required for the photoresist etch-back process to the etching chamber 201. The process gas input pipeline may include a first pipeline 202, a second pipeline 204, a third pipeline 207, and a fourth pipeline 209 connecting the etching chamber 201. Specifically, a first control valve 203 may be installed on the first pipeline 202, a second control valve 205 may be installed on the second pipeline 204, a third control valve 206 may be installed on the third pipeline 207, and a fourth control valve 208 may be installed on the fourth pipeline 209.

[0075] The first control valve to the fourth control valves 203, 205, 206, and 208 are connected to the control module 210.

[0076] The control module 210 establishes a process menu for performing a complete photoresist etch-back process, and controls the etching cavity 201 to continuously complete the complete photoresist etch-back process on the substrate 10 according to the process menu.

[0077] In one optional embodiment, the first conduit 202 can be used to supply O2 gas to the etching chamber 201; the second conduit 204 can be used to supply H2 gas to the etching chamber 201; the third conduit 207 can be used to supply CF4 gas to the etching chamber 201; and the fourth conduit 209 can be used to supply CHF3 gas to the etching chamber 201. However, these conduits can also be interchanged.

[0078] The photoresist etch-back process mode established on the process menu may include a first etch-back step for etching the photoresist 12 and a second etch-back step for etching the oxide hard mask layer 14 in the pseudo gate structure 11.

[0079] In a preferred embodiment, the control module 210, by executing the process menu, controls the closure of the third control valve 206 on the third pipeline 207 and the fourth control valve 208 on the fourth pipeline 209 during the first etch step, and opens the first control valve 203 on the first pipeline 202 and the second control valve 205 on the second pipeline 204, so that O2 gas and H2 gas with a first flow ratio are respectively introduced into the etching chamber 201 through the first pipeline 202 and the second pipeline 204 to partially etch the photoresist 12 covering the substrate 10, exposing the top surface of the dummy gate structure 11.

[0080] The control module 210 also controls the closing of the first control valve 203 and the second control valve 205, and the opening of the third control valve 206 and the fourth control valve 208 during the second etching step by executing the process menu. This allows CF4 gas and CHF3 gas with a second flow ratio to be introduced into the etching chamber 201 through the third pipeline 207 and the fourth pipeline 209, respectively. It also controls argon bombardment to remove the oxide hard mask layer 14 in the pseudo gate structure 11.

[0081] In a preferred embodiment, the first flow ratio can satisfy:

[0082] O2:H2 < 1:10

[0083] In a preferred embodiment, the second flow ratio can satisfy:

[0084] CF4:CHF3 = 1:1

[0085] In an optional embodiment, the etching chamber 201 may be an etching chamber 201 capable of generating plasma etching gas.

[0086] In an optional embodiment, the control module 210 may be located on or outside the photoresist etch-back device 200, and may be connected to the production execution system.

[0087] In an optional embodiment, the control module 210 can be connected to the host computer 211 to realize remote control of photoresist re-etching.

[0088] In an optional embodiment, a control module 210 operation menu can also be provided on the graphical user interface of the photoresist etch-back apparatus 200, so that the set values ​​on the photoresist etch-back process menu can be modified on-site according to the data measurement structure. Therefore, two-level control of the photoresist etch-back process, both on-site and remote, can be realized.

[0089] In summary, this invention integrates the photoresist etch-back process, combining the first and second etch-back steps, which previously required separate etching chambers with different contamination levels, into a single etching chamber 201 for continuous execution. It also establishes a new process menu encompassing both the first and second etch-back steps, enabling the complete photoresist etch-back process to be completed within the same etching chamber 201. This ensures the stability of the etching results from the first etch-back step while eliminating the need for an etching chamber and the step of measuring the remaining photoresist thickness between the first and second etch-back steps. Furthermore, it saves wafer transfer time and avoids the risk of excessive waiting time between the first and second etch-back steps, significantly shortening the process flow and thus improving the overall efficiency of photoresist etch-back.

[0090] While embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations fall within the scope and spirit of the invention as set forth in the claims. Furthermore, the invention described herein may have other embodiments and can be implemented or carried out in various ways.

Claims

1. A photoresist etching method for improving efficiency, characterized in that, include: A process menu with complete control over the photoresist etch-back process is established using an etching cavity, wherein the etching cavity has a second contamination level; The substrate, after photolithography before photoresist etch-back, is fed into the etching chamber of the second contamination level using a photolithography device of the first contamination level. The complete photoresist etch-back process is then continuously completed. A dummy gate structure and photoresist covering at least a portion of the dummy gate structure are formed on the substrate after photolithography before etch-back. The complete photoresist etch-back process includes a first etch-back step for etching the photoresist and a second etch-back step for etching the oxide hard mask layer in the dummy gate structure. The first contamination level is lower than the second contamination level. When performing the first etching step, O2 gas and H2 gas are introduced into the etching cavity to partially etch the photoresist covering the substrate, exposing the top surface of the dummy gate structure. By reducing the ratio between the O2 gas and the H2 gas, the etching rate of the photoresist is reduced to counteract the accelerating effect of the second contamination level etching cavity on the etching rate of the photoresist. During the second etching step, the oxide hard mask layer in the pseudo gate structure is removed by stopping the introduction of O2 and H2 gases into the etching chamber, introducing CF4 and CHF3 gases into the etching chamber, and bombarding with argon gas.

2. The photoresist etching method for improving efficiency according to claim 1, characterized in that, Conducting Before the photolithography, the process also includes: first covering the substrate, including the dummy gate structure, with an etch stop layer, then covering the photoresist on the etch stop layer, and then performing the photolithography.

3. The photoresist etching method for improving efficiency according to claim 2, characterized in that, After completion After the second etching step, the remaining thickness of the etching stop layer is measured to verify whether the remaining thickness of the photoresist after the first etching step meets the standard.

4. A photoresist back-etching device for improving efficiency, characterized in that, include: An etching chamber with a second level of contamination; The control module has a process menu for performing a complete photoresist etch-back process; In this process, after the substrate that has been photolithographically etched before photoresist etch-back is sent into the etching cavity of the second contamination level by a photolithography device of the first contamination level, the control module controls the etching cavity to continuously complete the complete photoresist etch-back process according to the process menu. The substrate on which photoresist lithography is performed before etch-back is formed has a dummy gate structure and a photoresist covering at least a portion of the dummy gate structure; the complete photoresist etch-back process includes a first etch-back step for etching the photoresist and a second etch-back step for etching the oxide hard mask layer in the dummy gate structure, wherein the first contamination level is lower than the second contamination level; it also includes: The process gas input pipeline includes a first pipeline, a second pipeline, a third pipeline, and a fourth pipeline connected to the etching chamber. A first control valve is provided on the first pipeline, a second control valve is provided on the second pipeline, a third control valve is provided on the third pipeline, and a fourth control valve is provided on the fourth pipeline. The first control valve to the fourth control valve are connected to the control module. The control module, by executing the process menu, controls the closure of the third and fourth control valves and the opening of the first and second control valves during the first etch-back step. This allows O2 and H2 gases with a first flow ratio to be introduced into the etching chamber through the first and second pipelines, respectively, to partially etch the photoresist covering the substrate, exposing the top surface of the dummy gate structure. During the second etch-back step, the control module controls the closure of the first and second control valves and the opening of the third and fourth control valves. This allows CF4 and CHF3 gases with a second flow ratio to be introduced into the etching chamber through the third and fourth pipelines, respectively, and controls argon bombardment to remove the oxide hard mask layer in the dummy gate structure.

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