Vertical power device structure, manufacturing method and electronic equipment

Abstract

A structure, a manufacturing method and an electronic device of a vertical power device belong to the field of semiconductor technology. The invention comprises an upper arm structure and a lower arm structure; both the upper arm structure and the lower arm structure comprise a substrate, a buffer layer, an epitaxial layer, a channel layer, an active layer, an isolation column and a first metal column; the substrate, the buffer layer, the epitaxial layer, the channel layer and the active layer are arranged in sequence from bottom to top; the gate structure passes through the active layer and the channel layer vertically downward from the upper surface of the active layer; the side surface of the isolation column overlaps with the cut surface and passes through from the upper surface of the active layer to the lower surface of the epitaxial layer; the first metal column passes through from the lower surface of the substrate to the epitaxial layer; the cut surface is the interface between the upper arm structure and the lower arm structure; the depth of the first metal column in the lower arm structure is greater than the depth of the first metal column in the upper arm structure; therefore, while meeting the high withstand voltage of the upper arm device, the on-resistance of the lower arm device is reduced.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular relates to a structure, a manufacturing method and an electronic device of a vertical power device. Background Art

[0002] like Figure 1 As shown, an inverter that converts DC to AC usually consists of two upper and lower switching devices (upper arm switching device V1 and lower arm switching device V2). The node where the switching devices are connected in series is the output end, and the output end is connected to the load (inductor L and resistor R).

[0003] The related vertical power device uses two switching devices with exactly the same structure. However, according to Figure 1 The working principle of the inverter is shown in the figure. When the upper arm switch device V1 is turned on, the current flows as follows: Figure 2 As shown, the current flow of the lower arm switch device V2 is as follows Figure 3 As shown, it can be seen that the loads and voltage levels connected to the drain and source ends of the upper-arm switching device V1 and the lower-arm switching device V2 are different. Specifically, the upper-arm switching device V1 is connected to a high DC potential and the load, while the lower-arm switching device V2 is connected to a low DC potential. Considering the continuous switching action, the upper-arm switching device V1 and the lower-arm switching device V2 require different circuit characteristics. That is, the upper-arm switching device V1 is subjected to positive voltage for a longer period of time, while the lower-arm switching device V2 is subjected to negative voltage for a longer period of time. Therefore, the upper-arm switching device V1 and the lower-arm switching device V2 require different voltage withstand capabilities and on-resistances.

[0004] Therefore, the related vertical power devices have the defect of being unable to improve the voltage resistance while reducing the on-resistance due to their identical structures. Summary of the Invention

[0005] The purpose of this application is to provide a structure, a manufacturing method and an electronic device of a vertical power device, aiming to solve the problem that related vertical power devices cannot reduce on-resistance while improving voltage resistance.

[0006] An embodiment of the present application provides a structure of a vertical power device, including an upper arm structure and a lower arm structure; wherein the upper arm structure and the lower arm structure both include:

[0007] The substrate, buffer layer, epitaxial layer, channel layer and active layer are arranged in sequence from bottom to top;

[0008] a gate structure extending vertically downward from the upper surface of the active layer through the active layer and the channel layer;

[0009] an isolation column having a side surface overlapping the cut surface and extending from the upper surface of the active layer to the lower surface of the epitaxial layer;

[0010] a first metal pillar extending from the lower surface of the substrate to the first epitaxial layer;

[0011] The section is an interface between the upper arm structure and the lower arm structure; and the depth of the first metal column in the lower arm structure is greater than the depth of the first metal column in the upper arm structure.

[0012] In one embodiment, the gate structure includes:

[0013] a first trench extending longitudinally downward from the upper surface of the active layer through the active layer and the channel layer;

[0014] a first dielectric layer covering the inner surface of the sidewalls of the first trench and the upper surface of the bottom of the first trench;

[0015] A conductive pillar is filled in the first dielectric layer.

[0016] In one embodiment, the upper arm structure and the lower arm structure both use the conductive column as the gate, and the upper arm structure and the lower arm structure both use the active layer as the source; the upper arm structure and the lower arm structure both use the first metal column as the drain electrode.

[0017] In one embodiment, the buffer layer, epitaxial layer, channel layer and active layer are all gallium nitride, the first dielectric layer is silicon nitride or silicon dioxide; the conductive column is polysilicon; and the first metal column is gold or palladium.

[0018] In one embodiment, the epitaxial layer is a low-doped N-type epitaxial layer, the channel layer is a P-type channel layer, and the active layer is an N-type active layer; or

[0019] The epitaxial layer is a low-doped P-type epitaxial layer, the channel layer is an N-type channel layer, and the active layer is a P-type active layer.

[0020] The present invention also provides a method for manufacturing a vertical power device, the method comprising:

[0021] forming a buffer layer on the upper surface of the substrate;

[0022] forming an epitaxial layer, a channel layer and an active layer in sequence from bottom to top on the upper surface of the buffer layer;

[0023] removing a portion of the active layer and a portion of the channel layer to form a gate structure;

[0024] Removing a portion of the epitaxial layer, a portion of the channel layer, and a portion of the active layer at a position corresponding to a cut surface to form a first columnar trench; wherein the cut surface is the interface between the upper arm structure and the lower arm structure in the vertical power device;

[0025] filling the first columnar trench with an insulating material to form an isolation column;

[0026] Removing portions of the substrate, the buffer layer, and the epitaxial layer at predetermined distances on both sides of the first columnar trench to form a second columnar trench and a third columnar trench; wherein the depth of the second columnar trench is greater than the depth of the third columnar trench;

[0027] A metal material is filled in the second pillar trench and the third pillar trench to form a first metal pillar.

[0028] In one embodiment, filling the second columnar trench and the third columnar trench with metal material to form the first metal column specifically comprises:

[0029] The second columnar trench is filled with metal material to form a first metal column of a lower arm structure. Meanwhile, the third columnar trench is filled with metal material to form a first metal column of an upper arm structure.

[0030] In one embodiment, removing a portion of the active layer and a portion of the channel layer to form a gate structure includes:

[0031] removing a portion of the active layer and a portion of the channel layer to form a second trench;

[0032] forming a second dielectric layer on an upper surface of the active layer and an upper surface of the second trench;

[0033] removing the second dielectric layer on the upper surface of the active layer and retaining the second dielectric layer on the upper surface of the second trench to form a first dielectric layer;

[0034] The interior of the first dielectric layer is filled to form a conductive pillar.

[0035] In one embodiment, forming an epitaxial layer, a channel layer, and an active layer on the upper surface of the buffer layer in sequence from bottom to top includes:

[0036] forming the epitaxial layer on the upper surface of the buffer layer;

[0037] ion implantation on the upper surface of the epitaxial layer to form the channel layer;

[0038] Ions are implanted into the upper surface of the channel layer to form the active layer.

[0039] An embodiment of the present application further provides an electronic device, which includes the structure of the vertical power device described above.

[0040] Compared with the prior art, the embodiments of the present invention have the following advantages: since the side surface of the isolation column overlaps with the sagittal plane and penetrates from the upper surface of the active layer to the lower surface of the epitaxial layer, the isolation column separates the vertical power device into an upper arm device (corresponding to the upper arm structure) and a lower arm device (corresponding to the lower arm structure) that do not interfere with each other; since the epitaxial layer, the channel layer and the active layer are arranged in sequence from bottom to top, and the gate structure penetrates the active layer and the channel layer longitudinally downward from the upper surface of the active layer; therefore, the active layer can serve as the source of the upper arm device and the lower arm device, and the epitaxial layer can serve as the drain of the upper arm device and the lower arm device; and since the first metal column penetrates from the lower surface of the substrate to the epitaxial layer, and the depth of the first metal column in the lower arm structure is greater than the depth of the first metal column in the upper arm structure, the upper arm device and the lower arm device can select metal columns of different depths as drain electrodes, so that the upper arm device can withstand positive voltage for a longer time, and the lower arm switching device can withstand negative voltage for a longer time, thereby improving the voltage resistance while reducing the on-resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical inventions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0042] Figure 1 An example circuit structure diagram of an inverter in the related art;

[0043] Figure 2 for Figure 1 A current flow diagram of an inverter of the related art is shown;

[0044] Figure 3 for Figure 1 Another current flow diagram of an inverter of the related art is shown;

[0045] Figure 4 A schematic structural diagram of a vertical power device provided in one embodiment of the present application;

[0046] Figure 5 Another structural schematic diagram of a vertical power device provided in one embodiment of the present application;

[0047] Figure 6 A schematic diagram of forming a buffer layer in the method for manufacturing a vertical power device provided in an embodiment of the present application;

[0048] Figure 7A schematic diagram of forming an epitaxial layer, a channel layer, and an active layer in the method for manufacturing a vertical power device provided in an embodiment of the present application;

[0049] Figure 8 A schematic diagram of forming a gate structure in a method for manufacturing a vertical power device provided in an embodiment of the present application;

[0050] Figure 9 A schematic diagram of forming a first columnar trench in the method for manufacturing a vertical power device provided in an embodiment of the present application;

[0051] Figure 10 A schematic diagram of forming an isolation column in the method for manufacturing a vertical power device provided in an embodiment of the present application;

[0052] Figure 11 A schematic diagram of forming second to third columnar trenches in the method for manufacturing a vertical power device provided in an embodiment of the present application;

[0053] Figure 12 A schematic diagram of forming a first metal column in the method for manufacturing a vertical power device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0054] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0055] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0056] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0057] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0058] Figure 4 The module structure of the vertical power device provided by the embodiment of the present invention is shown. For ease of description, only the parts related to the embodiment of the present invention are shown, which are detailed as follows:

[0059] The structure of the vertical power device includes an upper arm structure and a lower arm structure; wherein, the upper arm structure and the lower arm structure both include a substrate 80, a buffer layer 90, an epitaxial layer 12, a channel layer 13, an active layer 14, a gate structure 15, an isolation column 16 and a first metal column 17.

[0060] The substrate 80, the buffer layer 90, the epitaxial layer 12, the channel layer 13 and the active layer 14 are arranged in sequence from bottom to top; the gate structure 15 passes through the active layer 14 and the channel layer 13 vertically downward from the upper surface of the active layer 14; the side of the isolation column 16 overlaps with the cut surface 100 and passes through from the upper surface of the active layer 14 to the lower surface of the epitaxial layer 12; the first metal column 17 passes through from the lower surface of the substrate 80 to the epitaxial layer 12; wherein the cut surface 100 is the boundary surface between the upper arm structure and the lower arm structure; the depth of the first metal column 17 in the lower arm structure is greater than the depth of the first metal column 17 in the upper arm structure.

[0061] The substrate 80 may be a silicon substrate 80. By providing the buffer layer 90, the lattice adaptation degree of the epitaxial layer 12 formed on the silicon substrate 80 is improved, thereby improving the performance of the vertical power device and the product manufacturing yield.

[0062] like Figure 5 As shown, the gate structure 15 includes a first trench 151 , a first dielectric layer 152 and a conductive pillar 153 .

[0063] The first trench 151 passes through the active layer 14 and the channel layer 13 vertically downward from the upper surface of the active layer 14 ; the first dielectric layer 152 covers the inner surface of the sidewall of the first trench 151 and the bottom upper surface of the first trench 151 ; the conductive pillar 153 fills the inside of the first dielectric layer 152 .

[0064] The gate structure 15 has simple process and reliable performance.

[0065] It should be emphasized that both the upper arm structure and the lower arm structure use the conductive pillar 153 as the gate, and both the upper arm structure and the lower arm structure use the active layer 14 as the source; and both the upper arm structure and the lower arm structure use the first metal pillar 17 as the drain electrode.

[0066] The depth of the first metal pillar 17 in the lower arm structure is greater than the depth of the first metal pillar 17 in the upper arm structure, and both the upper arm structure and the lower arm structure use the first metal pillar 17 as the drain electrode. Therefore, the upper arm device meets the high withstand voltage requirement to prevent device breakdown, and the lower arm device meets the low on-resistance requirement to reduce power consumption, so that the upper arm device can withstand positive voltage for a longer time, and the lower arm device can withstand negative voltage for a longer time.

[0067] It should be noted that the buffer layer 90 , epitaxial layer 12 , channel layer 13 and active layer 14 are all made of gallium nitride, the first dielectric layer 152 is made of silicon nitride or silicon dioxide; the conductive pillar 153 is made of polysilicon; and the first metal pillar 17 is made of gold or palladium.

[0068] As an example but not a limitation, the epitaxial layer 12 is a low-doped N-type epitaxial layer 12 , the channel layer 13 is a P-type channel layer 13 , and the active layer 14 is an N-type active layer 14 ; thereby forming an N-type switching device.

[0069] As an example but not a limitation, the epitaxial layer 12 is a low-doped P-type epitaxial layer 12 , the channel layer 13 is an N-type channel layer 13 , and the active layer 14 is a P-type active layer 14 ; thereby forming a P-type switching device.

[0070] Corresponding to an embodiment of a vertical power device, the present invention also provides an embodiment of a method for manufacturing a vertical power device.

[0071] A method for manufacturing a vertical power device includes steps 400 to 406.

[0072] In step 400, if Figure 6 As shown, a buffer layer 90 is formed on the upper surface of the substrate 80 .

[0073] The buffer layer 9090 may be formed on the upper surface of the substrate 80 by vapor deposition, sputtering or other processes.

[0074] In step 401, if Figure 7 As shown, an epitaxial layer 12 , a channel layer 13 and an active layer 14 are sequentially formed on the upper surface of the buffer layer 90 from bottom to top.

[0075] In a specific implementation, step 401 includes steps A1 to C1.

[0076] In step A1, an epitaxial layer 12 is formed on the upper surface of the buffer layer 90. The epitaxial layer 12 can be formed on the upper surface of the buffer layer 90 by vapor deposition or sputtering.

[0077] In step B1 , ions are implanted into the upper surface of the epitaxial layer 12 to form a channel layer 13 .

[0078] In step C1 , ions are implanted on the upper surface of the channel layer 13 to form the active layer 14 .

[0079] In step 402, if Figure 8 As shown, a portion of the active layer 14 and a portion of the channel layer 13 are removed and a gate structure 15 is formed.

[0080] In a specific implementation, step 402 includes steps A2 to D2.

[0081] In step A2 , a portion of the active layer 14 and a portion of the channel layer 13 are removed to form a second trench.

[0082] A portion of the active layer 14 and a portion of the channel layer 13 may be removed by an etching process to form a second trench.

[0083] In step B2, a second dielectric layer is formed on the upper surface of the active layer 14 and the upper surface of the second trench;

[0084] A second dielectric layer may be formed on the upper surface of the active layer 14 and the upper surface of the second trench by vapor deposition, sputtering or other processes.

[0085] In step C2, the second dielectric layer on the upper surface of the active layer 14 is removed and the second dielectric layer on the upper surface of the second trench is retained to form a first dielectric layer 152;

[0086] The second dielectric layer on the upper surface of the active layer 14 is etched back and the second dielectric layer on the upper surface of the second trench is retained to form a first dielectric layer 152 ; wherein the material of the first dielectric layer 152 and the second dielectric layer can both be silicon dioxide or silicon nitride.

[0087] In step D2, the interior of the first dielectric layer 152 is filled to form a conductive pillar 153. The conductive pillar 153 may be made of polysilicon.

[0088] In step 403, if Figure 9 As shown, part of the epitaxial layer 12 , part of the channel layer 13 and part of the active layer 14 are removed at a position corresponding to the cut surface 100 to form a first columnar trench 71 ; wherein the cut surface 100 is the interface between the upper arm structure and the lower arm structure in the vertical power device.

[0089] A portion of the epitaxial layer 12 , a portion of the channel layer 13 , and a portion of the active layer 14 may be removed at a position corresponding to the cut surface 100 by an etching process to form a first pillar trench 71 .

[0090] The first columnar trench 71 penetrates from the upper surface of the active layer 1414 to the lower surface of the epitaxial layer 12 .

[0091] In step 404, if Figure 10As shown, an insulating material is filled in the first pillar trench 71 to form an isolation column 16 .

[0092] The first columnar trench 71 may be filled with an insulating material by a process such as vapor deposition or sputtering to form the isolation column 16 .

[0093] In step 405, if Figure 11 As shown, part of the substrate 80, part of the buffer layer 90 and part of the epitaxial layer 12 are removed at preset distances on the left and right sides of the first columnar trench 71 to form a second columnar trench 72 and a third columnar trench 73; wherein the depth of the second columnar trench 72 is greater than the depth of the third columnar trench 73.

[0094] A development process may be used to remove portions of the substrate 80 , the buffer layer 90 , and the epitaxial layer 12 at predetermined distances on both sides of the first columnar trench 71 to form the second columnar trench 72 and the third columnar trench 73 .

[0095] The second pillar trench 72 and the third pillar trench 73 penetrate from the upper surface of the active layer 14 to the epitaxial layer 12 .

[0096] In step 406, if Figure 12 As shown, metal material is filled in the second pillar trench 72 and the third pillar trench 73 to form the first metal pillar 17 .

[0097] The second columnar trench 72 is filled with metal material to form the first metal pillar 17 of the lower arm structure. At the same time, the third columnar trench 73 is filled with metal material to form the first metal pillar 17 of the upper arm structure. Therefore, the depth of the first metal pillar 17 in the lower arm structure is greater than the depth of the first metal pillar 17 in the upper arm structure.

[0098] The first metal pillar 17 may be gold or palladium.

[0099] The embodiment of the present invention includes an upper arm structure and a lower arm structure; the upper arm structure and the lower arm structure both include a substrate, a buffer layer, an epitaxial layer, a channel layer, an active layer, an isolation column and a first metal column; the substrate, buffer layer, epitaxial layer, channel layer and active layer are arranged in sequence from bottom to top; the gate structure passes through the active layer and the channel layer vertically downward from the upper surface of the active layer; the side surface of the isolation column overlaps with the cut surface and passes through from the upper surface of the active layer to the lower surface of the epitaxial layer; the first metal column passes through from the lower surface of the substrate to the epitaxial layer; the cut surface is the interface between the upper arm structure and the lower arm structure; the depth of the first metal column in the lower arm structure is greater than the depth of the first metal column in the upper arm structure; therefore, the upper arm structure and the lower arm structure can both use the first metal column as a drain electrode, so that the effective depth of the epitaxial layer serving as the drain in the upper arm structure is greater than the effective depth of the epitaxial layer serving as the drain in the lower arm structure, while meeting the high withstand voltage of the upper arm device and reducing the on-resistance of the lower arm device.

[0100] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0101] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A vertical power device structure, characterized in that: The invention comprises an upper arm structure and a lower arm structure; wherein the upper arm structure and the lower arm structure both comprise: The substrate, buffer layer, epitaxial layer, channel layer and active layer are arranged in sequence from bottom to top; a gate structure extending vertically downward from the upper surface of the active layer through the active layer and the channel layer; an isolation column having a side surface overlapping the cut surface and extending from the upper surface of the active layer to the lower surface of the epitaxial layer; a first metal pillar extending from the lower surface of the substrate to the epitaxial layer; The section is an interface between the upper arm structure and the lower arm structure; the depth of the first metal column in the lower arm structure is greater than the depth of the first metal column in the upper arm structure; The upper arm structure and the lower arm structure both use the active layer as a source electrode; and the upper arm structure and the lower arm structure both use the first metal column as a drain electrode.

2. The structure of the vertical power device according to claim 1, wherein: The gate structure includes: a first trench extending longitudinally downward from the upper surface of the active layer through the active layer and the channel layer; a first dielectric layer covering the inner surface of the sidewalls of the first trench and the upper surface of the bottom of the first trench; A conductive pillar is filled in the first dielectric layer.

3. The structure of the vertical power device according to claim 2, wherein: The upper arm structure and the lower arm structure both use the conductive pillar as a gate.

4. The structure of the vertical power device according to claim 2, wherein: The buffer layer, epitaxial layer, channel layer and active layer are all made of gallium nitride, the first dielectric layer is made of silicon nitride or silicon dioxide; the conductive column is made of polysilicon; and the first metal column is made of gold or palladium.

5. The structure of the vertical power device according to claim 1, wherein: The epitaxial layer is a low-doped N-type epitaxial layer, the channel layer is a P-type channel layer, and the active layer is an N-type active layer; or The epitaxial layer is a low-doped P-type epitaxial layer, the channel layer is an N-type channel layer, and the active layer is a P-type active layer.

6. A method for manufacturing a vertical power device, characterized in that: The manufacturing method comprises: forming a buffer layer on the upper surface of the substrate; forming an epitaxial layer, a channel layer and an active layer in sequence from bottom to top on the upper surface of the buffer layer; removing a portion of the active layer and a portion of the channel layer to form a gate structure; Removing a portion of the epitaxial layer, a portion of the channel layer, and a portion of the active layer at a position corresponding to a cut surface to form a first columnar trench; wherein the cut surface is the interface between the upper arm structure and the lower arm structure in the vertical power device; filling the first columnar trench with an insulating material to form an isolation column; Removing portions of the substrate, the buffer layer, and the epitaxial layer at predetermined distances on both sides of the first columnar trench to form a second columnar trench and a third columnar trench; wherein the depth of the second columnar trench is greater than the depth of the third columnar trench; Filling the second columnar trench with metal material to form a first metal column of the lower arm structure, and at the same time, filling the third columnar trench with metal material to form a first metal column of the upper arm structure; The upper arm structure and the lower arm structure both use the active layer as a source electrode; the first metal column of the upper arm structure serves as a drain electrode of the upper arm structure; and the first metal column of the lower arm structure serves as a drain electrode of the lower arm structure.

7. The method for manufacturing a vertical power device according to claim 6, wherein: The removing of part of the active layer and part of the channel layer to form a gate structure includes: removing a portion of the active layer and a portion of the channel layer to form a second trench; forming a second dielectric layer on an upper surface of the active layer and an upper surface of the second trench; removing the second dielectric layer on the upper surface of the active layer and retaining the second dielectric layer on the upper surface of the second trench to form a first dielectric layer; The interior of the first dielectric layer is filled to form a conductive pillar.

8. The method for manufacturing a vertical power device according to claim 6, wherein: The step of sequentially forming an epitaxial layer, a channel layer, and an active layer on the upper surface of the buffer layer from bottom to top includes: forming the epitaxial layer on the upper surface of the buffer layer; ion implantation on the upper surface of the epitaxial layer to form the channel layer; Ions are implanted into the upper surface of the channel layer to form the active layer.

9. An electronic device, characterized in that: The electronic device comprises the structure of the vertical power device according to any one of claims 1 to 5.

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