Fir digital filtering device, filtering method, medium and computer program product

Abstract

This invention provides an FIR digital filtering device, a filtering method, a computer-readable storage medium, and an FIR digital filtering device containing a computer program, comprising an input module, a block filtering module, and an output module. The input module is used to input a signal vector x of length N, a state vector s of length M, and a coefficient vector c of length M, where N > M. The block filtering module is used to perform shift-block processing to obtain N sample values ​​of an information vector y. The output module is used to output a signal vector y of length N. This solution significantly improves computational efficiency, reduces computational load, greatly improves resource utilization, and reduces energy consumption.

Description

Technical Field

[0001] This invention relates to the field of digital filtering technology, and in particular to an FIR digital filtering device, filtering method, computer-readable storage medium, and product containing computer program based on a DSP processor. Background Technology

[0002] Finite-length impulse response (FIR) filters are widely used in digital signal processing and are the most basic unit in digital signal processing systems. They are simple in structure, easy to implement, have stable performance due to the absence of feedback, and offer advantages such as high accuracy and linear phase. In practical applications, to achieve good filtering effects and high accuracy, FIR filters typically require high orders. Therefore, the calculation of FIR filters consumes significant computational resources and increases chip power consumption. Hardware implementation of FIR filters can be achieved through several methods: integrated circuits, DSP chips, and programmable logic devices. One solution uses a monolithic general-purpose digital filter integrated circuit. This circuit is simple to use, but due to the limited word length and order specifications, it is difficult to fully meet practical needs. Although multiple chips can be used to expand the requirements, this increases size and power consumption, thus limiting its practical application. Another solution uses programmable logic devices, such as FPGAs / CPLDs. FPGAs have regular internal logic block arrays and abundant interconnect resources, making them particularly suitable for implementing fine-grained and highly parallel FIR filters. Compared to general-purpose DSP chips that rely on serial operations, they offer better parallelism and scalability. Another solution involves using DSP chips. DSP chips have dedicated digital signal processing functions that can be called, or the code can be designed to implement the FIR function according to the chip's instruction set structure. Because the coefficient calculation and quantization in FIR design are relatively complex, MATLAB software is generally used as an auxiliary design tool to calculate the FIR coefficients before implementing the code. Implementing an FIR filter is relatively simple, but the speed is limited due to the sequential execution of the program. Moreover, even DSP chips from different companies may have different programming instructions, resulting in a longer development cycle.

[0003] As the most basic unit in digital signal processing systems, FIR filters are widely used in fields such as communication, image processing, audio processing, and pattern recognition. The most basic function of an FIR filter is to implement the transfer function of a system or module, convolving it with the input signal in the time domain to obtain the output of the system or module. Generally, the higher the order of the FIR filter, the better its response to the system or module and the higher its accuracy. However, higher-order FIR filters consume more computational resources during FIR calculations, and if a high-order FIR filter is called multiple times in an algorithm, it will affect the overall computational load, reducing the algorithm's efficiency and performance. When the algorithm is implemented in a terminal device, it is ported to the corresponding algorithm processor chip. Taking a mobile terminal as an example, the high computational load of one module's algorithm will affect the operation of other modules and increase the phone's power consumption. Therefore, while ensuring the performance of the FIR filter and the algorithm, it is necessary to optimize the FIR filter calculation to reduce its consumption of computational resources.

[0004] Terminal devices typically use digital signal processors (DSPs) to process various audio / video algorithms. Most DSP processors are equipped with data processing units such as arithmetic logic units (ALUs) and multipliers and accumulators (MACs). Existing filtering methods have high hardware overhead and consume a lot of energy. Summary of the Invention

[0005] Based on the above situation, this invention aims to design a solution that can reduce computational load and improve computational speed. The purpose of this invention is to provide a method for block-based computation of FIR filter outputs based on a DSP processor. While keeping the number of multiply-accumulate operations constant, by reducing the loop overhead in the algorithm, it can significantly improve computational efficiency, reduce computational load, greatly improve resource utilization, and reduce energy consumption compared to existing solutions.

[0006] In a first aspect, embodiments of the present invention provide an FIR digital filtering device, comprising an input module, a block filtering module, and an output module; the input module is used to input a signal vector x of length N, x = [x0, x1, ..., xn]. N-1 And a state vector s of length M, s = [s0, s1, ..., s2] M-1 And an input coefficient vector c of length M, c = [c0, c1, ..., c2] M-1 ], where N>M;

[0007] The block filtering module is used to perform shift block processing to obtain N sample values ​​of the information vector y; the output module is used to output a signal vector y of length N, y = [y0, y1, ..., y2]. N-1 ].

[0008] The calculation of the FIR filter based on the DSP processor-based FIR digital filtering device provided in this embodiment of the invention consumes a lot of computing resources and increases the power consumption of the chip. This invention proposes a method for quickly calculating the FIR filter on a DSP processor. Compared with existing calculation methods, this method can significantly improve the calculation efficiency, save chip computing resources, and reduce processor power consumption.

[0009] In a further embodiment, the FIR digital filtering device includes a first processing module, a second processing module, and a third processing module for block filtering;

[0010] The first processing module performs data processing by performing a matrix concatenation of the signal vector x and the state vector s to generate an extended vector z, z = s|x = [s0, s1, ..., s2]. M-1 ,x0,x1,···,x N-1 ];

[0011] The second processing module is used to perform M / 2 inner loop processing and N / 3 outer loop processing to obtain M*N cumulative terms of the information vector y;

[0012] The third processing module is used to classify and accumulate the corresponding M*N accumulation terms based on the sample points of the vector y; to obtain the N sample point values ​​of the information vector y.

[0013] In a further embodiment, the FIR digital filtering device, the second processing module includes an inner loop module and an outer loop module.

[0014] The inner loop module is used to obtain the three sample values ​​of vector Y in sequence every M / 2 inner loop processes.

[0015] The outer loop module is used to perform N / 3 outer loops in conjunction with the inner loop to obtain M*N cumulative terms of the vector y.

[0016] In some embodiments, the FIR digital filtering device has a main window of 2 for the coefficient vector c, which covers the first two c samples. The extended (buffered) vector z has a subordinate window of 4, which covers the first four z samples. Each time the inner loop processing module loads, it loads the two c samples covered by the main window and the four z samples covered by the subordinate window. In one loading cycle, the inner loop processing module performs a corresponding shift matching product on the two c samples of the coefficient vector c and the four z samples of the extended vector z. In one loading cycle, the main window moves twice with the two covered c samples, moving one c sample position each time, while the subordinate window remains unchanged.

[0017] In some other embodiments, in a new loading cycle, the main window of the FIR digital filter moves by 2 c-sample points to sequentially cover the 2 c-sample points in the sorted sequence, the subordinate window moves by 2 z-sample points to sequentially cover the 4 z-sample points in the sorted sequence, and the inner loop processing module loads the newly covered 2 c-sample points and the newly covered 4 z-sample points.

[0018] Secondly, this invention also provides a digital filtering processing method applied to an FIR digital filtering device based on a DSP processor, comprising the following steps:

[0019] S100: Input signal vector x of length N, x = [x0, x1, ..., x2] N-1 Let the input signal of the M-1 order FIR filter be x;

[0020] Step S200: Input a state vector s of length M, s = [s0, s1, ..., s200]. M-1 ];

[0021] Step S300: Concatenate the signal vector x and the state vector s using a matrix to generate an extended vector z, z = s|x = [s0, s1, ..., s2]. M-1 ,x0,x1,···,x N-1 ], put it into the cache.

[0022] Step S400: Input a coefficient vector c of length M, c = [c0, c1, ..., c2] M-1 ];

[0023] Step S500: The block filtering module performs a shift and block processing operation on the input vector, especially the coefficient vector z in the buffer corresponding to the coefficient vector c, to obtain N sample values ​​of the information vector y.

[0024]

[0025] Similarly, we can obtain:

[0026]

[0027]

[0028] until……

[0029]

[0030] Step S700: Output a signal vector y of length N, y = [y0, y1, ..., y2] N-1 ], where N>M.

[0031] In a further embodiment, the digital filtering processing method, step S500 further includes:

[0032] Step S510: In each inner loop, obtain the 3 sample values ​​of vector y in sequence, and obtain the 3 sample values ​​of vector y in M / 2 inner loops;

[0033] Step S520: Perform M / 2 inner loop processing and N / 3 outer loop processing to obtain M*N cumulative terms of the information vector y.

[0034] In a further embodiment, the digital filtering processing method, step S510 further includes: 8

[0035] Step S511: Each loading in the inner loop process loads 2 c-samples covered by the main window and 4 z-samples covered by the subordinate window;

[0036] Step S512: During one loading cycle, the inner loop processing module performs a corresponding shift matching product of the two c samples of the coefficient vector c and the four z samples of the extended vector z. During one loading cycle, the main window moves twice with the two covered c samples, moving one c sample position each time, while the subordinate window remains unchanged.

[0037] Step S513: In a new loading cycle, the main window moves 2 c-sample points to sequentially cover the 2 c-sample points in the sorted order, the subordinate window moves 2 z-sample points to sequentially cover the 4 z-sample points in the sorted order, and the inner loop processing module loads the newly covered 2 c-sample points and the newly covered 4 z-sample points.

[0038] In some embodiments, the digital filtering processing method further includes the following steps after step S520:

[0039] Step S600: Based on the sample points of vector y, classify the corresponding M*N accumulated terms; obtain N sample point values ​​of information vector y.

[0040] Thirdly, embodiments of the present invention also provide a computer-readable storage medium storing a computer program, characterized in that the computer program, when executed by a processor, implements the filtering method described in any of the second aspects above.

[0041] Fourthly, this embodiment of the invention also provides a computer program product that, when run on a DSP processor-based FIR digital filter device, enables the FIR digital filter device to implement any of the possible filtering methods described in the second aspect above.

[0042] For the beneficial effects of the second to fourth aspects mentioned above, please refer to the description in the first aspect mentioned above. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 A schematic diagram of the FIR digital filtering device module based on a DSP processor provided by the present invention;

[0045] Figure 2 This is a schematic flowchart of a digital filtering processing method provided in an embodiment of the present invention;

[0046] Figure 3 This is a schematic diagram of a filtering process provided in an embodiment of the present invention;

[0047] Figure 4 This is a schematic diagram of the first loading of the main window in the shifted block according to an embodiment of the present invention;

[0048] Figure 5 This is a schematic diagram of the second loading of the main window and subordinate window in the shifting block according to an embodiment of the present invention;

[0049] Figure 6 A schematic diagram illustrating the generation of sample points for vector y according to an embodiment of the present invention;

[0050] Figure 7 This is a schematic diagram of a block filtering process provided in an embodiment of the present invention;

[0051] Figure 8This is a schematic diagram of a terminal device structure provided in an embodiment of the present invention;

[0052] Figure 9 This is a schematic diagram of a test host structure provided in an embodiment of the present invention. Detailed Implementation

[0053] The technical solutions of the embodiments of the present invention will be described below with reference to the accompanying drawings. In the description of the embodiments of the present invention, the terminology used in the following embodiments is for the purpose of describing specific embodiments only and is not intended to be a limitation of this application. As used in the specification and appended claims of this application, the singular expressions “a,” “the,” “the,” “the,” and “this” are intended to also include expressions such as “one or more,” unless the context clearly indicates otherwise. It should also be understood that in the following embodiments of this application, “at least one” and “one or more” refer to one or more (including two). The term “and / or” is used to describe the relationship between related objects, indicating that three relationships can exist; for example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character “ / ” generally indicates that the preceding and following related objects are in an “or” relationship.

[0054] References to "one embodiment" or "some embodiments" in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized. The term "connection" includes direct connections and indirect connections, unless otherwise stated. "First" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0055] In embodiments of the present invention, the terms "exemplarily" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplarily" or "for example" in embodiments of the present invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the terms "exemplarily" or "for example" is intended to present the relevant concepts in a specific manner.

[0056] An FIR digital filtering device provided in this embodiment of the invention, such as... Figure 1 As shown, the FIR digital filtering device 700 includes an input module 701, a block filtering module 702, and an output module 703; the input module 701 is used to input a signal vector x of length N, x = [x0, x1, ..., x2]. N-1 And a state vector s of length M, s = [s0, s1, ..., s2] M-1 And an input coefficient vector c of length M, c = [c0, c1, ..., c2] M-1 ], where N>M;

[0057] The block filtering module 702 is used to perform shift block processing to obtain N sample values ​​of the information vector y; the output module 703 is used to output a signal vector y of length N, y = [y0, y1, ..., y2]. N-1 ].

[0058] In this device, further as... Figure 3 The diagram shows the filtering process in an existing FIR digital filter device.

[0059] Where 101 is the input buffer [z] k ,z k+1 ,···,z M+k-1 ], that is, the vector in the extended vector z consisting of the k-th point to the (M+k-1)-th point; 102 is the coefficient vector c; 103 is... This represents the product of corresponding elements of the input extended vector z and the coefficient vector c, i.e., the Hadamard product of these two vectors; 104 represents the summation of the M products from the previous step, thus obtaining the output y. k Specifically, the calculation method for each sample point in the output y is as follows:

[0060]

[0061] Similarly, we can obtain:

[0062]

[0063]

[0064] until……

[0065]

[0066] It can be seen that if y = [y0, y1, ..., y] is calculated completely... N-1Given N points in the input extended vector z, an outer loop is needed N times. Within each outer loop, an inner loop is needed M times for accumulation calculation. That is, each inner loop M calculates the product of a point in the input extended vector z and the corresponding point in the coefficient vector c, and then accumulates the results. Therefore, the entire operation requires M×N loops. It can be analyzed that if y=[y0,y1,···,y N-1 Given N points in the input buffer vector z, the outer loop needs to be run N times. Within each outer loop, the inner loop needs to run M times for accumulation calculation. That is, each inner loop M calculates the product of a point in the input buffer vector z and the corresponding point in the coefficient vector c, and accumulates the results. Therefore, the entire calculation process requires M×N loops.

[0067] It is worth mentioning that the innovative scheme disclosed in this invention performs block-based processing for the calculation of the FIR filter, with a data block size of I×J. That is, the inner loop M loads J points each time to calculate I output samples. Taking a 3×2 block as an example... Figure 4 and Figure 5 As shown, in the inner loop, each iteration loads two points from the coefficient vector c and four points from the input buffer z. Specifically, the first load in the first iteration of the inner loop is shown below. Figure 4 As shown, c0 and c1, along with the input buffers s1, s2, s3, and s4, can simultaneously calculate the first two multiplicative terms of the three output values ​​y0, y1, and y2. The first load outputs six cumulative terms, as shown in expressions (1), (2), and (3); the second load in the first inner loop, as shown... Figure 5 As shown, the third and fourth product terms of the three output values ​​y0, y1, and y2 can be calculated simultaneously. The second load also outputs 6 product terms. Then, the inner loop continues until all product terms of y0, y1, and y2 are calculated, as shown. Figure 6 As shown, each M / 2 inner loop can calculate 3 output points (elements) of vector Y, thus reducing the total number of loops to M×N / 6. One embodiment applies this algorithm to the CEVADSP processor. Compared to some other processors, the CEVADSP processor's MAC unit can directly read data from the input cache and coefficient vector address, eliminating the need for pre-loading data. Furthermore, in fixed-point arithmetic, the ALU unit can work with the MAC unit to perform shift operations in parallel during multiplication and accumulation, further improving the algorithm's execution efficiency.

[0068] In a specific embodiment, the input signal x is a vector with a length of 240 points and the coefficient vector c has 48 points. The calculation result based on the CEVADSP processor is as follows: it takes 25,700 cycles to complete the FIR filtering calculation using the conventional method; while it only takes 12,800 cycles using the method proposed in this paper. The method reduces the processor's computational load by about 50%.

[0069] In one possible implementation, the FIR digital filtering device further includes a first processing module, a second processing module, and a third processing module for the block filtering; as shown below. Figure 7 As shown, in step 501, input vectors x and s are used. The first processing module performs data processing to transform the signal vector x, x = [x0, x1, ..., x2] into a signal vector s. N-1 The state vector s, s = [s0, s1, ..., s2] is given. M-1 Perform a matrix concatenation to generate an extended vector z, z = s|x = [s0, s1, ..., s M-1 ,x0,x1,···,x N-1 ], where N>M;

[0070] Step 502: Input vector z into the buffer; and step 503: Input coefficient vector c into the buffer.

[0071] Step 504: The second processing module performs M / 2 inner loop processing and N / 3 outer loop processing on vectors z and c to obtain M*N cumulative terms of information vector y.

[0072] The third processing module is used to classify and accumulate the corresponding M*N accumulation terms based on the sample points of the vector y; to obtain the N sample point values ​​of the information vector y.

[0073] In some further possible embodiments, the FIR digital filtering device, the second processing module includes an inner loop module and an outer loop module.

[0074] The inner loop module is used to obtain the three sample values ​​of vector Y in sequence every M / 2 inner loop processes.

[0075] In the above embodiment, the FIR digital filtering device sets the number of main windows for the coefficient vector c to 2, meaning the main window covers 2 c samples. During the initial load, the main window covers the first 2 c samples. The number of subordinate windows for the extended vector z is 4, meaning the subordinate windows cover 4 z samples. During the initial load, the subordinate windows cover the first 4 z samples. Each load of the inner loop processing module loads the 2 c samples covered by the main window and the 4 z samples covered by the subordinate windows. In one loading period, such as... Figure 4 As shown, in this loading cycle, two new covered c-samples (c0 and c1) and four new covered z-samples (s1, s2, s3, and s4) are loaded. The inner loop processing module performs a corresponding shift-matching product between the two c-samples of the coefficient vector c and the four z-samples of the extended vector z. In one loading cycle, the main window moves twice with the two covered c-samples (i.e., ...). Figure 4 The positions of the main window corresponding to rows y1 and y2 are shown in the table. Each time, the order of sample points is shifted by 1 c. During the first loading period, the subordinate window remains unchanged, that is, the subordinate window of the extended vector z covers 4 sample points. The result of the shift matching product is the output of three cumulative terms y0, y1, and y2. The output values ​​are as shown in the first two cumulative terms in expressions (1), (2), and (3), for a total of 6 cumulative terms.

[0076] In some other embodiments, the FIR digital filter device, in a new loading cycle, such as Figure 5 As shown, the main window moves 2 c-sample points, sequentially covering the 2 c-sample points in the sorted sequence. The subordinate window moves 2 z-sample points, sequentially covering the 4 z-sample points in the sorted sequence. At this time, c2 of vector c corresponds to s3 of vector z. In this loading cycle, the inner loop processing module loads the newly covered 2 c-sample points (c2 and c3) and the newly covered 4 z-sample points (s3, s4, s5, and s6). In one loading cycle, the main window moves twice with the covered 2 c-sample points (i.e., ...). Figure 5 The positions of the main window corresponding to rows y1 and y2 in the table are respectively moved by 1 c sample point each time. During the new loading period, the subordinate window remains unchanged. The inner loop processing module performs corresponding shift matching product on the 2 c sample points of the coefficient vector c and the 4 z sample points of the extension vector z. The result of the shift matching product is the output of the three accumulated terms y0, y1, and y2. The output values ​​are the 3rd and 4th accumulated terms shown in expressions (1)(2)(3), for a total of 6 accumulated terms.

[0077] In some other embodiments, the inner loop module is used to sequentially obtain the three sample values ​​y0, y1, y2 of vector Y, including all 3*N accumulated terms of the three sample values, every M / 2 inner loop processes.

[0078] The outer loop module is used to perform N / 3 outer loops in conjunction with the inner loop, that is, until M*N accumulated terms of the vector y are obtained, and the shift-matching product correspondence is as follows. Figure 6 As shown, Figure 7 The 505th step outputs the vector y.

[0079] A digital filtering method, applied to a DSP processor-based FIR digital filtering device, includes the following steps:

[0080] S100: Input signal vector x of length N, x = [x0, x1, ..., x2] N-1 Let the input signal of the M-1 order FIR filter be x;

[0081] Step S200: Input a state vector s of length M, s = [s0, s1, ..., s200]. M-1 ];

[0082] Step S300: Concatenate the signal vector x and the state vector s using a matrix to generate an extended vector z, z = s|x = [s0, s1, ..., s2]. M-1 ,x0,x1,···,x N-1 ], put it into the cache.

[0083] Step S400: Input a coefficient vector c of length M, c = [c0, c1, ..., c2] M-1 ];

[0084] Step S500: The block filtering module performs a shift and block processing operation on the input vector, especially the coefficient vector z in the buffer corresponding to the coefficient vector c, to obtain N sample values ​​of the information vector y.

[0085]

[0086] Similarly, we can obtain:

[0087]

[0088]

[0089] until……

[0090]

[0091] In other embodiments, the present invention provides a digital filtering processing method applied to an FIR digital filtering device based on a DSP processor, comprising the following steps, such as... Figure 2 As shown:

[0092] Step S100: Input a signal vector x of length N, x = [x0, x1, ..., x2] N-1 ];

[0093] Step S200: Input a state vector s of length M, s = [s0, s1, ..., s200]. M-1 ];

[0094] Step S300: Concatenate the signal vector x and the state vector s using a matrix to generate an extended vector z, z = s|x = [s0, s1, ..., s2]. M-1 ,x0,x1,···,x N-1 ], put it into the cache.

[0095] Step S400: Input a coefficient vector c of length M, c = [c0, c1, ..., c2] M-1 ];

[0096] Step S500: The block filtering module performs a shift and block processing operation on the input vector, especially the coefficient vector z in the buffer corresponding to the coefficient vector c, to obtain N sample values ​​of the information vector y.

[0097]

[0098] Similarly, we can obtain:

[0099]

[0100]

[0101] until……

[0102]

[0103] Step S700: Output a signal vector y of length N, y = [y0, y1, ..., y2] N-1 ], where N>M.

[0104] In a further embodiment, the digital filtering processing method, step S500 further includes:

[0105] Step S510: In each inner loop, obtain the 3 sample values ​​of vector y in sequence, and obtain the 3 sample values ​​of vector y in M / 2 inner loops;

[0106] Step S520: Perform M / 2 inner loop processing and N / 3 outer loop processing to obtain M*N cumulative terms of the information vector y.

[0107] In a further embodiment, the digital filtering processing method, step S510 further includes: 8

[0108] Step S511: Each loading in the inner loop process loads 2 c-samples covered by the main window and 4 z-samples covered by the subordinate window;

[0109] Step S512: During one loading cycle, the inner loop processing module performs a corresponding shift matching product of the two c samples of the coefficient vector c and the four z samples of the extended vector z. During one loading cycle, the main window moves twice with the two covered c samples, moving one c sample position each time, while the subordinate window remains unchanged.

[0110] Step S513: In a new loading cycle, the main window moves 2 c-sample points to sequentially cover the 2 c-sample points in the sorted order, the subordinate window moves 2 z-sample points to sequentially cover the 4 z-sample points in the sorted order, and the inner loop processing module loads the newly covered 2 c-sample points and the newly covered 4 z-sample points.

[0111] In some embodiments, the digital filtering processing method further includes the following steps after step S520:

[0112] Step S600: Based on the sample points of vector y, classify the corresponding M*N accumulated terms; obtain N sample point values ​​of information vector y.

[0113] In some embodiments, the present invention also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the above-described filtering method.

[0114] In some embodiments, the present invention also provides a computer program product that, when run on a DSP processor-based FIR digital filter device, enables the FIR digital filter device to implement any of the above-described possible filtering methods.

[0115] In other embodiments, Figure 9A hardware configuration block diagram of the FIR digital filtering device 30 is shown. The FIR digital filtering device 30 includes at least one of the following: a tuner / demodulator 310, a mobile communication module 320, a wireless communication module 330, a data acquisition unit 340, an external device interface 350, a controller 360, a display 370, an audio output interface 380, a memory, a power supply, and a user interface. The mobile communication module 320 can provide solutions for wireless communication, including 2G / 3G / 4G / 5G, applied to the terminal under test 30. The mobile communication module 320 may include at least one filter, a switch, a power amplifier, a low noise amplifier (LNA), etc. The mobile communication module 320 can receive electromagnetic waves through an antenna, filter and amplify the received electromagnetic waves, and transmit them to the tuner / demodulator 310 for demodulation. The mobile communication module 320 can also amplify the signal modulated by the tuner / demodulator 310 and convert it into electromagnetic waves for radiation through the antenna. In some embodiments, at least some functional modules of the mobile communication module 320 may be housed in the controller 360. In some embodiments, at least some functional modules of the mobile communication module 320 may be housed in the same device as at least some modules of the controller 360.

[0116] The wireless communication module 330 can provide solutions for wireless communication applications on the terminal under test 30, including wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), and infrared (IR) technologies. The wireless communication module 330 can be one or more devices integrating at least one communication processing module. The wireless communication module 330 receives electromagnetic waves via an antenna, performs frequency modulation and filtering of the electromagnetic wave signals, and sends the processed signal to the controller 360. The wireless communication module 330 can also receive signals to be transmitted from the controller 360, perform frequency modulation and amplification, and then convert them into electromagnetic waves for radiation via the antenna.

[0117] In other embodiments, the collector 340 is used to collect signals from the external environment or to interact with the outside world. For example, the collector 340 includes a light receiver, a sensor for collecting ambient light intensity; or, the collector 340 includes an image collector, such as a camera, which can be used to collect external environmental scenes, user attributes, or user interaction gestures; or, the collector 340 includes a sound collector, such as a microphone, for receiving external sounds.

[0118] In some other embodiments, the external device interface 350 may include, but is not limited to, one or more of the following interfaces: High Definition Multimedia Interface (HDMI), analog or data high-definition component input interface (component), composite video input interface (CVBS), USB input interface (USB), RGB port, etc. It may also be a composite input / output interface formed by multiple of the above interfaces.

[0119] In some other embodiments, the controller 360 and the tuner 310 may be located in different separate devices, that is, the tuner 310 may also be in an external device of the main device where the controller 360 is located, such as an external set-top box.

[0120] In some embodiments, the controller 360 controls the operation of the display device and responds to user operations through various software control programs stored in memory. The controller 360 controls the overall operation of the terminal under test 30. For example, in response to receiving a user command to select a UI object to display on the display 370, the controller 360 can perform operations related to the object selected by the user command.

[0121] In some possible embodiments, the controller 360 includes at least one of a central processing unit (CPU), a video processor, an audio processor, a graphics processing unit (GPU), RAM, ROM, a first to an nth interface for input / output, a communication bus, etc.

[0122] A central processing unit (CPU) is used to execute operating system and application instructions stored in memory, as well as various interactive instructions received from external input, to execute various applications, data, and content in order to ultimately display and play various audio and video content. A CPU can include multiple processors, such as a main processor and one or more subprocessors. A digital signal processor (DSP) is a signal processing module that commonly uses at least one of the following: Fast Fourier Transform (FFT), Finite Impulse Response (FIR) filter, Infinite Impulse Response (IIR) filter, and Convolutional Waveform (CONV).

[0123] In some embodiments, a graphics processor is used to generate at least one of various graphical objects, such as icons, operation menus, and user-input-based graphics. The graphics processor includes an arithmetic logic unit (ALU) that performs calculations based on various user-input interactive commands and displays various objects according to display attributes; it also includes a renderer that renders the various objects obtained from the ALU, the rendered objects being displayed on a monitor.

[0124] In some embodiments, the video processor is configured to receive external video signals and perform at least one of the following video processing operations according to the standard encoding and decoding protocol of the input signals: decompression, decoding, scaling, noise reduction, frame rate conversion, resolution conversion, image synthesis, etc., to obtain a signal that can be directly displayed or played on the test terminal 30.

[0125] In other embodiments of this application, the present invention discloses an FIR digital filtering host based on a DSP processor, such as... Figure 8 As shown, the test host may include: one or more processors 801; memory 802; display 803; one or more application programs (not shown); and one or more computer programs 804. These devices can be connected via one or more communication buses 805. The one or more computer programs 804 are stored in the memory 802 and configured to be executed by the one or more processors 801. The one or more computer programs 804 include instructions that can be used to perform actions such as... Figure 1 , Figure 2 or Figure 7 And the various steps in the corresponding embodiments.

[0126] Through the above description of the embodiments, those skilled in the art will clearly understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. The specific working process of the system, device, and unit described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0127] In the various embodiments of this invention, the functional units can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0128] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiments of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as flash memory, portable hard disk, read-only memory, random access memory, magnetic disk, or optical disk.

[0129] The above description is merely a specific implementation of the embodiments of the present invention, but the protection scope of the embodiments of the present invention is not limited thereto. Any changes or substitutions within the technical scope disclosed in the embodiments of the present invention should be covered within the protection scope of the embodiments of the present invention. Therefore, the protection scope of the embodiments of the present invention should be determined by the protection scope of the claims.

Claims

1. An FIR digital filtering device, characterized in that, It includes an input module, a block filtering module, and an output module; The input module is used to input a signal vector x of length N, a state vector s of length M, and a coefficient vector c of length M, where N>M; The block filtering module includes a first processing module, a second processing module, and a third processing module. The first processing module is used to perform matrix concatenation of the signal vector x and the state vector s to generate an extended vector z. The second processing module is used to perform M / 2 inner loop processing and N / 3 outer loop processing to obtain M*N accumulated terms of the information vector y. The third processing module is used to classify and accumulate the corresponding M*N accumulated terms based on the sample points of the vector y to obtain N sample point values ​​of the signal vector y. The second processing module includes an inner loop module and an outer loop module. The inner loop module is used to obtain 3 sample point values ​​of the vector Y sequentially after each M / 2 inner loop processing. The outer loop module is used to perform N / 3 outer loops in conjunction with the inner loop to obtain the M*N accumulated terms of the vector y. The coefficient vector c has 2 main windows, which cover the first two c samples. The extended vector z has 4 subordinate windows, which cover the first four z samples. Each time the inner loop processing module loads, it loads the 2 c samples covered by the main window and the 4 z samples covered by the subordinate window. In one loading cycle, the inner loop processing module performs a corresponding shift matching product on the 2 c samples of the coefficient vector c and the 4 z samples of the extended vector z. In one loading cycle, the main window moves twice with the 2 covered c samples, moving one c sample position each time, while the subordinate windows remain unchanged. The output module is used to output a signal vector y of length N.

2. The FIR digital filtering device according to claim 1, characterized in that, In a new loading cycle, the main window moves two c-sample points, sequentially covering two c-sample points in the sorted order; the subordinate window moves two z-sample points, sequentially covering four z-sample points in the sorted order; and the inner loop processing module loads the two newly covered c-sample points and the four newly covered z-sample points.

3. A digital filtering method, applied to an FIR digital filtering device based on a DSP processor, characterized in that, Includes the following steps S100: Input signal vector x of length N; Step S200: Input a state vector s of length M; Step S300: Connect the signal vector x and the state vector s using a matrix to generate an extended vector z; Step S400: Input a coefficient vector c of length M; Step S5 00: The block filtering module performs shifting and block processing on the input vector to obtain N sample values ​​of the information vector y, including: Step S510: In each inner loop, obtain 3 sample values ​​of vector Y in sequence, and obtain 3 sample values ​​of vector Y in M / 2 inner loops; Step S520: Perform M / 2 inner loop processing and N / 3 outer loop processing to obtain M*N accumulated terms of information vector y; wherein, step S510 further includes: Step S511: In each loading of the inner loop processing, load 2 c samples covered by the main window and load 4 z samples covered by the subordinate window; Step S512: In one loading period, The inner loop processing module performs a corresponding shift matching product on the two c-sample points of the coefficient vector c and the four z-sample points of the extended vector z. In one loading cycle, the main window moves twice with the two covered c-sample points, moving one c-sample point position each time, while the subordinate window remains unchanged. Step S513: In the new loading cycle, the main window moves two c-sample points, sequentially covering the two c-sample points in the sorted order, and the subordinate window moves two z-sample points, sequentially covering the four z-sample points in the sorted order. The inner loop processing module loads the newly covered two c-sample points and the newly covered four z-sample points. Step S700: Output a signal vector y of length N, where N>M.

4. The digital filtering processing method according to claim 3, characterized in that, The following steps are included after step S520: Step S600: Based on the sample points of vector y, classify the corresponding M*N accumulated terms; obtain the N sample point values ​​of information vector y.

5. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, characterized in that, when the computer program is executed by a processor, it implements the method described in any one of claims 3 to 4.

6. A product comprising a computer program, characterized in that, When the computer program product is run on a DSP processor-based FIR digital filter, the FIR digital filter causes the FIR digital filter to perform the method as described in any one of claims 3 to 4.

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