Semiconductor structure and method of fabricating the same

Abstract

This application provides a semiconductor structure and its fabrication method. The semiconductor structure includes, from bottom to top, a substrate, a heterojunction, a P-type ion-doped layer, and a gate insulating layer. The heterojunction includes a source region, a drain region, and a gate region. The P-type ion-doped layer on the gate region includes an active region and a non-active region. P-type doped ions in the active region are activated, while P-type doped ions in the non-active region are passivated. The non-active region includes at least two regions spaced apart in a direction perpendicular to the line connecting the source and drain regions. The gate insulating layer is located on the non-active region and is used to expose the active region. Using the gate insulating layer as a mask layer when activating the P-type doped ions avoids etching the P-type ion-doped layer, thereby preventing the loss of the heterojunction due to etching. Furthermore, the spaced non-active regions can isolate the active region, increase the width of the depletion region, change the electric field distribution between the gate and drain, and improve the breakdown voltage of the semiconductor structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] As a typical representative of third-generation semiconductor materials, group III nitrides, with their wide bandgap semiconductors, have excellent properties such as large bandgap, high voltage resistance, high temperature resistance, high electron saturation velocity and drift velocity, and easy formation of high-quality heterostructures. They are very suitable for manufacturing high-temperature, high-frequency, and high-power electronic devices.

[0003] For example, AlGaN / GaN heterojunctions have strong spontaneous polarization and piezoelectric polarization, resulting in a high concentration of two-dimensional electron gas (2DEG) at the AlGaN / GaN interface. They are widely used in semiconductor structures such as high electron mobility transistors (HEMTs).

[0004] Enhancement-mode devices have a wide range of applications in power electronics due to their normally-off nature. There are many ways to implement enhancement-mode devices, such as by using a P-type semiconductor at the gate to deplete the two-dimensional electron gas.

[0005] In planar devices, current flows along the plane within the quantum well formed by the heterojunction. Under reverse bias, the electric field distribution is typically non-uniform, generally resulting in severe electric field concentration at the gate or drain edges. This electric field increases rapidly with increasing reverse voltage, and the device breaks down when the critical breakdown field strength is reached.

[0006] A higher breakdown voltage means a wider operating voltage range, higher power density, and greater reliability. Therefore, improving the breakdown voltage of devices is a key focus for electronic device researchers. Summary of the Invention

[0007] However, the inventors of this application have discovered that enhancement-mode devices achieved by placing a P-type semiconductor at the gate require etching the P-type semiconductor outside the gate region, but etching inevitably leads to etching losses. Furthermore, the breakdown voltage needs to be improved.

[0008] To address the above problems, the present invention provides a semiconductor structure comprising:

[0009] The substrate, heterojunction, P-type ion doped layer, and gate insulating layer are distributed from bottom to top. The heterojunction includes a source region, a drain region, and a gate region located between the source region and the drain region. The P-type ion doped layer on the gate region includes an active region and a non-active region. The P-type doped ions in the active region are activated, and the P-type doped ions in the non-active region are passivated. The non-active region includes at least two regions and is spaced apart in a direction perpendicular to the line connecting the source region and the drain region. The gate insulating layer is located on the non-active region and is used to expose the active region.

[0010] Optionally, the semiconductor structure further includes a source, a drain, and a gate, wherein the gate is located on the gate insulating layer, the source is located on the source region of the heterojunction, and the drain is located on the drain region of the heterojunction.

[0011] Optionally, the gates are electrically connected together.

[0012] Optionally, the P-type ion doped layer on the drain region includes a drain activation region, in which the P-type doped ions are activated.

[0013] Optionally, the semiconductor structure further includes a source, a drain, and a gate, wherein the gate is located on the gate insulating layer, the source is located on the source region, and the drain is located on the drain active region and the drain region.

[0014] Optionally, the gates are electrically connected together.

[0015] Optionally, the heterojunction includes a channel layer and a barrier layer from bottom to top.

[0016] Optionally, the heterojunction includes a channel layer and a barrier layer from bottom to top; the source and the drain are in contact with the channel layer or the barrier layer.

[0017] Optionally, the material of the P-type ion-doped layer includes a group III nitride material.

[0018] Optionally, the gate insulating layer is a single-layer structure or a stacked structure.

[0019] Another aspect of the present invention provides a method for fabricating a semiconductor structure, comprising:

[0020] A substrate is provided on which a heterojunction, a P-type ion-doped layer, and an insulating material layer are sequentially formed; the heterojunction includes a source region, a drain region, and a gate region located between the source region and the drain region;

[0021] The insulating material layer is patterned to form a gate insulating layer to expose a portion of the P-type ion-doped layer; the gate insulating layer includes at least two regions and is spaced apart in a direction perpendicular to the line connecting the source region and the drain region;

[0022] Using the gate insulating layer as a mask, the P-type doped ions in the exposed P-type ion doped layer are activated to form an activation region.

[0023] Optionally, the P-type doped ions are activated by annealing at a temperature greater than 500°C.

[0024] Optionally, the P-type doped ions are activated in a nitrogen atmosphere, a mixture of nitrogen and oxygen, nitrous oxide, or argon atmosphere.

[0025] Optionally, the fabrication method further includes: forming a gate on the gate insulating layer, forming a source on the source region of the heterojunction, and forming a drain on the drain region of the heterojunction.

[0026] Optionally, when the P-type doped ions in the exposed P-type ion doped layer are activated using the gate insulating layer as a mask, the P-type ion doped layer on the drain region is also activated to form a drain activation region.

[0027] Optionally, the fabrication method further includes: forming a gate on the gate insulating layer, forming a source on the source region, and forming a drain on the drain active region and the drain region.

[0028] Optionally, the heterojunction includes a channel layer and a barrier layer from bottom to top.

[0029] Optionally, the heterojunction includes a channel layer and a barrier layer from bottom to top; the source and the drain are in contact with the channel layer or the barrier layer.

[0030] Optionally, the material of the P-type ion-doped layer includes a group III nitride material.

[0031] Optionally, the gate insulating layer is a single-layer structure or a stacked structure.

[0032] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0033] 1) The semiconductor structure of the present invention includes, from bottom to top, a substrate, a heterojunction, a P-type ion-doped layer, and a gate insulating layer. The heterojunction includes a source region, a drain region, and a gate region. The P-type ion-doped layer on the gate region includes an active region and a non-active region. P-type doped ions in the active region are activated, while P-type doped ions in the non-active region are passivated. The non-active region includes at least two regions spaced apart in a direction perpendicular to the line connecting the source and drain regions. The gate insulating layer is located on the non-active region and is used to expose the active region. Using the gate insulating layer as a mask layer for activating the P-type doped ions allows the regions not covered by the gate insulating layer to form active regions, and the regions covered by the gate insulating layer to form non-active regions. This avoids etching the P-type ion-doped layer, thereby preventing the loss of the heterojunction due to etching. Furthermore, the spaced non-active regions separate the active regions, increasing the width of the depletion region, changing the electric field distribution between the gate and drain, and improving the reverse breakdown voltage of the semiconductor structure.

[0034] 2) In the optional scheme, the heterojunction includes a channel layer and a barrier layer from bottom to top. Specifically, a) the channel layer and the barrier layer can each have one layer; or b) the channel layer and the barrier layer can each have multiple layers, which are alternately distributed; or c) one channel layer and two or more barrier layers to meet different functional requirements.

[0035] 3) In an optional embodiment, the heterojunction includes a group III nitride material. Group III nitride materials may include any one or a combination of GaN, AlGaN, and AlInGaN. The semiconductor structure of this invention has strong compatibility with existing HEMT devices.

[0036] 4) In the optional schemes, a) the gate insulating layer is a single-layer structure, and the material of the single-layer structure includes one or more of SiN, AlN, AlO, AlON, SiO, and HfO; or b) the gate insulating layer is a multilayer structure, and the material of any layer in the multilayer structure includes one of SiN, AlN, AlO, AlON, SiO, and HfO. Regardless of scheme a) or b), the gate insulating layer can be used as a mask when activating P-type doped ions. This is because: in the P-type ion doped layer covered by the gate insulating layer, H atoms in the P-type ion doped layer cannot escape due to the obstruction of the gate insulating layer. The H atoms will combine with P-type doped ions (e.g., Mg ions), thus passivating the P-type doped ions and preventing them from generating holes; while in the P-type ion doped layer not covered by the gate insulating layer, H atoms can escape, thus activating the P-type doped ions.

[0037] 5) In the optional scheme, the P-type ion doped layer on the drain region includes a drain activation region, in which the P-type doped ions are activated. The drain activation region can be activated in the same process and using the same method as the activation region in the P-type ion doped layer, ensuring process compatibility. Attached Figure Description

[0038] Figure 1 This is a top view of the semiconductor structure according to the first embodiment of the present invention;

[0039] Figure 2 It is along Figure 1 A sectional view of line AA in the diagram;

[0040] Figure 3 It is along Figure 1 A sectional view of the BB line in the middle;

[0041] Figure 4 This is a flowchart of a method for fabricating a semiconductor structure according to the first embodiment of the present invention;

[0042] Figure 5 yes Figure 4 A schematic diagram of the intermediate structure corresponding to the process in the document;

[0043] Figure 6 This is a cross-sectional schematic diagram of the semiconductor structure according to the second embodiment of the present invention;

[0044] Figure 7 This is a top view of the semiconductor structure according to the third embodiment of the present invention;

[0045] Figure 8 This is a top view of the semiconductor structure according to the fourth embodiment of the present invention;

[0046] Figure 9 It is along Figure 8 A cross-sectional view of the CC line in the diagram;

[0047] Figure 10 This is a top view of the semiconductor structure according to the fifth embodiment of the present invention;

[0048] Figure 11 It is along Figure 10 A sectional view of the DD line in the middle;

[0049] Figure 12 This is a cross-sectional schematic diagram of the semiconductor structure according to the sixth embodiment of the present invention.

[0050] To facilitate understanding of this invention, all reference numerals appearing in the accompanying drawings are listed below:

[0051] Semiconductor structure 1, 2, 3, 4, 5, 6; Substrate 10

[0052] Heterojunction 11, Channel layer 11a

[0053] Barrier layer 11b Gate region 11c

[0054] Source region 11d, Drain region 11e

[0055] P-type ion doped layer 12, active region 121

[0056] Non-active region 122 Gate insulating layer 13

[0057] Gate 14a Source 14b

[0058] Drain 14c Insulating material layer 13'

[0059] Leakage area activation area 123 Detailed Implementation

[0060] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0061] Figure 1 This is a top view of the semiconductor structure according to the first embodiment of the present invention. Figure 2 It is along Figure 1 A cross-sectional view of line AA in the middle. Figure 3 It is along Figure 1 A cross-sectional view of the BB line.

[0062] Reference Figures 1 to 3 As shown, semiconductor structure 1 includes:

[0063] The substrate 10, heterojunction 11, P-type ion doped layer 12, and gate insulating layer 13 are distributed from bottom to top. The heterojunction 11 includes a source region 11d, a drain region 11e, and a gate region 11c located between the source region 11d and the drain region 11e. The P-type ion doped layer 12 on the gate region 11c includes an active region 121 and an inactive region 122. The P-type doped ions in the active region 121 are activated, and the P-type doped ions in the inactive region 122 are passivated. The inactive region 122 includes at least two regions and is spaced apart in a direction perpendicular to the line connecting the source region 11d and the drain region 11e. The gate insulating layer 13 is located on the inactive region 122 and is used to expose the active region 121.

[0064] The source 14b, drain 14c and gate 14a are located on the gate insulating layer 13, the source 14b is located on the source region 11d of the heterojunction 11, and the drain 14c is located on the drain region 11e of the heterojunction 11.

[0065] The substrate 10 can be made of sapphire, silicon carbide, silicon, diamond, GaN, or one of sapphire, silicon carbide, silicon, diamond, or GaN on it.

[0066] Heterojunction 11 may include group III nitride materials.

[0067] The heterojunction 11 may include a channel layer 11a and a barrier layer 11b from bottom to top. A two-dimensional electron gas can be formed at the interface between the channel layer 11a and the barrier layer 11b. In one alternative embodiment, the channel layer 11a is an intrinsic GaN layer, and the barrier layer 11b is an N-type AlGaN layer. In other alternative embodiments, the material combination of the channel layer 11a and the barrier layer 11b can also be GaN / AlN, GaN / InN, GaN / InAlGaN, GaAs / AlGaAs, GaN / InAlN, or InN / InAlN. In addition, besides Figure 2 The channel layer 11a and barrier layer 11b shown each have one layer; the channel layer 11a and barrier layer 11b may also have multiple layers, which are alternately distributed; or one channel layer 11a and two or more barrier layers 11b to form a multi-barrier structure.

[0068] The source region 11d of the heterojunction 11 is used to form the source 14b, the drain region 11e is used to form the drain 14c, and the gate region 11c is used to form the gate 14a.

[0069] From bottom to top, the heterojunction 11 and the substrate 10 may also have a nucleation layer and a buffer layer (not shown). The nucleation layer can be made of materials such as AlN or AlGaN, and the buffer layer can be made of at least one of AlN, GaN, AlGaN, and AlInGaN. The nucleation layer can alleviate the problems of lattice mismatch and thermal mismatch between the epitaxially grown semiconductor layer, such as the channel layer 11a in the heterojunction 11, and the substrate 10. The buffer layer can reduce the dislocation density and defect density of the epitaxially grown semiconductor layer, thereby improving the crystal quality.

[0070] The material of the p-type ion doped layer 12 can be a group III nitride material, such as at least one of GaN, AlGaN, and AlInGaN. The p-type dopant ions can be at least one of Mg ions, Zn ions, Ca ions, Sr ions, or Ba ions to deplete the two-dimensional electron gas below the gate region to form an enhancement-mode device.

[0071] The activation of P-type doped ions in active region 121 means that P-type doped ions can generate holes. The deactivated region 122 means that the P-type doped ions therein are passivated and cannot generate holes.

[0072] Figures 1 to 3 In the illustrated embodiment, the inactive area 122 comprises three regions. In other embodiments, the inactive area 122 may also comprise two or more regions.

[0073] The function of the multiple non-active regions 122 being distributed laterally in the direction perpendicular to the line connecting the source region 11d and the drain region 11e is as follows: under reverse bias conditions (i.e., in the off state), the active region 121 can deplete the two-dimensional electron gas below the gate region 11c; the spacing of the non-active regions 122 can isolate the active region 121, increase the width of the depletion region, change the electric field distribution between the gate and drain, and improve the reverse breakdown voltage (i.e., the off-state breakdown voltage) of the semiconductor structure 1.

[0074] In some embodiments, the gate insulating layer 13 may be a single-layer structure, and the material of the single-layer structure may include one or more of SiN, AlN, AlO, AlON, SiO and HfO.

[0075] In other embodiments, the gate insulating layer 13 may be a stacked structure, and the material of any layer in the stacked structure may include one of SiN, AlN, AlO, AlON, SiO and HfO.

[0076] In some other embodiments, certain portions of the gate insulating layer 13 may also contain H atoms.

[0077] Figure 2 In this structure, the source 14b and drain 14c are in contact with the barrier layer 11b, and ohmic contacts are formed between the source 14b and the barrier layer 11b, and between the drain 14c and the barrier layer 11b. The gate 14a and the barrier layer 11b form a Schottky contact with the gate insulating layer 13 through the non-active region 122. The source 14b, drain 14c, and gate 14a can be made of metal, such as existing conductive materials like Ti / Al / Ni / Au and Ni / Au.

[0078] In some embodiments, ohmic contacts can be formed between the source 14b and the barrier layer 11b, and between the drain 14c and the barrier layer 11b, using N-type ion heavily doped layers. The N-type ion heavily doped layers enable the source 14b to directly form ohmic contact layers with the source region 11d of the heterojunction 11, and the drain 14c to the drain region 11e of the heterojunction 11, without high-temperature annealing. This also avoids the performance degradation and reduced electron mobility of the heterojunction 11 caused by the high temperatures during annealing.

[0079] In some embodiments, at least one of the source region 11d and drain region 11e of the heterojunction 11 may have an N-type ion heavily doped layer. The source region 11d and source 14b of the heterojunction 11 without an N-type ion heavily doped layer, or the drain region 11e and drain 14c of the heterojunction 11 without an N-type ion heavily doped layer, may form an ohmic contact layer by high-temperature annealing.

[0080] In an N-type ion heavily doped layer, the N-type ions can be at least one of Si, Ge, Sn, Se, or Te ions. For different N-type ions, the doping concentration can be greater than 1E19 / cm². 3 The N-type ion-doped layer can be a group III nitride material, such as at least one of GaN, AlGaN, and AlInGaN.

[0081] Figure 4 This is a flowchart of a method for fabricating a semiconductor structure according to the first embodiment of the present invention; Figure 5 yes Figure 4 The diagram shows the intermediate structure corresponding to the process flow.

[0082] First, refer to Figure 4 Step S1 in Figure 5 , Figures 1 to 3 As shown, a substrate 10 is provided, on which a heterojunction 11, a P-type ion doped layer 12 and an insulating material layer 13' are sequentially formed; the heterojunction 11 includes a source region 11d, a drain region 11e and a gate region 11c located between the source region 11d and the drain region 11e.

[0083] The substrate 10 can be made of sapphire, silicon carbide, silicon, diamond, GaN, or one of sapphire, silicon carbide, silicon, diamond, or GaN on it.

[0084] Heterojunction 11 may include group III nitride materials.

[0085] The heterojunction 11 may include a channel layer 11a and a barrier layer 11b from bottom to top. In one alternative embodiment, the channel layer 11a is an intrinsic GaN layer, and the barrier layer 11b is an N-type AlGaN layer. In other alternative embodiments, the combination of the channel layer 11a and the barrier layer 11b may also be GaN / AlN, GaN / InN, GaN / InAlGaN, GaAs / AlGaAs, GaN / InAlN, or InN / InAlN. The formation process of the channel layer 11a and the barrier layer 11b may include: atomic layer deposition (ALD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), metal-organic chemical vapor deposition (MOCVD), or a combination thereof.

[0086] Apart from Figure 5 The channel layer 11a and barrier layer 11b shown each have one layer; the channel layer 11a and barrier layer 11b may also have multiple layers, which are alternately distributed; or one channel layer 11a and two or more barrier layers 11b to form a multi-barrier structure.

[0087] Before forming the heterojunction 11 on the substrate 10, a nucleation layer and a buffer layer (not shown) can be formed sequentially. The nucleation layer can be made of materials such as AlN or AlGaN, and the buffer layer can be made of at least one of AlN, GaN, AlGaN, and AlInGaN. The method for forming the buffer layer can be the same as the method for forming the heterojunction 11. The nucleation layer can alleviate the problems of lattice mismatch and thermal mismatch between the epitaxially grown semiconductor layer, such as the channel layer 11a in the heterojunction 11, and the substrate 10. The buffer layer can reduce the dislocation density and defect density of the epitaxially grown semiconductor layer, thereby improving the crystal quality.

[0088] The material of the p-type ion-doped layer 12 can be a group III nitride material, such as at least one of GaN, AlGaN, and AlInGaN, wherein the p-type dopant ion can be at least one of Mg ions, Zn ions, Ca ions, Sr ions, or Ba ions. The formation process of the p-type ion-doped layer 12 can refer to the formation process of the channel layer 11a and the barrier layer 11b.

[0089] In this embodiment, an insulating material layer 13' is formed on the P-type ion-doped layer 12 without activation.

[0090] In some embodiments, the insulating material layer 13' can be a single-layer structure, and the material of the single-layer structure can include one or more of SiN, AlN, AlO, AlON, SiO and HfO.

[0091] In other embodiments, the insulating material layer 13' may be a stacked structure, and the material of any layer in the stacked structure may include one of SiN, AlN, AlO, AlON, SiO and HfO.

[0092] In some other embodiments, certain portions of the insulating layer 13' may also contain H atoms.

[0093] Next, refer to Figure 4 Step S2 in Figure 5 , Figures 1 to 3 As shown, a patterned insulating material layer 13' forms a gate insulating layer 13 to expose a portion of the P-type ion-doped layer 12; the gate insulating layer 13 includes at least two regions and is spaced apart in a direction perpendicular to the line connecting the source region 11d and the drain region 11e.

[0094] The patterned insulating material layer 13' can be achieved using dry etching or wet etching. Specifically, a patterned mask layer is first formed on the insulating material layer 13'. The mask layer can be a photoresist layer, and patterning is performed using a pre-exposure, post-development process. The dry etching gas can be CF4, C3F8, etc., and the wet etching solution can be hot phosphoric acid.

[0095] The gate insulating layer 13 is spaced apart in the direction perpendicular to the line connecting the source region 11d and the drain region 11e, and its function is to form spaced non-active regions 122 and separate the active regions 121.

[0096] Then, refer to Figure 4 Step S3 in Figures 1 to 3 As shown, using the gate insulating layer 13 as a mask, the P-type doped ions in the exposed P-type ion doped layer 12 are activated to form an activation region 121.

[0097] In the process environment for growing the p-type ion-doped layer 12, such as the MOCVD growth environment, there are a large number of H atoms. If they are not removed, the p-type dopant ions (acceptor dopants, such as Mg ions) in the group III nitride material will bond with the H atoms, that is, they will be passivated by a large number of H atoms and will not generate holes. Exposing the p-type ion-doped layer 12 can provide an escape path for releasing H atoms.

[0098] Therefore, in the P-type ion doped layer 12 covered by the gate insulating layer 13, H atoms cannot escape due to the obstruction of the gate insulating layer 13. The H atoms will combine with the P-type dopant ions (such as Mg ions), thus passivating the P-type dopant ions and preventing them from generating holes; correspondingly forming the non-active region 122. On the other hand, in the P-type ion doped layer 12 exposed by the gate insulating layer 13, H atoms can escape, thus activating the P-type dopant ions; correspondingly forming the active region 121.

[0099] As can be seen, using the gate insulating layer 13 as a mask layer when activating P-type doped ions results in the region of the P-type ion doped layer 12 not covered by the gate insulating layer 13 forming the active region 121, and the region covered by the gate insulating layer 13 forming the inactive region 122. The advantage is that etching of the P-type ion doped layer 12 can be avoided, thereby avoiding the loss of the heterojunction 11 caused by etching.

[0100] In some embodiments, high-temperature annealing is performed in an inert gas, such as at temperatures above 500°C, to activate P-type dopant ions and prevent the introduction of H atoms. In other embodiments, P-type dopant ions can be activated in a hydrogen-free atmosphere, such as nitrogen, a mixture of nitrogen and oxygen, nitrous oxide (NO), or argon. During high-temperature annealing, nitrogen molecules and their decomposition products can effectively penetrate into the surface of the group III nitride material, effectively compensating for nitrogen vacancies created during etching and improving the quality of the activated region 121.

[0101] Next, refer to Figure 4 Step S4 in Figures 1 to 3 As shown, a gate 14a is formed on the gate insulating layer 13, a source 14b is formed on the source region 11d of the heterojunction 11, and a drain 14c is formed on the drain region 11e of the heterojunction 11.

[0102] The source 14b, drain 14c, and gate 14a can be made of metal, such as existing conductive materials like Ti / Al / Ni / Au and Ni / Au, and are formed using physical vapor deposition or chemical vapor deposition methods.

[0103] Before forming the source 14b, drain 14c, and gate 14a, an N-type ion heavily doped layer (not shown) can be formed on the source region 11d and drain region 11e of the heterojunction 11. The N-type ion heavily doped layer enables the source 14b and the source region 11d of the heterojunction 11, and the drain 14c and the drain region 11e of the heterojunction 11, to directly form an ohmic contact layer without high-temperature annealing.

[0104] The N-type ion heavily doped layer can be a group III nitride material, such as at least one of GaN, AlGaN, and AlInGaN, wherein the N-type dopant ions can be at least one of Si ions, Ge ions, Sn ions, Se ions, or Te ions. The formation process of the N-type ion heavily doped layer can refer to the formation process of the channel layer 11a and the barrier layer 11b, and N-type ions can be doped while growing, or N-type ions can be implanted after epitaxial growth. In some embodiments, the growth temperature of the N-type ion heavily doped layer can be lower than 1000°C, preferably lower than 800°C, to avoid secondary passivation of the activated P-type dopant ions.

[0105] In the N-type ion heavily doped layer growth process, the gate insulating layer 13 can be used as a mask layer to prevent the N-type ion heavily doped layer from forming on it.

[0106] In some embodiments, an N-type ion heavily doped layer may also be formed on at least one of the source region 11d and the drain region 11e of the heterojunction 11.

[0107] For the source region 11d and source 14b of the heterojunction 11 without N-type ion heavy doping layer, or the drain region 11e and drain 14c of the heterojunction 11 without N-type ion heavy doping layer, an ohmic contact layer can be formed by high-temperature annealing.

[0108] Figure 6 This is a cross-sectional schematic diagram of the semiconductor structure according to the second embodiment of the present invention.

[0109] Reference Figure 6 , Figures 1 to 3 As shown, the semiconductor structure 2 in this embodiment is largely the same as the semiconductor structure 1 in embodiment 1, except that the source 14b and the drain 14c are in contact with the channel layer 11a, and an ohmic contact is formed between the source 14b and the channel layer 11a, and between the drain 14c and the channel layer 11a.

[0110] Correspondingly, the method for fabricating the semiconductor structure 2 in this embodiment is largely the same as the method for fabricating the semiconductor structure 1 in this embodiment, except that: in step S4, when forming the source 14b on the source region 11d of the heterojunction 11 and the drain 14c on the drain region 11e, the gate insulating layer 13, the P-type ion doped layer 12 (specifically the non-active region 122) and the barrier layer 11b of the source region 11d and the drain region 11e are removed to expose the channel layer 11a.

[0111] In some embodiments, ohmic contacts can also be formed between the source 14b and the channel layer 11a, and between the drain 14c and the channel layer 11a, using N-type ion heavily doped layers. The N-type ion heavily doped layers enable the formation of ohmic contact layers between the source 14b and the channel layer 11a, and between the drain 14c and the channel layer 11a, without the need for high-temperature annealing.

[0112] In some embodiments, an ohmic contact is formed between the source 14b and the channel layer 11a, or between the drain 14c and the channel layer 11a, using an N-type ion heavily doped layer. An ohmic contact layer can be formed between the channel layer 11a and the source 14b, or between the channel layer 11a and the drain 14c, without an N-type ion heavily doped layer, through high-temperature annealing.

[0113] Figure 7 This is a top view of the semiconductor structure according to the third embodiment of the present invention.

[0114] Reference Figure 7 , Figure 6 , Figures 1 to 3 As shown, the semiconductor structure 3 of this embodiment is largely the same as the semiconductor structures 1 and 2 of embodiments 1 and 2, the only difference being that each gate 14a is electrically connected together.

[0115] The gates 14a are electrically connected together to facilitate the application of voltage to each gate 14a.

[0116] Specifically, an electrical connection layer can be provided at both ends of each gate 14a to electrically connect each gate 14a. The electrical connection layer can be located in the same layer as the gate 14a and fabricated in the same process.

[0117] In some embodiments, the aforementioned electrical connection layer may also be disposed only at one end of each gate 14a.

[0118] In some other embodiments, the electrical connection layer may also be disposed above each gate 14a, and the electrical connection layer and the active region 121 are electrically insulated from each other by an insulating layer.

[0119] Figure 8 This is a top view of the semiconductor structure according to the fourth embodiment of the present invention. Figure 9 It is along Figure 8 A cross-sectional view of the CC line.

[0120] Reference Figure 8 , Figure 9 , Figure 7 , Figure 6 , Figures 1 to 3As shown, the semiconductor structure 4 in this embodiment is largely the same as the semiconductor structures 1, 2, and 3 in embodiments 1, 2, and 3, with the only difference being that the semiconductor structure 4 is an intermediate semiconductor structure and does not have a gate 14a, a source 14b, and a drain 14c.

[0121] Correspondingly, the method for fabricating the semiconductor structure 4 in this embodiment is roughly the same as the method for fabricating the semiconductor structures 1, 2, and 3 in embodiments 1, 2, and 3, with the only difference being that step S4 is omitted.

[0122] Semiconductor structure 4 can be produced and sold as a semi-finished product.

[0123] Figure 10 This is a top view of the semiconductor structure according to the fifth embodiment of the present invention. Figure 11 It is along Figure 10 A cross-sectional view of the DD line.

[0124] Reference Figure 10 , Figure 11 , Figure 8 and Figure 9 As shown, the semiconductor structure 5 in this embodiment 5 is largely the same as the semiconductor structure 4 in embodiment 4, except that the P-type ion doped layer 12 on the drain region 11e includes a drain activation region 123, and the P-type doped ions in the drain activation region 123 are activated.

[0125] The size of the active region 123 is smaller than the size of the drain region 11e, so as to expose part of the drain region 11e.

[0126] Regarding the fabrication method, the drain activation region 123 can be activated in the same process and using the same method as the activation region 121 in the P-type ion doped layer 12, making the process compatible.

[0127] Semiconductor structure 5 can be produced and sold as a semi-finished product.

[0128] Figure 12 This is a cross-sectional schematic diagram of the semiconductor structure according to the sixth embodiment of the present invention.

[0129] Reference Figure 12 , Figure 10 and Figure 11 As shown, the semiconductor structure 6 of this embodiment is largely the same as the semiconductor structure 5 of embodiment 5, except that the semiconductor structure 5 further includes a source 14b, a drain 14c and a gate 14a. The gate 14a is located on the gate insulating layer 13, the source 14b is located on the source region 11d, and the drain 14c is located on the drain active region 123 and the drain region 11e.

[0130] The source 14b, drain 14c, and gate 14a can be made of metal, such as existing conductive materials like Ti / Al / Ni / Au and Ni / Au, and are formed using physical vapor deposition or chemical vapor deposition methods.

[0131] The semiconductor structure 6 of this embodiment can also be combined with the semiconductor structure 3 of embodiment 3 to electrically connect multiple gates 14a together.

[0132] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate (10), a heterojunction (11), a P-type ion doped layer (12), and a gate insulating layer (13) are distributed from bottom to top; the heterojunction (11) includes a source region (11d), a drain region (11e), and a gate region (11c) located between the source region (11d) and the drain region (11e); the P-type ion doped layer (12) on the gate region (11c) includes an active region (121) and an inactive region (122); the P-type doped ions in the active region (121) are activated, and the P-type doped ions in the inactive region (122) are passivated; the inactive region (122) includes at least two regions and is spaced apart in a direction perpendicular to the line connecting the source region (11d) and the drain region (11e); the gate insulating layer (13) is located on the inactive region (122) and is used to expose the active region (121); and The gate (14a) is located on the gate insulating layer (13) and does not contact the P-type ion doped layer (12).

2. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes a source (14b) and a drain (14c), wherein the source (14b) is located on the source region (11d) of the heterojunction (11) and the drain (14c) is located on the drain region (11e) of the heterojunction (11).

3. The semiconductor structure according to claim 2, characterized in that, Each of the gates (14a) is electrically connected together.

4. The semiconductor structure according to claim 1, characterized in that, The P-type ion doped layer (12) on the drain region (11e) includes a drain activation region (123) in which the P-type doped ions are activated.

5. The semiconductor structure according to claim 4, characterized in that, The semiconductor structure further includes a source (14b), a drain (14c), and a gate (14a), wherein the gate (14a) is located on the gate insulating layer (13), the source (14b) is located on the source region (11d), and the drain (14c) is located on the drain active region (123) and the drain region (11e).

6. The semiconductor structure according to claim 5, characterized in that, Each of the gates (14a) is electrically connected together.

7. The semiconductor structure according to claim 1, characterized in that, The heterojunction (11) includes a channel layer (11a) and a barrier layer (11b) from bottom to top.

8. The semiconductor structure according to claim 2 or 5, characterized in that, The heterojunction (11) includes a channel layer (11a) and a barrier layer (11b) from bottom to top; the source (14b) and the drain (14c) are in contact with the channel layer (11a) or the barrier layer (11b).

9. The semiconductor structure according to claim 1, characterized in that, The material of the P-type ion-doped layer (12) includes group III nitride materials.

10. The semiconductor structure according to claim 1, characterized in that, The gate insulating layer (13) is a single-layer structure or a stacked structure.

11. A method for fabricating a semiconductor structure, characterized in that, include: A substrate (10) is provided, on which a heterojunction (11), a P-type ion-doped layer (12), and an insulating material layer (13') are sequentially formed; the heterojunction (11) includes a source region (11d), a drain region (11e), and a gate region (11c) located between the source region (11d) and the drain region (11e); The insulating material layer (13') is patterned to form a gate insulating layer (13) to expose a portion of the P-type ion-doped layer (12); the gate insulating layer (13) comprises at least two regions and is spaced apart in a direction perpendicular to the line connecting the source region (11d) and the drain region (11e); Using the gate insulating layer (13) as a mask, the P-type doped ions in the exposed P-type ion doped layer (12) are activated to form an activation region (121); A gate (14a) is formed on the gate insulating layer (13), and the gate (14a) does not contact the P-type ion doped layer (12).

12. The method for fabricating a semiconductor structure according to claim 11, characterized in that, The P-type doped ions are activated by annealing at temperatures above 500°C.

13. The method for fabricating a semiconductor structure according to claim 12, characterized in that, The P-type doped ions are activated in a nitrogen atmosphere, a mixture of nitrogen and oxygen, nitrous oxide, or argon atmosphere.

14. The method for fabricating a semiconductor structure according to claim 11, characterized in that, The fabrication method further includes: forming a gate (14a) on the gate insulating layer (13), forming a source (14b) on the source region (11d) of the heterojunction (11), and forming a drain (14c) on the drain region (11e) of the heterojunction (11).

15. The method for fabricating a semiconductor structure according to claim 11, characterized in that, When the P-type doped ions in the exposed P-type doped layer (12) are activated using the gate insulating layer (13) as a mask, the P-type doped layer (12) on the drain region (11e) is also activated to form a drain activation region (123).

16. The method for fabricating a semiconductor structure according to claim 15, characterized in that, The fabrication method further includes forming a source (14b) on the source region (11d) and forming a drain (14c) on the drain activation region (123) and the drain region (11e).

17. The method for fabricating a semiconductor structure according to claim 11, characterized in that, The heterojunction (11) includes a channel layer (11a) and a barrier layer (11b) from bottom to top.

18. The method for fabricating a semiconductor structure according to claim 14 or 16, characterized in that, The heterojunction (11) includes a channel layer (11a) and a barrier layer (11b) from bottom to top; the source (14b) and the drain (14c) are in contact with the channel layer (11a) or the barrier layer (11b).

19. The method for fabricating a semiconductor structure according to claim 11, characterized in that, The material of the P-type ion-doped layer (12) includes group III nitride materials.

20. The method for fabricating a semiconductor structure according to claim 11, characterized in that, The gate insulating layer (13) is a single-layer structure or a stacked structure.

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