Method and apparatus for circulating current suppression in an inverter parallel system

Abstract

The application relates to a circulating current suppression method and device in an inverter parallel system, and relates to the power supply field, which can suppress the circulating current in the inverter parallel system and improve the reliability of inverter components. The common-mode current and common-mode injection voltage of each inverter in the inverter parallel system are acquired (S801); the virtual damping voltage of each inverter is determined based on the common-mode current of each inverter and a preset common-mode damping coefficient (S802); wherein, if the direction of the current flowing out of the inverter is the positive direction, the preset common-mode damping coefficient is a negative value; if the direction of the current flowing into the inverter is the positive direction, the preset common-mode damping coefficient is a positive value; the virtual damping voltage is superimposed on the common-mode injection voltage of each inverter to obtain the target common-mode voltage of each inverter (S803); and each inverter is controlled to operate based on the target common-mode voltage of each inverter and the differential-mode voltage of each inverter (S804).

Description

Technical Field

[0001] This application relates to the field of power supply, and more particularly to a circulating current suppression method and apparatus in a parallel inverter system. Background Technology

[0002] An inverter is a device that converts direct current (DC) to alternating current (AC). Typically, to increase the power capacity of an inverter, multiple inverters can be connected together in series or parallel. However, connecting multiple inverters in series or parallel often creates a circulating current loop. This circulating current can affect inverter efficiency and easily trigger overcurrent protection.

[0003] Figure 1 For a parallel inverter system, such as Figure 1 As shown, the inverter parallel system includes four inverters, namely inverter 1 to inverter 4, wherein the DC input terminals of inverters 1 to inverter 4 are respectively connected to four direct current (DC) power supplies (e.g., Figure 1 The DC input terminals of inverters 1 to 4 are connected to DC1 to DC4 respectively. The AC output terminals of inverters 1 and 3 are connected in parallel, and the AC output terminals of inverters 2 and 4 are also connected in parallel. If there is a difference between the sum of the DC bus voltages of inverter 1 and inverter 2 and the sum of the DC bus voltages of inverter 3 and inverter 4, a circulating current will form among these four inverters, affecting the normal operation of the parallel inverter system.

[0004] To suppress circulating current in a parallel inverter system, one approach is to connect the positive and negative buses of the inverters in parallel via hardware wiring, ensuring consistent bus voltages across multiple inverters. However, this approach requires additional DC parallel cabling, resulting in a significant initial investment and poor economic efficiency. Another approach involves monitoring and adjusting the DC bus voltages of different inverters. However, this is an open-loop control method, and even slight differences in the detected DC bus voltages of different inverters can still lead to substantial circulating currents. Summary of the Invention

[0005] This application provides a circulating current suppression method and apparatus in a parallel inverter system, which can suppress circulating current in the parallel inverter system and improve the reliability of inverter components.

[0006] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0007] A first aspect of this application provides a circulating current suppression method in a parallel inverter system. The method includes: acquiring the common-mode current and common-mode injection voltage of each inverter in the parallel inverter system; determining a virtual damping voltage for each inverter based on the common-mode current and a preset common-mode damping coefficient; wherein, if the direction of current outflow from the inverter is taken as the positive direction, the preset common-mode damping coefficient is negative; if the direction of current inflow into the inverter is taken as the positive direction, the preset common-mode damping coefficient is positive; superimposing the virtual damping voltage on the common-mode injection voltage of each inverter to obtain a target common-mode voltage for each inverter; and controlling the operation of each inverter based on the target common-mode voltage and the differential-mode voltage of each inverter. Based on this solution, since the direction of the common-mode current of different inverters differs when circulating current occurs in a parallel inverter system, if the direction of current outflow from the inverter is predefined as positive, a virtual damping voltage can be superimposed on the common-mode injection voltage of each inverter. This reduces the effective value of the common-mode voltage difference between inverters, thereby reducing the common-mode circulating current and effectively suppressing it in the parallel inverter system. Furthermore, compared to the existing method of suppressing circulating current through hardware wiring, this solution, by real-time detection of the inverter's circulating current magnitude and the superposition of a virtual damping voltage, suppresses circulating current without the need for additional hardware parallel cables, thus saving cable costs and offering better economic efficiency.

[0008] In conjunction with the first aspect, in one possible implementation, the aforementioned inverter parallel system includes: N inverter groups, where N is an integer greater than or equal to 2. Each inverter group includes a first inverter and a second inverter. The DC input terminal of the first inverter is connected to a first DC power supply, and the DC input terminal of the second inverter is connected to a second DC power supply. The negative terminal of the first DC power supply is connected to the positive terminal of the second DC power supply. The AC output terminals of the N first inverters in the aforementioned N inverter groups are used to connect to a first transformer, and the AC output terminals of the N second inverters in the aforementioned N inverter groups are used to connect to a second transformer. Optionally, this inverter parallel system can be referred to as a DC cascaded AC parallel system. Based on this solution, the circulating current suppression method provided in this application can be applied to this DC cascaded AC parallel system, which can reduce the circulating current in the DC cascaded AC parallel system and improve the reliability of the inverter components in the DC cascaded AC parallel system.

[0009] In conjunction with the first aspect and the above possible implementations, in another possible implementation, the negative terminals of the N first DC power supplies in the N inverter groups are connected together. Based on this scheme, the inverter parallel system connects the negative terminals of the N first DC power supplies in the DC cascaded AC parallel system, thereby reducing the circulating current in the inverter parallel system and improving the reliability of the inverter components in the inverter parallel system through the above circulating current suppression method.

[0010] Combining the first aspect and the aforementioned possible implementations, in another possible implementation, the inverter parallel system includes: N inverters, where N is an integer greater than or equal to 2; the AC output terminals of the N inverters are connected to each other, and the AC output terminals of the N inverters are used to connect to a transformer; the DC input terminals of the N inverters are respectively connected to N DC power supplies, and the positive terminals of the N DC power supplies are connected to each other. Optionally, this inverter parallel system can be called a common DC positive AC parallel system. Based on this scheme, the aforementioned circulating current suppression method can be applied to the common DC positive AC parallel system, which can reduce the circulating current in the common DC positive AC parallel system and improve the reliability of the inverter components in the common DC positive AC parallel system.

[0011] Combining the first aspect and the aforementioned possible implementations, in another possible implementation, the inverter parallel system includes: N inverters, where N is an integer greater than or equal to 2; the AC output terminals of the N inverters are connected to each other, and the AC output terminals of the N inverters are used to connect to a transformer; the DC input terminals of the N inverters are respectively connected to N DC power supplies, and the negative terminals of the N DC power supplies are connected to each other. Optionally, this inverter parallel system can be called a common DC negative AC parallel system. Based on this scheme, the aforementioned circulating current suppression method can be applied to the common DC negative AC parallel system, which can reduce the circulating current in the common DC negative AC parallel system and improve the reliability of the inverter components in the common DC negative AC parallel system.

[0012] In conjunction with the first aspect and the aforementioned possible implementations, in another possible implementation, obtaining the common-mode injection voltage of each inverter includes: determining the common-mode injection voltage of each inverter based on its common-mode voltage injection method. Based on this scheme, the common-mode injection voltage of each inverter can be calculated according to its common-mode voltage injection method. By superimposing a virtual damping voltage on this common-mode injection voltage, the effective value of the common-mode voltage difference between inverters can be reduced, thereby reducing common-mode circulating current and effectively suppressing circulating current in the inverter parallel system. Optionally, the common-mode voltage injection method includes sinusoidal pulse width modulation (SPWM), voltage space vector pulse width modulation (SVPWM), or discontinuous pulse width modulation (DPWM). Optionally, the common-mode voltage injection method of all inverters in the inverter parallel system can be the same.

[0013] Optionally, if the direction of current outflow from the inverter is taken as the positive direction, the above-mentioned preset common-mode damping coefficient can be -1.5 ohms; if the direction of current inflow from the inverter is taken as the positive direction, the above-mentioned preset common-mode damping coefficient can be 1.5 ohms.

[0014] Combining the first aspect and the above possible implementations, in another possible implementation, the target common-mode voltage is obtained by the following formula: U cmv =U cmv0 +U vir ;U vir =i cmv R vir Among them, U cmv For the target common-mode voltage mentioned above, U cmv0 For the aforementioned common-mode injection voltage, U vir For the aforementioned virtual damping voltage, R vir For the aforementioned preset common-mode damping coefficient, i cmv The above refers to the common-mode current. Based on this scheme, by superimposing a virtual damping voltage on the common-mode injection voltage of each inverter, the effective value of the common-mode voltage difference between inverters can be reduced, thereby reducing the common-mode circulating current and effectively suppressing the circulating current in the inverter parallel system.

[0015] Combining the first aspect and the above possible implementations, in another possible implementation, the above common-mode current can be obtained by the following formula: i cmv =(i a +i b +i c ) / 3; where i a i b i c These are the three-phase output currents of the inverter, i cmvThe common-mode current is as described above. Based on this scheme, the common-mode current of the inverter can be calculated from the three-phase output current of the inverter. Then, combined with the common-mode current of the inverter, a virtual damping voltage superimposed on the common-mode injection voltage of each inverter can be determined. After superimposing this virtual damping voltage on the common-mode injection voltage, the effective value of the common-mode voltage difference between inverters can be reduced, thereby reducing the common-mode circulating current and effectively suppressing the circulating current in the inverter parallel system.

[0016] Combining the first aspect and the aforementioned possible implementations, in another possible implementation, controlling the operation of each inverter based on the target common-mode voltage and the differential-mode voltage of each inverter includes: superimposing the target common-mode voltage and the differential-mode voltage of each inverter to obtain the modulation voltage of each inverter; and using the modulation voltage of each inverter as the drive signal for the switching element of each inverter to control the operation of each inverter. Based on this scheme, by superimposing a virtual damping voltage on the common-mode injection voltage of each inverter to obtain the target common-mode voltage, and controlling the operation of the inverters based on the target common-mode voltage and the differential-mode voltage, the effective value of the common-mode voltage difference between inverters can be reduced, thereby reducing the common-mode circulating current and effectively suppressing the circulating current in the inverter parallel system.

[0017] A second aspect of this application provides a circulating current suppression device in a parallel inverter system. The device includes: a processor configured to acquire the common-mode current and common-mode injection voltage of each inverter in the parallel inverter system; the processor is further configured to determine a virtual damping voltage for each inverter based on the common-mode current of each inverter and a preset common-mode damping coefficient; wherein the preset common-mode damping coefficient is negative if the direction of current outflow from the inverter is considered positive, and positive if the direction of current inflow into the inverter is considered positive; the processor is further configured to superimpose the virtual damping voltage onto the common-mode injection voltage of each inverter to obtain a target common-mode voltage for each inverter; and the processor is further configured to control the operation of each inverter via a controller based on the target common-mode voltage and differential-mode voltage of each inverter obtained by the processor.

[0018] In conjunction with the second aspect, in one possible implementation, the aforementioned inverter parallel system includes: N inverter groups, where N is an integer greater than or equal to 2; each inverter group includes a first inverter and a second inverter; the DC input terminal of the first inverter is connected to a first DC power supply, and the DC input terminal of the second inverter is connected to a second DC power supply; the negative terminal of the first DC power supply is connected to the positive terminal of the second DC power supply; the AC output terminals of the N first inverters in the aforementioned N inverter groups are used to connect to a first transformer, and the AC output terminals of the N second inverters in the aforementioned N inverter groups are used to connect to a second transformer.

[0019] In combination with the second aspect and the above possible implementations, in another possible implementation, the negative terminals of the N first DC power supplies in the N inverter groups are connected together.

[0020] In conjunction with the second aspect and the above possible implementations, in another possible implementation, the inverter parallel system includes: N inverters, where N is an integer greater than or equal to 2; the AC output terminals of the N inverters are connected to each other, and the AC output terminals of the N inverters are used to connect to a transformer; the DC input terminals of the N inverters are respectively connected to N DC power supplies, and the positive terminals of the N DC power supplies are connected to each other. In conjunction with the second aspect and the above possible implementations, in another possible implementation, the inverter parallel system includes: N inverters, where N is an integer greater than or equal to 2; the AC output terminals of the N inverters are connected to each other, and the AC output terminals of the N inverters are used to connect to a transformer; the DC input terminals of the N inverters are respectively connected to N DC power supplies, and the negative terminals of the N DC power supplies are connected to each other.

[0021] In combination with the second aspect and the above possible implementations, in another possible implementation, the processor is specifically used to: determine the common-mode injection voltage of each inverter based on the common-mode voltage injection method of each inverter.

[0022] In combination with the second aspect and the above possible implementations, in another possible implementation, the above common-mode voltage injection method includes sinusoidal pulse width modulation (SPWM), voltage space vector pulse width modulation (SVPWM), or discontinuous pulse width modulation (DPWM).

[0023] Combining the second aspect and the above possible implementations, in another possible implementation, the target common-mode voltage is obtained by the following formula: U cmv =U cmv0 +U vir ;U vir =i cmv R vir Among them, U cmv For the target common-mode voltage mentioned above, U cmv0 For the aforementioned common-mode injection voltage, U vir For the aforementioned virtual damping voltage, R vir For the aforementioned preset common-mode damping coefficient, i cmv This refers to the common-mode current mentioned above.

[0024] Combining the second aspect and the above possible implementations, in another possible implementation, the aforementioned common-mode current can be obtained by the following formula: i cmv =(i a +i b +i c) / 3; where i a i b i c These are the three-phase output currents of the inverter, i cmv This refers to the common-mode current mentioned above.

[0025] In conjunction with the second aspect and the above possible implementations, in another possible implementation, the processor is further configured to superimpose the target common-mode voltage of each inverter with the differential-mode voltage of each inverter to obtain the modulation voltage of each inverter; the controller is specifically configured to use the modulation voltage of each inverter obtained by the processor as the drive signal of the switching element of each inverter to control the operation of each inverter.

[0026] A third aspect of this application provides a power supply system including an inverter parallel system and a circulating current suppression device in the inverter parallel system as described in any of the second aspects above, the circulating current suppression device in the inverter parallel system being used to suppress circulating current in the inverter parallel system. Attached Figure Description

[0027] Figure 1 A schematic diagram of a circulating current generated in a parallel inverter system provided in this application embodiment;

[0028] Figure 2 A schematic diagram of a structure for suppressing circulating current in a parallel inverter system provided in this application embodiment;

[0029] Figure 3a A schematic diagram of a parallel inverter system provided in this application embodiment;

[0030] Figure 3b A schematic diagram of another inverter parallel system provided in this application embodiment;

[0031] Figure 4a A schematic diagram of another inverter parallel system provided in this application embodiment;

[0032] Figure 4b A schematic diagram of another inverter parallel system provided in this application embodiment;

[0033] Figure 5 A schematic diagram of another inverter parallel system provided in this application embodiment;

[0034] Figure 6 A schematic diagram of another inverter parallel system provided in this application embodiment;

[0035] Figure 7 A schematic diagram of a large-scale photovoltaic power plant collection system provided in this application embodiment;

[0036] Figure 8 A schematic flowchart of a circulation suppression method provided in an embodiment of this application;

[0037] Figure 9 This is a schematic diagram illustrating the application of a circulation suppression method provided in an embodiment of this application;

[0038] Figure 10 This is a schematic diagram illustrating the application of another circulation suppression method provided in the embodiments of this application;

[0039] Figure 11 This is a schematic diagram comparing the suppression effect of a circulation suppression method provided in an embodiment of this application;

[0040] Figure 12 This is a schematic diagram of the composition of a circulation suppression device provided in an embodiment of this application. Detailed Implementation

[0041] The technical solutions in the embodiments of this application will be described below with reference to the accompanying drawings. In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, or B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the related objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, a and b, a and c, b and c, or a and b and c, where a, b, and c can be single or multiple. Furthermore, to facilitate a clear description of the technical solutions in the embodiments of this application, the terms "first" and "second" are used in the embodiments of this application to distinguish identical or similar items with essentially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order. For example, "first" in the first inverter and "second" in the second inverter in the embodiments of this application are only used to distinguish different inverters. The descriptions of "first" and "second" appearing in the embodiments of this application are only for illustration and to distinguish the described objects, and have no order, nor do they indicate a special limitation on the number of devices in the embodiments of this application, and cannot constitute any limitation on the embodiments of this application.

[0042] It should be noted that, in this application, the terms "exemplary" or "for example" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0043] For example, Figure 1 This is an inverter parallel system comprising four inverters: inverter 1, inverter 2, inverter 3, and inverter 4. For example... Figure 1 As shown, the DC input terminals of inverters 1, 2, 3, and 4 are connected to DC1 through DC4 respectively. Inverters 1 through 4 are used to convert the connected DC power into AC power. The negative terminal of DC1 is connected to the positive terminal of DC2, and the negative terminal of DC3 is connected to the positive terminal of DC4. Optionally, inverters 1 and 3 can be referred to as positive inverters, and inverters 2 and 4 can be referred to as negative inverters.

[0044] like Figure 1 As shown, the AC output terminals of inverter 1 and inverter 3 are connected to each other, and the AC output terminals of inverter 1 and inverter 3 are used to connect to one winding of the three-winding transformer. The AC output terminals of inverter 2 and inverter 4 are connected to each other, and the AC output terminals of inverter 2 and inverter 4 are used to connect to the other winding of the three-winding transformer.

[0045] Optionally, the AC output terminals of inverters 1 and 3, and the AC output terminals of inverters 2 and 4, are respectively used to connect to two different windings. These two different windings can be two different windings of the same transformer, or windings of different transformers. For example, the AC output terminals of inverters 1 and 3 can be connected to a two-winding transformer, and the AC output terminals of inverters 2 and 4 can be connected to another two-winding transformer. Figure 1 The illustration only takes the AC output terminals of inverter 1 and inverter 3 as an example, which are connected to different windings of the same transformer as the AC output terminals of inverter 2 and inverter 4.

[0046] If the sum of the DC bus voltages of inverter 1 and inverter 2 differs from the sum of the DC bus voltages of inverter 3 and inverter 4, then a circulating current will form between inverters 1, 2, 3, and 4. Figure 1As shown, the circulating current flows from the AC output terminal of inverter 1 to the AC output terminal of inverter 3, then through inverter 3, from the DC input terminal of inverter 3 to the DC input terminal of inverter 4, then through inverter 4, from the AC output terminal of inverter 4 to the AC output terminal of inverter 2, then through inverter 2, and finally back from the DC input terminal of inverter 2 to the DC input terminal of inverter 1, thus forming a circulating current. It is understood that the embodiments of this application do not limit the direction of the circulating current in the inverter parallel system. Figure 1 The circulating current direction in the inverter parallel system shown can also be excluding Figure 1 Other directions besides the indicated circulation direction, Figure 1 This is merely an illustrative example.

[0047] The circulating current formed by the parallel inverter system mentioned above will affect the inverter efficiency and is prone to triggering overcurrent protection, resulting in low reliability of inverter components.

[0048] To suppress circulating current in a parallel inverter system, Figure 2 A scheme for suppressing circulating current in a parallel inverter system is provided. For example... Figure 2 As shown, this scheme connects the positive terminal of DC1 to the positive terminal of DC3, and the negative terminal of DC2 to the negative terminal of DC4. This ensures that the sum of the DC bus voltages of inverter 1 and inverter 2 is consistent with the sum of the DC bus voltages of inverter 3 and inverter 4, thus suppressing circulating current in the parallel inverter system. However, this scheme, by using hardware wiring to connect the positive and negative terminals of the common DC bus, requires additional DC parallel cables, resulting in a large initial investment and poor economic efficiency.

[0049] Another approach to suppress circulating current in parallel inverter systems involves detecting the DC bus voltages of different inverters and adjusting these voltages accordingly to ensure uniformity. However, this approach is an open-loop control, and even slight differences in the detected DC bus voltages of different inverters can still lead to significant circulating currents.

[0050] In order to suppress circulating current in a parallel inverter system while improving economic efficiency, this application provides a circulating current suppression method. This method can suppress circulating current in a parallel inverter system without adding hardware wiring, which not only improves the reliability of inverter components but also enhances economic benefits.

[0051] The circulating current suppression method provided in this application is applied to a parallel inverter system. This parallel inverter system includes N inverter groups, where N is an integer greater than or equal to 2. Each inverter group includes a first inverter and a second inverter. The DC input terminal of the first inverter is connected to a first DC power supply, and the DC input terminal of the second inverter is connected to a second DC power supply. The negative terminal of the first DC power supply is connected to the positive terminal of the second DC power supply. The AC output terminals of the N first inverters in the N inverter groups are connected to each other and are used to connect to a first transformer. Similarly, the AC output terminals of the N second inverters in the N inverter groups are connected to each other and are used to connect to a second transformer.

[0052] Optionally, the first transformer and the second transformer can be different transformers or the same transformer. When the first transformer and the second transformer are the same transformer, the AC output terminals of the N first inverters and the AC output terminals of the N second inverters are respectively used to connect to different windings of the transformer. For example, the AC output terminals of the N first inverters are used to connect to one winding of the three-winding transformer, and the AC output terminals of the N second inverters are used to connect to the other winding of the three-winding transformer.

[0053] As is understandable, the AC output terminals of the aforementioned N first inverters and the AC output terminals of the N second inverters are respectively used to connect two different windings. These two different windings can be different windings of the same transformer, or windings of different transformers. The following embodiment is only used as an example where the two different windings are different windings of the same transformer.

[0054] For example, taking the above-mentioned inverter parallel system as an example, which includes two inverter groups, such as... Figure 3a As shown, the inverter parallel system includes a first inverter group and a second inverter group. The first inverter group includes inverter 1 and inverter 2, and the second inverter group includes inverter 3 and inverter 4. The DC input terminal of inverter 1 is connected to DC1, the DC input terminal of inverter 2 is connected to DC2, and the negative terminal of DC1 is connected to the positive terminal of DC2. The DC input terminal of inverter 3 is connected to DC3, and the DC input terminal of inverter 4 is connected to DC4, with the negative terminal of DC3 connected to the positive terminal of DC4. The AC output terminal of inverter 1 is connected to the AC output terminal of inverter 3, and the AC output terminals of inverter 1 and inverter 3 are used to connect to one winding of a three-winding transformer. The AC output terminal of inverter 2 is connected to the AC output terminal of inverter 4, and the AC output terminals of inverter 2 and inverter 4 are used to connect to the other winding of the three-winding transformer.

[0055] For example, taking the above-mentioned inverter parallel system as an example, which includes three inverter groups, such as... Figure 3bAs shown, the inverter parallel system includes a first inverter group, a second inverter group, and a third inverter group. The first inverter group includes inverter 1 and inverter 2; the second inverter group includes inverter 3 and inverter 4; and the third inverter group includes inverter 5 and inverter 6. The DC input terminal of inverter 1 is connected to DC1; the DC input terminal of inverter 2 is connected to DC2; and the negative terminal of DC1 is connected to the positive terminal of DC2. The DC input terminal of inverter 3 is connected to DC3; the DC input terminal of inverter 4 is connected to DC4; and the negative terminal of DC3 is connected to the positive terminal of DC4. The DC input terminal of inverter 5 is connected to DC5; and the DC input terminal of inverter 6 is connected to DC6; and the negative terminal of DC5 is connected to the positive terminal of DC6. The AC output terminals of inverter 1, inverter 3, and inverter 5 are connected together, and the AC output terminals of inverter 1, inverter 3, and inverter 5 are connected to one winding of a three-winding transformer. The AC output terminals of inverter 2, inverter 4, and inverter 6 are connected together, and the AC output terminals of inverter 2, inverter 4, and inverter 6 are connected to the other winding of a three-winding transformer.

[0056] Optionally, the circulating current suppression method provided in this application embodiment can also be applied to another inverter parallel system, which includes: N inverter groups, where N is an integer greater than or equal to 2. Each inverter group includes a first inverter and a second inverter. The DC input terminal of the first inverter is used to connect to a first DC power supply, and the DC input terminal of the second inverter is used to connect to a second DC power supply. The negative terminal of the first DC power supply is connected to the positive terminal of the second DC power supply. The AC output terminals of the N first inverters in the N inverter groups are connected to each other, and the AC output terminals of the N first inverters are used to connect to a first transformer. The AC output terminals of the N second inverters in the N inverter groups are connected to each other, and the AC output terminals of the N second inverters are used to connect to a second transformer. The negative terminals of the N first DC power supplies in the N inverter groups are connected to each other. It is understood that the difference between this inverter parallel system and the aforementioned inverter parallel system is that the negative terminals of the N first DC power supplies in the N inverter groups in the aforementioned inverter parallel system are connected to each other. That is, connecting the neutral lines between different inverter groups.

[0057] For example, taking the above-mentioned inverter parallel system as an example, which includes two inverter groups, such as... Figure 4aAs shown, the inverter parallel system includes a first inverter group and a second inverter group. The first inverter group includes inverter 1 and inverter 2, and the second inverter group includes inverter 3 and inverter 4. The DC input terminal of inverter 1 is connected to DC1, the DC input terminal of inverter 2 is connected to DC2, and the negative terminal of DC1 is connected to the positive terminal of DC2 and the negative terminal of DC3. The DC input terminal of inverter 3 is connected to DC3, and the DC input terminal of inverter 4 is connected to DC4, with the negative terminal of DC3 connected to the positive terminal of DC4. The AC output terminal of inverter 1 is connected to the AC output terminal of inverter 3, and the AC output terminals of inverter 1 and inverter 3 are used to connect to one winding of a three-winding transformer. The AC output terminal of inverter 2 is connected to the AC output terminal of inverter 4, and the AC output terminals of inverter 2 and inverter 4 are used to connect to the other winding of the three-winding transformer.

[0058] For example, taking the above-mentioned inverter parallel system as an example, which includes three inverter groups, such as... Figure 4b As shown, the inverter parallel system includes a first inverter group, a second inverter group, and a third inverter group. The first inverter group includes inverter 1 and inverter 2; the second inverter group includes inverter 3 and inverter 4; and the third inverter group includes inverter 5 and inverter 6. The DC input terminal of inverter 1 is connected to DC1; the DC input terminal of inverter 2 is connected to DC2; the negative terminal of DC1 is connected to the positive terminal of DC2, the negative terminal of DC3, and the negative terminal of DC5. The DC input terminal of inverter 3 is connected to DC3; the DC input terminal of inverter 4 is connected to DC4; the negative terminal of DC3 is connected to the positive terminal of DC4. The DC input terminal of inverter 5 is connected to DC5; the DC input terminal of inverter 6 is connected to DC6; and the negative terminal of DC5 is connected to the positive terminal of DC6. The AC output terminals of inverter 1, inverter 3, and inverter 5 are connected together, and the AC output terminals of inverter 1, inverter 3, and inverter 5 are connected to one winding of a three-winding transformer. The AC output terminals of inverter 2, inverter 4, and inverter 6 are connected together, and the AC output terminals of inverter 2, inverter 4, and inverter 6 are connected to the other winding of a three-winding transformer.

[0059] Understandably, the above Figure 4a and Figure 3a The difference in the parallel inverter system shown is that the negative terminals of DC1 and DC3 are connected together. (The above...) Figure 4b and Figure 3b The difference in the parallel inverter system shown is that the negative terminals of DC1, DC3, and DC5 are connected together.

[0060] It is understood that the inverter parallel system to which the circulating current suppression method provided in this application is applied may also include four or more inverter groups, and this application is not limited thereto. Figure 3a , Figure 3b , Figure 4a and Figure 4b The illustration will only take the inverter parallel system, which includes two inverter groups or three inverter groups, as an example.

[0061] The circulating current suppression method provided in this application embodiment can also be applied to another inverter parallel system, which includes: N inverters, where N is an integer greater than or equal to 2, the AC output terminals of the N inverters are connected to each other, and the AC output terminals of the N inverters are used to connect to a transformer. The DC input terminals of the N inverters are respectively connected to N DC power supplies, and the positive terminals of the N DC power supplies are connected to each other, or the negative terminals of the N DC power supplies are connected to each other.

[0062] For example, such as Figure 5 The diagram illustrates a parallel inverter system comprising two inverters, inverter 1 and inverter 2. The AC output terminals of inverter 1 and inverter 2 are connected, and their AC output terminals are used to connect a transformer. The DC input terminal of inverter 1 is connected to DC1, and the DC input terminal of inverter 2 is connected to DC2. The positive terminal of DC1 is connected to the positive terminal of DC2. Optionally, this parallel inverter system can be referred to as a common DC positive AC parallel system.

[0063] For example, such as Figure 6 The diagram illustrates a parallel inverter system comprising two inverters, inverter 1 and inverter 2. The AC output terminals of inverter 1 and inverter 2 are connected, and their AC output terminals are used to connect a transformer. The DC input terminal of inverter 1 is connected to DC1, and the DC input terminal of inverter 2 is connected to DC2. The negative terminal of DC1 is connected to the negative terminal of DC2. Optionally, this parallel inverter system can be referred to as a common DC negative AC parallel system.

[0064] Understandable. Figure 5 and Figure 6 The example shown is based on a parallel inverter system with two inverters. In actual applications, a parallel inverter system may include three or more inverters. This application does not limit the specific number of inverters included in the parallel inverter system.

[0065] It should be noted that the embodiments of this application do not limit the specific type and structure of each inverter in the inverter parallel system. Figures 1 to 6The inverter structure shown in the parallel inverter system is merely an exemplary illustration. Figures 1 to 6 The inverter circuit in the inverter shown may include one or more switching elements. By controlling the on and off of the switching elements in the inverter circuit, the DC power input to the inverter can be converted into AC power.

[0066] Optionally, the above Figures 3a to 6 The inverter parallel system shown can be Figure 7 The inverter parallel system in the large photovoltaic power station collection system shown.

[0067] like Figure 7 As shown, the photovoltaic strings in this large-scale photovoltaic power station collection system can be composed of multiple photovoltaic panels connected in series and parallel. The photovoltaic strings are used to convert solar energy into electrical energy. The electrical energy generated by the photovoltaic strings is input into a maximum power point tracking (MPPT) boost converter box through DC cables for voltage boosting. The boosted DC power is then converted into AC power through a parallel inverter system. The AC power is transmitted to a transformer through AC cables. After the transformer adjusts the voltage, it is fed into the AC power grid through AC cables to realize the power generation function.

[0068] Optionally, the circulating current suppression method provided in the following embodiments of this application can be executed by a circulating current suppression device, which may include a processor and a controller.

[0069] This application provides a circulating current suppression method, such as... Figure 8 As shown, the method includes the following steps:

[0070] S801. Obtain the common-mode current and common-mode injection voltage of each inverter in the inverter parallel system.

[0071] Optionally, step S801 can be executed by the processor in the circulating current suppression device.

[0072] Optionally, the inverter parallel system in step S801 can be any of the inverter parallel systems described above. For example, the inverter parallel system in step S801 can be any of the above-mentioned inverter parallel systems. Figure 3a , Figure 3b , Figure 4a , Figure 4b , Figure 5 or Figure 6 Any of the inverters shown in parallel system.

[0073] For example, obtaining the common-mode current of each inverter in step S801 above may include: obtaining the three-phase output current of each inverter, and determining the common-mode current of each inverter based on the three-phase output current of each inverter. Optionally, the three-phase output current of each inverter can be detected by a sensor element. For example, the processor can receive the three-phase output current of the inverter detected by a Hall sensor. Optionally, the sensor element can detect the three-phase output current of each inverter in real time.

[0074] Optionally, the common-mode current of each inverter can be obtained using the following formula:

[0075] i cmv =(i a +i b +i c ) / 3;

[0076] Among them, i a i b i c i represents the three-phase output current of each inverter. cmv This refers to the common-mode current for each inverter.

[0077] It should be noted that during the operation of a parallel inverter system, the direction of the common-mode current of each inverter may change. For example, at time T1, the direction of the common-mode current of inverter 1 may be out of the inverter, while at time T2, the direction of the common-mode current of inverter 1 may be in the inverter.

[0078] Optionally, if the direction of current outflow from the inverter is predefined as the positive direction, then the common-mode current of inverter 1 at time T1 is positive and the common-mode current of inverter 1 at time T2 is negative. If the direction of current inflow into the inverter is predefined as the positive direction, then the common-mode current of inverter 1 at time T1 is negative and the common-mode current of inverter 1 at time T2 is positive.

[0079] For example, such as Figure 9 As shown, with the circulation path as Figure 9 Taking the circulating current path indicated by the middle arrow as an example. If the positive direction of the current is predetermined as the direction in which the current flows out of the inverter, then... Figure 9 The common-mode current of inverter 1 is positive, the common-mode current of inverter 2 is negative, the common-mode current of inverter 3 is negative, and the common-mode current of inverter 4 is positive.

[0080] For example, such as Figure 9 As shown, with the circulation path as Figure 9 Taking the circulating current path indicated by the middle arrow as an example. If the positive direction of the current is predetermined as the direction in which the current flows into the inverter, then... Figure 9The common-mode current of inverter 1 is negative, the common-mode current of inverter 2 is positive, the common-mode current of inverter 3 is positive, and the common-mode current of inverter 4 is negative.

[0081] Optionally, obtaining the common-mode injection voltage of each inverter in step S801 above may include: determining the common-mode injection voltage of each inverter based on the common-mode voltage injection method of each inverter. This common-mode injection voltage can be represented by U... cmv0 express.

[0082] For example, common-mode voltage injection methods include sine pulse width modulation (SPWM), space vector pulse width modulation (SVPWM), or discontinuity pulse width modulation (DPWM). It is understood that the specific method for determining the common-mode injection voltage of each inverter, based on its common-mode voltage injection method, can refer to existing technologies and will not be elaborated here. For example, it can be based on the differential-mode voltage u of each inverter. a u b u c And the common-mode voltage injection method of the inverter, calculate the common-mode injection voltage U of the inverter. cmv0 .

[0083] Optionally, the common-mode voltage injection method of all inverters in the inverter parallel system of this application embodiment can be the same.

[0084] S802. Based on the common-mode current and preset common-mode damping coefficient of each inverter, determine the virtual damping voltage of each inverter.

[0085] Optionally, step S802 can be executed by a processor in the circulating current suppression device.

[0086] If the direction of current outflow from the inverter is predefined as positive, then the common-mode damping coefficient is preset to a negative value. If the direction of current inflow from the inverter is predefined as positive, then the common-mode damping coefficient is preset to a positive value.

[0087] For example, such as Figure 9 The inverter parallel system shown has the circulating current path as... Figure 9 Taking the circulating current path indicated by the middle arrow as an example, the circulating current suppression method provided in this application embodiment can add virtual damping to each inverter. The preset common-mode damping coefficient corresponding to this virtual damping is R. vir .like Figure 9 As shown, if the positive direction of the current is predetermined as the direction in which the current flows out of the inverter, then Figure 9 The preset common-mode damping coefficient R in vir All are negative values. If the positive direction of the current is predetermined as the direction in which the current flows into the inverter, then Figure 9 The preset common-mode damping coefficient R in vir It is a positive value. This is understandable, such as... Figure 9 As shown, in this embodiment of the application, a virtual damper can be added to each inverter in the inverter parallel system, and the resistance value corresponding to the virtual damper can be a preset common-mode damping coefficient.

[0088] Optionally, in a parallel inverter system, the preset common-mode damping coefficients corresponding to the virtual damping added to all inverters are the same. If the positive direction of the current is predefined as the direction of current outflow from the inverter, then the preset common-mode damping coefficients corresponding to the virtual damping added to all inverters in the parallel inverter system are all negative. If the positive direction of the current is predefined as the direction of current inflow into the inverter, then the preset common-mode damping coefficients corresponding to the virtual damping added to all inverters in the parallel inverter system are all positive.

[0089] For example, if the direction of current outflow from the inverter is taken as the positive direction, the preset common-mode damping coefficient is -1.5 ohms. If the direction of current inflow into the inverter is taken as the positive direction, the preset common-mode damping coefficient is 1.5 ohms. This application does not limit the specific value of the preset common-mode damping coefficient; here, only the values ​​of -1.5 ohms or 1.5 ohms are used as examples for illustration. It should be noted that a larger preset common-mode damping coefficient results in better suppression of circulating current; however, a larger preset common-mode damping coefficient may cause overmodulation, leading to worse harmonics and potentially failing to meet grid requirements. Therefore, in practical applications, the value of the preset common-mode damping coefficient must consider both the effect of suppressing circulating current and avoiding overmodulation.

[0090] For example, such as Figure 9 As shown, if the direction of current flow out of the inverter is predetermined as the positive direction, then Figure 9 The preset common-mode damping coefficient R in vir Both are -1.5 ohms. If the direction of current flow into the inverter is predefined as the positive direction, then... Figure 9 The preset common-mode damping coefficient R in vir It is 1.5 ohms.

[0091] Optionally, the virtual damping voltage is obtained using the following formula:

[0092] U vir =i cmv R vir ;

[0093] Among them, U vir R is the virtual damping voltage.vir To preset the common-mode damping coefficient, i cmv This is the common-mode current of the inverter.

[0094] S803. A virtual damping voltage is superimposed on the common-mode injection voltage of each inverter to obtain the target common-mode voltage of each inverter.

[0095] Optionally, step S803 can be executed by the processor in the circulating current suppression device.

[0096] Optionally, the target common-mode voltage for each of the above inverters can be obtained using the following formula:

[0097] U cmv =U cmv0 +U vir ;

[0098] Among them, U cmv The target common-mode voltage for each inverter, U cmv0 The common-mode injection voltage for each inverter, U vir The virtual damping voltage for each inverter.

[0099] For example, such as Figure 10 As shown, based on the three-phase output current i of each inverter a i b i c Calculate the common-mode current i cmv And based on the common-mode current i cmv and the preset common-mode damping coefficient R vir Obtain the virtual damping voltage U vir And the virtual damping voltage U vir Superimposed on the common-mode injection voltage U cmv0 The target common-mode voltage U is obtained. cmv .

[0100] Understandably, the method for calculating the target common-mode voltage is the same for each inverter in a parallel inverter system. Since the direction of the common-mode current differs between inverters when circulating current occurs in a parallel inverter system, if the direction of current outflow from the inverter is predefined as positive, the preset common-mode damping coefficient can be set to a negative value; if the direction of current inflow into the inverter is predefined as positive, the preset common-mode damping coefficient can be set to a positive value. This allows a virtual damping voltage to be superimposed on the common-mode injection voltage of each inverter, reducing the effective value of the common-mode voltage difference between inverters, thereby reducing common-mode circulating current and effectively suppressing circulating current in the parallel inverter system.

[0101] For example, taking the circulation path as Figure 9The circulating current path indicated by the middle arrow is used as an example, where the positive direction of the current is predefined as the direction in which the current flows out of the inverter. For instance... Figure 9 As shown, for inverter 1, since the preset common-mode damping coefficient is negative, the direction of the common-mode current in inverter 1 is the direction of outflow from the inverter (the common-mode current of inverter 1 is positive), therefore, the virtual damping voltage value of inverter 1 is negative. The virtual damping voltage is superimposed on the common-mode injection voltage of inverter 1 to obtain the target common-mode voltage of inverter 1. The effective value of this target common-mode voltage of inverter 1 is smaller than the effective value of the common-mode injection voltage of inverter 1. For inverter 2, since the preset common-mode damping coefficient is negative, the direction of the common-mode current in inverter 2 is the direction of inflow into the inverter (the common-mode current of inverter 2 is negative), therefore, the virtual damping voltage value of inverter 2 is positive. The virtual damping voltage is superimposed on the common-mode injection voltage of inverter 2 to obtain the target common-mode voltage of inverter 2. The effective value of this target common-mode voltage of inverter 2 is larger than the effective value of the common-mode injection voltage of inverter 2. After adopting the circulating current suppression method, the effective value of the common-mode voltage of inverter 1 decreases, while the effective value of the common-mode voltage of inverter 2 increases. Therefore, the effective value of the common-mode voltage difference between inverter 1 and inverter 2 after adopting the circulating current suppression method is smaller than the effective value of the common-mode voltage difference between inverter 1 and inverter 2 before adopting the circulating current suppression method. Thus, the circulating current in the inverter parallel system can be effectively suppressed.

[0102] S804 controls the operation of each inverter based on the target common-mode voltage and the differential-mode voltage of each inverter.

[0103] Optionally, step S804 can be performed by the controller in the circulating current suppression device.

[0104] For example, step S804 may include: superimposing the target common-mode voltage of each inverter with the differential-mode voltage of each inverter to obtain the modulation voltage of each inverter. The modulation voltage of each inverter is then used as a drive signal for the switching elements of each inverter to control the operation of each inverter. For instance, the target common-mode voltage of the inverter can be superimposed with the differential-mode voltage, and the superimposed modulation voltage can be used as a drive signal to control the operation of the switching elements in the inverter circuit of the inverter. Figures 1 to 6 and Figure 9 The structure of the switching elements in each inverter is not shown in the parallel inverter system shown.

[0105] It is understood that the circulating current suppression method provided in this application embodiment reduces the effective value of the common-mode voltage difference between inverters by superimposing a virtual damping voltage on the common-mode injection voltage of each inverter in the inverter parallel system, thereby effectively suppressing the circulating current in the inverter parallel system.

[0106] For example, Figure 11This is a comparison diagram showing the effect of circulating current suppression before and after using the circulating current suppression method of this application. For example... Figure 11 As shown in (a) of this application, before adopting the circulating current suppression method provided in this embodiment, the effective value of the circulating current in the inverter parallel system is relatively large. Figure 11 As shown in (b) of this application, the effective value of the circulating current in the inverter parallel system is smaller after adopting the circulating current suppression method provided in this application embodiment. Clearly, after adopting the circulating current suppression method provided in this application embodiment, the effective value of the circulating current in the inverter parallel system is significantly lower than the effective value of the circulating current before adopting the method of this embodiment. Therefore, the circulating current suppression method provided in this application can effectively suppress the circulating current in the inverter parallel system. Moreover, compared with the prior art of suppressing circulating current through hardware wiring, the method of this application embodiment, by real-time detection of the circulating current magnitude of the inverter and superimposing a virtual damping voltage, can suppress the circulating current without adding hardware parallel cables, thus saving cable costs and achieving better economic efficiency.

[0107] The circulating current suppression method provided in this application reduces the effective value of the common-mode voltage difference between inverters by superimposing a virtual damping voltage on the common-mode injection voltage of each inverter in a parallel inverter system. This effectively suppresses circulating current in the parallel inverter system and improves the reliability of inverter components. Furthermore, compared to existing technologies that suppress circulating current through hardware wiring, this method eliminates the need for additional hardware parallel cables, thus saving cable costs and offering better economic efficiency.

[0108] The foregoing mainly describes the solutions provided by the embodiments of this application from the perspective of method steps. It is understood that, in order to implement the above functions, a computer includes corresponding hardware structures and / or software modules for executing each function. Those skilled in the art should readily recognize that, in conjunction with the modules and algorithm steps of the various examples described in the embodiments disclosed herein, this application can be implemented in a combination of hardware and computer software. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0109] This application embodiment can divide the computer into functional modules according to the above method example. For example, each function can be divided into its own functional modules, or two or more functions can be integrated into one processing module. The integrated module can be implemented in hardware or as a software functional module. It should be noted that the module division in this application embodiment is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods.

[0110] Figure 12A possible structural schematic diagram of the circulating current suppression device involved in the above embodiments is shown. The circulating current suppression device 1200 includes a processing unit 1201 and a control unit 1202. Optionally, if the circulating current suppression device 1200 includes a storage unit, the processing unit 1201 can also execute programs or instructions stored in the memory to enable the circulating current suppression device 1200 to implement the methods and functions involved in any of the above embodiments.

[0111] For example, the processing unit 1201 can be used to support the execution of the circulating current suppression device 1200. Figure 8 S801-S803, and / or other processes used in the technology described herein. Control unit 1202 can be used to support the execution of the circulating current suppression device 1200. Figure 8 S804 in the above method embodiments, and / or other processes used in the technology described herein. All relevant content regarding each step in the above method embodiments can be referenced to the functional description of the corresponding functional module, and will not be repeated here.

[0112] Optionally, the circulating current suppression device 1200 may further include a transceiver unit, through which the processing unit 1201 can acquire the output current of each inverter in the inverter parallel system in real time. Optionally, the function of the transceiver unit may be performed by a transceiver or a communication interface.

[0113] For example, in hardware implementation, the functions of processing unit 1201 can be executed by one or more processors, and the functions of control unit 1202 can be executed by a controller. The processing unit 1201 can be embedded in or independent of the processor of the circulating current suppression device 1200 in hardware form, or it can be stored in the memory of the circulating current suppression device 1200 in software form, so that the processor can call and execute the operations corresponding to the above-mentioned functional units. Optionally, the processor executing the functions of processing unit 1201 and the controller executing the functions of control unit 1202 can be integrated into a single chip.

[0114] This application embodiment also provides a power supply system, which includes a circulating current suppression device, and as follows: Figure 3a , Figure 3b , Figure 4a , Figure 4b , Figure 5 or Figure 6 In any of the inverter parallel systems shown, the circulating current suppression device is used to employ... Figure 8 The circulating current suppression method shown suppresses circulating current in a parallel inverter system.

[0115] This application also provides an apparatus, which exists in the form of at least one chip, such as a chipset. The apparatus includes a processor and interface circuitry, and the processor can communicate with other devices through the interface circuitry. Optionally, the apparatus may further include a memory coupled to the processor to store necessary program instructions and data. The processor executes the program instructions stored in the memory, causing the apparatus to perform... Figure 8 The circulating current suppression method is shown. Optionally, the memory can be a storage module within the chip, such as a register or cache. The storage module can also be a storage module located outside the chip, such as a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, such as random access memory (RAM).

[0116] The steps of the methods or algorithms described in this application can be implemented in hardware or by a processor executing software instructions. The software instructions can consist of corresponding software modules, which can be stored in random access memory (RAM), flash memory, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, portable hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and storage medium can reside in an ASIC. Alternatively, the ASIC can reside in a core network interface device. Of course, the processor and storage medium can also exist as discrete components in the core network interface device.

[0117] Those skilled in the art will recognize that, in one or more of the examples above, the functions described in this invention can be implemented using hardware, software, firmware, or any combination thereof. When implemented in software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium accessible to a general-purpose or special-purpose computer.

[0118] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made on the basis of the technical solution of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for suppressing circulating current in a parallel inverter system, characterized in that, The method includes: Obtain the common-mode current and common-mode injection voltage of each inverter in the inverter parallel system; Based on the common-mode current of each inverter and the preset common-mode damping coefficient, the virtual damping voltage of each inverter is determined; wherein, if the direction of current outflow from the inverter is taken as the positive direction, the preset common-mode damping coefficient is negative; if the direction of current inflow from the inverter is taken as the positive direction, the preset common-mode damping coefficient is positive. The virtual damping voltage is superimposed on the common-mode injection voltage of each inverter to obtain the target common-mode voltage of each inverter; The operation of each inverter is controlled based on the target common-mode voltage and the differential-mode voltage of each inverter. The inverter parallel system includes: N inverter groups, where N is an integer greater than or equal to 2. Each inverter group includes a first inverter and a second inverter. The DC input terminal of the first inverter is connected to a first DC power supply, and the DC input terminal of the second inverter is connected to a second DC power supply. The negative terminal of the first DC power supply is connected to the positive terminal of the second DC power supply. The AC output terminals of the N first inverters in the N inverter groups are used to connect to a first transformer, and the AC output terminals of the N second inverters in the N inverter groups are used to connect to a second transformer.

2. The method according to claim 1, characterized in that, The negative terminals of the N first DC power supplies in the N inverter groups are connected together.

3. The method according to claim 1, characterized in that, The inverter parallel system includes: N inverters, where N is an integer greater than or equal to 2; the AC output terminals of the N inverters are connected to each other; the AC output terminals of the N inverters are used to connect to a transformer; the DC input terminals of the N inverters are respectively connected to N DC power supplies; and the positive terminals of the N DC power supplies are connected to each other.

4. The method according to claim 1, characterized in that, The inverter parallel system includes: N inverters, where N is an integer greater than or equal to 2; the AC output terminals of the N inverters are connected to each other; the AC output terminals of the N inverters are used to connect to a transformer; the DC input terminals of the N inverters are respectively connected to N DC power supplies; and the negative terminals of the N DC power supplies are connected to each other.

5. The method according to any one of claims 1-4, characterized in that, The process of obtaining the common-mode injection voltage of each inverter includes: The common-mode injection voltage of each inverter is determined based on the common-mode voltage injection method of each inverter.

6. The method according to claim 5, characterized in that, The common-mode voltage injection methods include sinusoidal pulse width modulation (SPWM), voltage space vector pulse width modulation (SVPWM), or discontinuous pulse width modulation (DPWM).

7. The method according to any one of claims 1-4, characterized in that, The target common-mode voltage is obtained by the following formula: U cmv = U cmv0 + U vir ； U vir = i cmv R vir ； in, U cmv The target common-mode voltage, U cmv0 For the common-mode injection voltage, U vir The virtual damping voltage is... R vir The preset common-mode damping coefficient is... i cmv The common-mode current is denoted as .

8. The method according to claim 7, characterized in that, The common-mode current is obtained by the following formula: i cmv =( i a + i b + i c ) / 3； in, i a , i b , i c These are the three-phase output currents of the inverter. i cmv The common-mode current is denoted as .

9. The method according to any one of claims 1-8, characterized in that, Based on the target common-mode voltage and the differential-mode voltage of each inverter, control the operation of each inverter, including: The target common-mode voltage of each inverter is superimposed with the differential-mode voltage of each inverter to obtain the modulation voltage of each inverter; The modulation voltage of each inverter is used as the drive signal for the switching element of each inverter to control the operation of each inverter.

10. A circulating current suppression device in a parallel inverter system, characterized in that, The device includes: The processor is used to acquire the common-mode current and common-mode injection voltage of each inverter in the inverter parallel system; The processor is further configured to determine the virtual damping voltage of each inverter based on the common-mode current of each inverter and a preset common-mode damping coefficient; wherein, if the direction of current outflow from the inverter is taken as the positive direction, the preset common-mode damping coefficient is negative; if the direction of current inflow from the inverter is taken as the positive direction, the preset common-mode damping coefficient is positive. The processor is also configured to superimpose the virtual damping voltage onto the common-mode injection voltage of each inverter to obtain the target common-mode voltage of each inverter; The processor is further configured to control the operation of each inverter via a controller based on the target common-mode voltage and differential-mode voltage of each inverter obtained by the processor. The inverter parallel system includes: N inverter groups, where N is an integer greater than or equal to 2. Each inverter group includes a first inverter and a second inverter. The DC input terminal of the first inverter is connected to a first DC power supply, and the DC input terminal of the second inverter is connected to a second DC power supply. The negative terminal of the first DC power supply is connected to the positive terminal of the second DC power supply. The AC output terminals of the N first inverters in the N inverter groups are used to connect to a first transformer, and the AC output terminals of the N second inverters in the N inverter groups are used to connect to a second transformer.

11. The apparatus according to claim 10, characterized in that, The negative terminals of the N first DC power supplies in the N inverter groups are connected together.

12. The apparatus according to claim 10, characterized in that, The inverter parallel system includes: N inverters, where N is an integer greater than or equal to 2; the AC output terminals of the N inverters are connected to each other; the AC output terminals of the N inverters are used to connect to a transformer; the DC input terminals of the N inverters are respectively connected to N DC power supplies; and the positive terminals of the N DC power supplies are connected to each other.

13. The apparatus according to claim 10, characterized in that, The inverter parallel system includes: N inverters, where N is an integer greater than or equal to 2; the AC output terminals of the N inverters are connected to each other; the AC output terminals of the N inverters are used to connect to a transformer; the DC input terminals of the N inverters are respectively connected to N DC power supplies; and the negative terminals of the N DC power supplies are connected to each other.

14. The apparatus according to any one of claims 10-13, characterized in that, The processor is specifically used for: The common-mode injection voltage of each inverter is determined based on the common-mode voltage injection method of each inverter.

15. The apparatus according to claim 14, characterized in that, The common-mode voltage injection methods include sinusoidal pulse width modulation (SPWM), voltage space vector pulse width modulation (SVPWM), or discontinuous pulse width modulation (DPWM).

16. The apparatus according to any one of claims 10-13, characterized in that, The target common-mode voltage is obtained by the following formula: U cmv = U cmv0 + U vir ； U vir = i cmv R vir ； in, U cmv The target common-mode voltage, U cmv0 For the common-mode injection voltage, U vir The virtual damping voltage is... R vir The preset common-mode damping coefficient is... i cmv The common-mode current is denoted as .

17. The apparatus according to claim 16, characterized in that, The common-mode current is obtained by the following formula: i cmv =( i a + i b + i c ) / 3； in, i a , i b , i c These are the three-phase output currents of the inverter. i cmv The common-mode current is denoted as .

18. The apparatus according to any one of claims 10-13, characterized in that, The processor is further configured to superimpose the target common-mode voltage of each inverter with the differential-mode voltage of each inverter to obtain the modulation voltage of each inverter; The controller is specifically used to use the modulation voltage of each inverter obtained by the processor as the drive signal of the switching element of each inverter to control the operation of each inverter.

19. A power supply system, characterized in that, The power supply system includes an inverter parallel system and a circulating current suppression device in the inverter parallel system as described in any one of claims 10-18, wherein the circulating current suppression device in the inverter parallel system is used to suppress the circulating current in the inverter parallel system.

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