Metrology mark, semiconductor structure, metrology method, apparatus, and storage medium

Abstract

The present disclosure relates to a metrology mark, a semiconductor structure, a metrology method, an apparatus and a storage medium. The metrology mark is disposed on a semiconductor structure, the semiconductor structure comprises a substrate, the metrology mark is applied to an etching post-process inspection, the metrology mark comprises a first mark layer and a second mark layer stacked together, a projection profile of the first mark layer on the substrate coincides with a projection profile of the second mark layer on the substrate; the metrology mark comprises a first mark group on the first mark layer and a second mark group on the second mark layer; the metrology mark is configured such that, after the metrology light passes through the first mark group and the second mark group, the intensity distribution of the zero-order diffraction light of the metrology light is asymmetric. The metrology mark can be used to measure the overlay error between any two layers of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of semiconductor technology, and particularly to a measurement marker, semiconductor structure, measurement method, device, and storage medium. Background Technology

[0002] Semiconductor structures typically comprise multiple patterned material layers, where each current layer must be aligned with the previous layer within tight tolerances. The registration error between the current and previous layers in a semiconductor structure is called overlay error, also known as superposition error. Specifically, overlay error describes the pattern of the current layer relative to the pattern of the previous layer along the X-axis of the wafer surface (reference). Figure 1 (as shown) and the Y direction (reference) Figure 1 The diagram shows the deviation (as shown) and its distribution on the wafer surface. Overlay error is a key indicator for evaluating the quality of photolithography. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a measurement marker, a semiconductor structure, a measurement method, an apparatus, and a storage medium.

[0005] According to a first aspect of the present disclosure, a measurement mark for overlay error is provided, disposed on a semiconductor structure, the semiconductor structure including a substrate, the measurement mark being applied to an inspection process after etching, the measurement mark including a stacked first marking layer and a second marking layer, wherein the projection contour of the first marking layer on the substrate coincides with the projection contour of the second marking layer on the substrate;

[0006] The measurement markers include a first group of markers located in the first marker layer and a second group of markers located in the second marker layer;

[0007] The measurement markers are configured such that, after the measurement light passes through the first marker group and the second marker group, the intensity distribution of the zero-order diffracted light of the measurement light is asymmetrical.

[0008] The measurement mark includes at least one measurement pair, the measurement pair includes a plurality of first mark units in the first mark group and a plurality of second mark units in the second mark group, and the projections of the plurality of measurement pairs on the substrate are staggered.

[0009] In the measurement pair, the plurality of first marker units are arranged in a first preset manner, and the plurality of second marker units are arranged in a second preset manner. The first preset manner is either row-based or column-based, and the second preset manner is either row-based or column-based.

[0010] Among the measurement pairs,

[0011] The plurality of first marker units are arranged in different ways; and / or,

[0012] The arrangement of the multiple second marker units is different.

[0013] The number of first marker units in the plurality of first marker units is different from the number of second marker units in the plurality of second marker units.

[0014] The first marking unit and the second marking unit have different shapes.

[0015] The first marking unit and the second marking unit have different sizes.

[0016] In the measurement pair's projection onto the substrate, the projections of the plurality of first marking units are offset from or intersect with the projections of the plurality of second marking units.

[0017] The measurement pair includes multiple sub-pairs, each sub-pair including a first marking unit and a second marking unit, and the projections of the multiple sub-pairs on the substrate are staggered.

[0018] Wherein, the projection of the first marking unit on the substrate is offset from or intersects with the projection of the second marking unit on the substrate.

[0019] The first marking layer is located in the open-hole layer of the semiconductor structure.

[0020] According to a second aspect of the present disclosure, a semiconductor structure is provided, the semiconductor structure being provided with measurement marks as described in the first aspect.

[0021] The measurement mark is located in the dicing region of the semiconductor structure.

[0022] The semiconductor further includes an active region, and the dicing region is located on the periphery of the active region.

[0023] The measurement marks are set at multiple locations in the cutting channel area surrounding the active region.

[0024] The semiconductor structure includes a first layer and a second layer. The first marking layer of the measurement mark belongs to the first layer, the second marking layer of the measurement mark belongs to the second layer, and the first layer is located on top of the second layer.

[0025] The first layer has multiple openings.

[0026] According to a third aspect of the present disclosure, a method for measuring overlay error is provided, the method comprising:

[0027] After the semiconductor structure is etched, the measurement light is controlled to enter from the first marking layer of the semiconductor structure, and the zero-order diffracted light after the measurement light passes through the first marking group of the first marking layer and the second marking group of the second marking layer of the semiconductor structure is collected. The first marking layer and the second marking layer form the measurement mark as described in the first aspect, and the measurement mark is located in the dicing area of ​​the semiconductor structure.

[0028] Based on the intensity distribution of the zero-order diffracted light, the overlay error between the first layer and the second layer is determined.

[0029] According to a fourth aspect of the present disclosure, a measuring device for overlay error is provided, the measuring device comprising:

[0030] processor;

[0031] Memory used to store processor-executable instructions;

[0032] The processor is configured to perform the measurement method as described in the third aspect.

[0033] According to a fifth aspect of the present disclosure, a non-transitory computer-readable storage medium is provided, which, when instructions in the storage medium are executed by a processor of a measurement device, enables the measurement device to perform the measurement method as described in the third aspect.

[0034] The embodiments of this disclosure employ the above technical solution and have the following advantages: After the measurement light passes through the measurement mark, the intensity distribution of its zero-order diffracted light is asymmetrical. Therefore, based on the asymmetry of the intensity distribution of the zero-order diffracted light, the overlay error between the first mark group of the first mark layer (e.g., the current layer) and the second mark group of the second mark layer (e.g., the previous layer) in the measurement mark can be calculated, thereby obtaining the overlay error between the current layer and the previous layer of the semiconductor structure, and realizing accurate measurement of the overlay error. This measurement mark can be used to measure the overlay error between any two layers in a semiconductor structure.

[0035] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0036] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in the invention and should not be construed as limiting the scope of the invention.

[0037] Figure 1a This is a schematic diagram of measurement technology based on image recognition and scanning electron microscopy.

[0038] Figure 1 This is a schematic diagram illustrating a measurement mark according to an exemplary embodiment;

[0039] Figure 2 This is a schematic diagram of the first and second layers of a semiconductor structure as shown in an example;

[0040] Figure 3 This is a schematic diagram of a semiconductor structure as illustrated in one example;

[0041] Figure 4 This is a top view of a measurement mark as shown in the example;

[0042] Figure 5 This is a top view of a measurement mark as shown in the example;

[0043] Figure 6 This is a top view of a measurement mark as shown in the example;

[0044] Figure 7 This is a top view of a measurement mark as shown in the example;

[0045] Figure 8 This is a top view of a measurement mark as shown in the example;

[0046] Figure 9 This is a top view of a measurement mark as shown in the example;

[0047] Figure 10 This is a top view of a measurement mark as shown in the example;

[0048] Figure 11 This is a top view of a measurement mark as shown in the example;

[0049] Figure 12 This is a top view of a measurement mark as shown in the example;

[0050] Figure 13 This is a top view of a measurement mark as shown in the example;

[0051] Figure 14 This is a top view of a measurement mark as shown in the example;

[0052] Figure 15 This is a top view of a measurement mark as shown in the example;

[0053] Figure 16This is a top view of a measurement mark as shown in the example;

[0054] Figure 17 This is a flowchart illustrating a measurement method based on an example;

[0055] Figure 18 This is a block diagram illustrating a measurement setup based on an example.

[0056] Key reference numerals in the accompanying drawings: 1. Semiconductor structure; 10. First layer; 20. Second layer; 30. Substrate; 11. Active region; 12. Cleavage region; 2. Measurement mark; 100. First mark layer; 110. First mark group; 111. First mark unit; 200. Second mark layer; 210. Second mark group; 211. Second mark unit; 300. Measurement pair; 310. Sub-pair; 3. Measurement device; 31. Processor; 32. Memory. Detailed Implementation

[0057] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of this disclosure. Therefore, the drawings and description are considered to be exemplary in nature and not restrictive.

[0058] The detection of overlay errors is generally divided into after development inspection (ADI) and after etching inspection (AEI).

[0059] Post-development inspection refers to CD (critical dimension) measurement after development. It is generally used to test the performance indicators of exposure and development machines. After exposure and development are completed, the resulting pattern is qualitatively checked using an ADI machine to see if it is normal. Because it cannot be measured by transmitted light, ADI typically uses electron beam or scanning electron microscopy methods.

[0060] Post-etching inspection refers to CD measurement after etching. Before and after photoresist removal during the etching process, full inspection or sampling inspection is performed on the product.

[0061] Overlay errors can generally be measured using image-based overlay (IBO), scanning electron microscopy (SEM), and novel diffraction measurement techniques (IDM, InDevice Metrology, also known as In Die Measurement).

[0062] SEM is generally used for post-development inspection. However, for open layers with apertures in semiconductor structures, SEM cannot accurately measure the lateral direction (see reference). Figure 1 (X direction) and longitudinal direction (reference) Figure 1 Overlay error in the Y direction (reference) Figure 1a (As shown). IBO is also generally used for post-development inspection and relies on measurement marks. However, it cannot accurately measure overlay errors in open-cell layers with apertures in semiconductor structures (see reference). Figure 1a As shown in the figure, IDM is generally used for post-etching inspection. It does not require the setting of specific measurement marks, but uses the original pattern of the semiconductor structure to measure the overlay error. However, IDM relies on the asymmetry of the intensity of the zero-order diffracted light for measurement. For the open layer with openings in the semiconductor structure, there is no asymmetry in the intensity distribution of the zero-order diffracted light after passing through the original pattern of the current layer and the original pattern of the previous layer, so it is impossible to measure the overlay error.

[0063] This disclosure provides a measurement mark for overlay error, applied to post-etching inspection. After the measurement light passes through the measurement mark, the intensity distribution of its zero-order diffracted light is asymmetrical. Therefore, based on this asymmetry in the intensity distribution of the zero-order diffracted light, the overlay error between the first mark group of the first mark layer (e.g., the current layer) and the second mark group of the second mark layer (e.g., the previous layer) can be calculated, thereby obtaining the overlay error between the current layer and the previous layer of the semiconductor structure, achieving accurate measurement of the overlay error. This measurement mark can be used to measure the overlay error between any two layers in a semiconductor structure.

[0064] In one exemplary embodiment, a measurement mark for overlay error is provided. This measurement mark is disposed on a semiconductor structure to enable inspection of the etching between two layers in the semiconductor structure, thereby measuring the overlay error.

[0065] See Figures 1 to 3 As shown, the measurement mark 2 may include a first mark layer 100 and a second mark layer 200 stacked together, that is, the first mark layer 100 and the second mark layer 200 are aligned vertically (see reference). Figure 1 The marking layer 100 is arranged in the Z direction. The first marking layer 100 is the first layer 10 of the two layers for which overlay error needs to be detected, and the second marking layer 200 is the second layer 20 of the two layers for which overlay error needs to be detected. The first layer 10 can be the current layer, and the second layer 20 can be a previous layer.

[0066] Semiconductor structure 1 includes a substrate 30, with a first marking layer 100 and a second marking layer 200 both located on the upper layer of the substrate 30. The projected outline of the first marking layer 100 on the substrate 30 coincides with the projected outline of the second marking layer 200 on the substrate 30. Measurement marks 2 include a first mark group 110 located on the first marking layer 100 and a second mark group 210 located on the second marking layer 200. That is, the first mark group 110 and the second mark group 210 form a pair of mark groups to form a zero-order diffracted ray of measurement light.

[0067] The measurement mark 2 is configured such that after the measurement light passes through the first mark group 110 and the second mark group 210, the intensity distribution of the zero-order diffracted light of the measurement light is asymmetrical.

[0068] Among them, reference Figure 1 and 6 As shown, the measurement mark 2 may include at least one measurement pair 300. When there is more than one measurement pair, the multiple (two or more) measurement pairs 300 may be the same or different.

[0069] refer to Figure 1 As shown, each measurement pair 300 may include a plurality of first marker units 111 in the first marker group 110 (reference). Figure 1 Multiple first marker units 111 within the dashed box in the first marker group 110, and multiple second marker units 211 in the second marker group 210 (see reference). Figure 1 The multiple second marker units 211 within the dashed box in the second marker group 210, and the projections of the multiple measurement pairs on the substrate 30 are staggered.

[0070] The first marking unit 111 can be a hole or a solid mark (such as a patch, film, etc.). The second marking unit 211 can also be a hole or a solid mark, as long as the intensity distribution of the zero-order diffracted light is asymmetrical after the measurement light passes through the first marking group 110 and the second marking group 210.

[0071] In each measurement pair 300, multiple first marker units 111 are arranged in a first preset manner, and multiple second marker units 211 are also arranged in the first preset manner; that is, the arrangement of the multiple first marker units 111 and the multiple second marker units 211 is the same. The first preset manner can be a row arrangement, a column arrangement, or other arrangements besides a column arrangement and a row arrangement. The row arrangement refers to horizontal arrangement (see reference). Figure 1 (X direction), column method refers to along the longitudinal direction (refer to) Figure 1 Arranged in the Y direction, with the horizontal, vertical and longitudinal directions perpendicular to each other.

[0072] For example, refer to Figure 6 As shown ( Figure 6 The dashed lines are only used to show the first marker unit 111a and the second marker unit 211a included in the measurement pair 300a. The first preset mode is row mode. In the measurement pair 300a, multiple first marker units 111a are arranged in a row, and multiple second marker units 211a are arranged in a row.

[0073] For example, refer to Figure 14 As shown ( Figure 14 The dashed lines are only for illustrating the first marker unit 111i and the second marker unit 211i included in the measurement pair 300i. The first preset mode is a column mode. In the measurement pair 300i, multiple first marker units 111i are arranged in a column, and multiple second marker units 211i are arranged in a column.

[0074] It should be noted that in this measurement mark, the first mark unit located in the first mark layer and the second mark unit located in the second mark layer may not form a pair of measurement units.

[0075] For example, a first tagging layer may include multiple rows of first tagging units, each row of first tagging units including multiple first tagging units; a second tagging layer may include multiple rows of second tagging units, each row of second tagging units including multiple second tagging units. The number of rows of first tagging units in the first tagging layer is denoted as the first row number, and the number of rows of second tagging units in the second tagging layer is denoted as the second row number. The first row number and the second row number may be different or the same.

[0076] refer to Figure 4 As shown, when the number of the first row is different from the number of the second row, the first marker unit located in the first marker layer and the second marker unit located in the second marker layer will no longer form a pair of measurement pairs, or there will be at least one unpaired row of first marker units or one unpaired row of second marker units.

[0077] refer to Figure 6 As shown, when the number of the first row is the same as the number of the second row, the measurement markers may include the same number of measurement pairs as the number of the first row.

[0078] It should also be noted that the arrangement of multiple first marker units and multiple second marker units in a measurement pair can be different. When the two arrangements are different, the arrangement of multiple first marker units in the measurement pair can be the same, and the arrangement of multiple second marker units can also be the same.

[0079] For example, refer to Figure 5As shown (the dashed line in the figure is only to show the 10° angle), in the measurement pair 300n, multiple first marking units 111n are arranged horizontally (i.e., arranged in rows), and multiple second marking units 211n are arranged at a 10° angle to the horizontal direction. At this time, the length direction of multiple first marking units 111n is parallel to the horizontal direction, and the length direction of multiple second marking units 211n is at a 10° angle to the horizontal direction.

[0080] When using this measurement mark to measure the overlay error, the measurement light source illuminates the location of the measurement mark. The measurement light emitted by the measurement light source forms multi-order diffracted light after passing through the first and second mark groups. From the multi-order diffracted light, the zero-order diffracted light is collected, and the light intensity distribution of the zero-order diffracted light is formed. Then, based on the asymmetry of the light intensity distribution, the overlay error between the first and second mark layers is determined, thereby determining the overlay error between the first and second layers of the semiconductor structure, and realizing the measurement of the overlay error between the first and second layers.

[0081] In addition, since the intensity distribution of the zero-order diffracted light is asymmetrical after the measurement light passes through the first and second mark groups of the measurement mark, the overlay error between any two layers can be measured through the measurement mark without being limited by the image of the active region of each layer, thus improving the applicability of overlay error measurement based on diffraction.

[0082] The first layer can be an open-hole layer of a semiconductor structure, that is, the first marking layer can be located in the open-hole layer of the semiconductor structure, and the measurement of the overlay error between the open-hole layer and other layers has been completed.

[0083] It should be noted that the first and second floors can be adjacent floors (e.g., Figure 3 As shown), it can also be two non-adjacent layers (not shown in the figure), that is, there may be no other layers between the first layer and the second layer, or there may be other layers. The second layer can be in direct contact with the substrate (e.g., Figure 3 As shown in the figure, other layers (not shown in the figure) may also be disposed between the second layer and the substrate.

[0084] In one exemplary embodiment, a measurement marker is provided. In each measurement pair of the measurement marker, a plurality of first marker units are arranged in a different manner, or a plurality of second marker units are arranged in a different manner, or a plurality of first marker units are arranged in a different manner and a plurality of second marker units are arranged in a different manner.

[0085] Example 1,

[0086] refer to Figure 6 As shown, the first marking unit 111a is a rectangular unit, and the second marking unit 211a is a square unit.

[0087] In each measurement pair 300a, the first preset mode and the second preset mode are the same, and the arrangement of multiple first marker units 111a is different, while the arrangement of multiple second marker units 211a is the same.

[0088] Among them, some (at least one) of the first marking units 111a1 are arranged along the row direction, some of the first marking units 111a2 are arranged along the direction perpendicular to the row direction (i.e., the column direction), and some of the first marking units 111a3 are arranged at a 45° angle to the row direction.

[0089] Example 2,

[0090] refer to Figure 7 As shown, the first marking unit 111b is a square unit, and the second marking unit 211b is a rectangular unit.

[0091] In each measurement pair, the first preset method and the second preset method are the same, the multiple first mark units 111b are arranged in the same way, and the multiple second mark units 211b are arranged in different ways.

[0092] Among them, some (at least one) of the second marking units 211b1 are arranged along the row direction, some of the second marking units 211b2 are arranged along the direction perpendicular to the row direction (i.e., the column direction), and some of the second marking units 211b3 are arranged at a 45° angle to the row direction.

[0093] Example 3,

[0094] refer to Figure 8 As shown, the first marking unit 111c is a first rectangular unit, and the second marking unit 211c is a second rectangular unit.

[0095] In each measurement pair, the first preset method and the second preset method are the same, the arrangement of multiple first marker units 111c is different, and the arrangement of multiple second marker units 211c is different.

[0096] The length direction of the first marking unit 111c1 in the first part is arranged along the row direction; the length direction of the first marking unit 111c2 in the second part is arranged along the column direction (perpendicular to the row direction); and the length direction of the first marking unit 111c3 in the third part is arranged at a 45° angle to the row direction. Similarly, the length direction of the second marking unit 211c1 in the first part is arranged along the row direction; the length direction of the second marking unit 211c2 in the second part is arranged along the column direction (perpendicular to the row direction); and the length direction of the second marking unit 211c3 in the third part is arranged at a 45° angle to the row direction.

[0097] The first marking unit 111c1 in the first part is set to correspond with the second marking unit 211c2 in the second part, the first marking unit 111c2 in the second part is set to correspond with the second marking unit 211c3 in the third part, and the third marking unit 111c3 in the third part is set to correspond with the third marking unit 211c1 in the first part.

[0098] In this measurement mark, the arrangement of multiple first mark units in each measurement pair is set to be different, or the arrangement of multiple second mark units in each measurement pair is set to be different, or the arrangement of multiple first mark units and multiple second mark units in each measurement pair is set to be different at the same time, so as to enhance the asymmetry of the intensity part of the zero-order diffracted light, so as to better measure the overlay error accurately.

[0099] In one exemplary embodiment, a measurement mark is provided. In this measurement mark, the number of first marker units in a plurality of first marker units differs from the number of second marker units in a plurality of second marker units. That is, in each measurement pair, the number of first marker units differs from the number of second marker units, thereby enhancing the asymmetry of the intensity portion of the zero-order diffracted ray.

[0100] In each measurement pair, the number of the first marker units is denoted as the first quantity, and the number of the second marker units is denoted as the second quantity. The first quantity is greater than the second quantity, or the second quantity is greater than the first quantity.

[0101] Example 1,

[0102] refer to Figure 9 As shown, the first marking unit 111d is a first rectangular unit, and the second marking unit 211d is a second rectangular unit. In each measurement pair, the first quantity is 4, and the second quantity is 3.

[0103] Example 2,

[0104] refer to Figure 10 As shown, the first marking unit 111e is a first rectangular unit, and the second marking unit 211e is a second rectangular unit. In each measurement pair, the first quantity is 2, and the second quantity is 4.

[0105] The shapes of the first and second marker units can also be different. By changing the shapes, the asymmetry of the intensity distribution of the zero-order diffracted light can be enhanced.

[0106] Example 3,

[0107] refer to Figure 11 As shown, the first marking unit 111f is a rectangular unit, and the second marking unit 211f is a circular unit.

[0108] Example 4,

[0109] refer to Figure 12 As shown, the first marking unit 111g is rectangular, and the second marking unit 211g is square.

[0110] In addition, the first marking unit and the second marking unit can also have different sizes. By changing the size, the asymmetry of the intensity distribution of the zero-order diffracted light can also be enhanced.

[0111] Example 5,

[0112] refer to Figure 13 As shown, both the first marking unit 111h and the second marking unit 211h are rectangular units. The length of the long side of the first marking unit 111h is greater than the length of the long side of the second marking unit 211h, and the length of the wide side of the second marking unit 111h is equal to the length of the wide side of the second marking unit 211h.

[0113] It should be noted that, except for the inability to simultaneously set different sizes and shapes, all other settings can be used simultaneously to better enhance the asymmetry of the intensity distribution of the zero-order diffracted light, thereby further improving the accuracy of overlay error measurement. Furthermore, since there are multiple ways to set the measurement marks, the applicable scenarios for the measurement marks can be expanded, facilitating the setting of different measurement marks on different layers to better measure overlay errors between different layers.

[0114] In one exemplary embodiment, a measurement mark is provided. In this measurement mark, in the projection of the measurement pair onto a substrate, the projections of a plurality of first mark units are offset from or intersect with the projections of a plurality of second mark units.

[0115] In this configuration, the projections of multiple first marker units are staggered from the projections of multiple second marker units, and the projections of any first marker unit do not intersect with the projections of any second marker unit.

[0116] Example 1,

[0117] refer to Figure 14 As shown, the measurement markers include two measurement pairs 300i. Each measurement pair 300i includes a column of first marker units 111i and a column of second marker units 211i. The column of first marker units 111i includes four first marker units 111i, and the column of second marker units 211i includes four second marker units 211i. The projection of the column of first marker units 111i onto the substrate is offset from the projection of the column of second marker units 211i onto the substrate.

[0118] Wherein, the projections of multiple first marker units intersect with the projections of multiple second marker units, and the projection of at least one first marker unit intersects with the projection of at least one second marker unit.

[0119] Example 2,

[0120] refer to Figure 15 As shown, the measurement mark includes two measurement pairs. Each measurement pair includes a row of first mark units 111j and a row of second mark units 211j. The row of first mark units 111j includes four first mark units 111j, and the row of second mark units 211j includes four second mark units 211j. Only the projection of the first first mark unit 111j onto the substrate intersects with the projection of the first second mark unit 211j onto the substrate.

[0121] Example 3,

[0122] refer to Figure 16 As shown ( Figure 16 The dashed lines are only for showing the first marker unit 111k and the second marker unit 211k included in the subpair 310k. The measurement markers include three measurement pairs, each measurement pair including a row of first marker units 111k and a row of second marker units 211k. The row of first marker units 111k includes four first marker units 111k, and the row of second marker units 211k includes four second marker units 211k. In the projection of the measurement pair onto the substrate, the projections of the first marker units 111k and the projections of the second marker units 211k intersect each other.

[0123] The measurement pair may include multiple sub-pairs, each sub-pair may include a first marking unit and a second marking unit, and the projections of the multiple sub-pairs on the substrate are staggered to facilitate the setting of measurement marks.

[0124] In the projection of the subpair onto the substrate, the projection of the first marking unit and the projection of the second marking unit can be either staggered or intersecting.

[0125] refer to Figure 14 As shown, when the projections of multiple first marker units 111i and multiple second marker units 211i are misaligned in the projection of the measurement pair onto the substrate, the projections of the first marker unit 111i and the second marker unit 211i are all misaligned in the projection of each subpair 310i onto the substrate.

[0126] refer to Figure 16 As shown, when the projection of the first marking unit 111k intersects with the projection of the second marking unit 211k in the projection of any subpair 310k on the substrate, the projections of multiple first marking units 111k intersect with the projections of multiple second marking units 211k in the projection of the measurement pair on the substrate.

[0127] In this measurement mark, in the projection of the measurement pair onto the substrate, the projections of multiple first mark units and multiple second mark units can be either staggered or intersecting; similarly, in the projection of the sub-pair onto the substrate, the projections of the first mark units and the second mark units can also be either staggered or intersecting. This configuration provides more ways to arrange the measurement marks, expands their applicability, and facilitates the measurement of overlay errors between different layers.

[0128] In one exemplary embodiment, a semiconductor structure is provided, which is provided with the above-described measurement marks to measure the overlay error between different layers.

[0129] refer to Figure 1-3 As shown, the measurement mark 2 is located in the dicing region 12 of the semiconductor structure 1 to avoid damaging the active region 11 of the semiconductor structure 1. Therefore, the overlay error between different layers can be measured by the measurement mark 2 in the dicing region 12, thereby obtaining the overlay error of the active region 11 pattern between different layers and improving the product yield of the semiconductor structure 1.

[0130] Among them, reference Figures 1 to 3 As shown, the semiconductor structure 1 may include a first layer 10 and a second layer 20. The first marking layer 100 of the measurement mark 2 belongs to the first layer 10, and the second marking layer 200 of the measurement mark 2 belongs to the second layer 20. The first layer 10 may be located on top of the second layer 20.

[0131] refer to Figures 1 to 3 As shown, during measurement, the measurement light is incident from the first layer 10. After passing through the first mark group 110 of the first layer 10 and the second mark group 210 of the second layer 20, the intensity distribution of its zero-order diffracted light is asymmetrical. Then, based on the asymmetry, the overlay error of the first layer 10 and the second layer 20 is calculated.

[0132] Since a measurement mark 2 specifically for measuring overlay error is added to the semiconductor structure 1 and the measurement mark 2 is set in the dicing area 12, even if the first layer 10 or the second layer 20 is an open layer, or both the first layer 10 and the second layer 20 are open layers, the measurement of overlay error between the first layer 10 and the second layer 20 will not be affected.

[0133] For example, the first layer 10 has multiple openings, meaning the first layer 10 is an opening layer. By setting the aforementioned measurement mark 2, the overlay error between the pattern of the active area 11 of the first layer 10 and the pattern of the active area 11 of the second layer 20 can still be accurately measured.

[0134] In one exemplary embodiment, a method for measuring overlay error is provided. (See reference...) Figure 17 As shown, the measurement method may include:

[0135] S101. After the semiconductor structure is etched, the measurement light is controlled to enter from the first marking layer of the semiconductor structure, and the zero-order diffracted light after the measurement light passes through the first marking group of the first marking layer and the second marking group of the second marking layer is collected.

[0136] S102. Based on the intensity distribution of the zero-order diffracted light, determine the overlay error between the first and second layers.

[0137] The first and second marking layers form the aforementioned measurement marks. That is, this measurement method is applied to the semiconductor structure with the aforementioned measurement marks.

[0138] This measurement method differs from typical IBO and IDM methods; it combines the advantages of both. In this method, measurement marks are pre-set in the semiconductor structure, and overlay error is measured based on the intensity distribution of zero-order diffracted light. This allows for the measurement of overlay error between any two layers in the semiconductor structure. In other words, this method can accurately measure the overlay error between the aperture layer and other layers, thus improving product yield.

[0139] The measurement mark can be located in the dicing region of the semiconductor structure. That is, this measurement method is applied to the semiconductor structure with measurement marks set in the dicing region. Setting the measurement mark in the dicing region avoids interference between the measurement mark and the active area pattern, ensuring both the performance of the semiconductor structure and the accurate setting of the measurement mark, further improving measurement accuracy and expanding the applicable scenarios for the measurement mark.

[0140] This measurement method uses measurement marks in the cutting zone to measure the overprinting error between the active area pattern of the first layer and the active area pattern of the second layer, thereby improving measurement accuracy and increasing product yield.

[0141] In one exemplary embodiment, a measuring device is provided. This measuring device is used to implement the measurement method described above. The measuring device may be provided as a server. (See reference...) Figure 18 As shown, the measurement device 3 may include a processor 31, and the number of processors 31 can be set to one or more as needed. The measurement device 3 may also include a memory 32 for storing executable instructions of the processor 31, such as application programs. The number of memories 32 can be set to one or more as needed. The stored application programs can be one or more. The processor 31 is configured to execute instructions to perform the measurement method described above.

[0142] For example, processor 31 is configured to execute:

[0143] After the semiconductor structure is etched, the measurement light is controlled to enter from the first marking layer of the semiconductor structure, and the zero-order diffracted light after the measurement light passes through the first marking group of the first marking layer and the second marking group of the second marking layer is collected.

[0144] The overlay error between the first and second layers is determined based on the intensity distribution of the zero-order diffracted light.

[0145] In one exemplary embodiment, a non-transitory computer-readable storage medium (not shown) is provided. When the instructions in the storage medium are executed by the processor of the aforementioned measurement device, the measurement device is able to perform the aforementioned measurement method.

[0146] For example, when the instructions in the storage medium are executed by the processor of the aforementioned measurement device, the measurement device is able to perform:

[0147] After the semiconductor structure is etched, the measurement light is controlled to enter from the first marking layer of the semiconductor structure, and the zero-order diffracted light after the measurement light passes through the first marking group of the first marking layer and the second marking group of the second marking layer is collected.

[0148] The overlay error between the first and second layers is determined based on the intensity distribution of the zero-order diffracted light.

[0149] In the description of this specification, references to terms such as "embodiment," "implementation," etc., refer to specific features, structures, materials, or characteristics incorporated in that embodiment or implementation that are included in at least one embodiment or implementation of the present invention. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or implementations. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or implementations described in this specification, as well as the features of those different embodiments or implementations.

[0150] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defining "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0151] The foregoing disclosure provides different implementations or embodiments to achieve different structures of the present invention. To simplify the disclosure, specific examples of components and arrangements are described above. Of course, these are merely illustrative and not intended to limit the invention. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed. In addition, the present invention provides examples of various specific processes and materials, but those skilled in the art will conceive of other processes and / or the use of other materials.

[0152] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can conceive of other modifications or substitutions within the technical scope disclosed in the present invention, and such modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A measurement mark for overlay error, disposed on a semiconductor structure, said semiconductor structure including a substrate, characterized in that, The measurement mark is used in the inspection process after etching. The measurement mark includes a first mark layer and a second mark layer stacked together. The projection outline of the first mark layer on the substrate coincides with the projection outline of the second mark layer on the substrate. The measurement markers include a first group of markers located in the first marker layer and a second group of markers located in the second marker layer; The measurement marks are configured such that after the measurement light passes through the first mark group and the second mark group, the intensity distribution of the zero-order diffracted light of the measurement light is asymmetrical. The measurement mark is located in the dicing region of the semiconductor structure; The measurement mark includes at least one measurement pair, the measurement pair includes a plurality of first mark units in the first mark group and a plurality of second mark units in the second mark group, and the projections of the plurality of measurement pairs on the substrate are staggered. Multiple first marking units are arranged in a horizontal direction, and multiple second marking units are arranged at a 10° angle to the horizontal direction; the first marking units and the second marking units have different shapes and different sizes.

2. The measurement mark as described in claim 1, characterized in that, In the measurement pair, the plurality of first marker units are arranged in a first preset manner, and the plurality of second marker units are arranged in a second preset manner. The first preset manner is either row-based or column-based, and the second preset manner is either row-based or column-based.

3. The measurement mark as described in claim 1, characterized in that, In the measurement pair, The plurality of first marker units are arranged in different ways; and / or, The arrangement of the multiple second marker units is different.

4. The measurement mark as described in claim 1, characterized in that, The number of first marker units in the plurality of first marker units is different from the number of second marker units in the plurality of second marker units.

5. The measurement mark as described in claim 1, characterized in that, In the projection of the measurement pair onto the substrate, the projections of the plurality of first marking units are offset from or intersect with the projections of the plurality of second marking units.

6. The measurement mark as described in claim 5, characterized in that, The measurement pair includes multiple sub-pairs, each sub-pair including a first marking unit and a second marking unit, and the projections of the multiple sub-pairs on the substrate are staggered.

7. The measurement mark as described in claim 6, characterized in that, The projection of the first marking unit on the substrate is offset from or intersects with the projection of the second marking unit on the substrate.

8. The measurement mark as described in any one of claims 1-7, characterized in that, The first marking layer is located in the open-hole layer of the semiconductor structure.

9. A semiconductor structure, characterized in that, The semiconductor structure is provided with measurement markings as described in any one of claims 1 to 8.

10. The semiconductor structure as described in claim 9, characterized in that, The measurement markers are located in the dicing region of the semiconductor structure.

11. The semiconductor structure as claimed in claim 10, characterized in that, The semiconductor also includes an active region, and the diced channel region is located on the periphery of the active region.

12. The semiconductor structure as claimed in claim 11, characterized in that, The measurement marks are set at multiple locations in the cutting channel area surrounding the active region.

13. The semiconductor structure as described in claim 10, characterized in that, The semiconductor structure includes a first layer and a second layer. The first marking layer of the measurement mark belongs to the first layer, and the second marking layer of the measurement mark belongs to the second layer. The first layer is located on top of the second layer.

14. The semiconductor structure as described in claim 13, characterized in that, The first layer has multiple openings.

15. A method for measuring overlay error, characterized in that, The measurement method includes: After the semiconductor structure is etched, the measurement light is controlled to enter from the first marking layer of the semiconductor structure, and the zero-order diffracted light after the measurement light passes through the first marking group of the first marking layer and the second marking group of the second marking layer of the semiconductor structure is collected, wherein the first marking layer and the second marking layer form the measurement mark as described in any one of claims 1-8, and the measurement mark is located in the dicing area of ​​the semiconductor structure; Based on the intensity distribution of the zero-order diffracted light, the overlay error between the first marking layer and the second marking layer is determined.

16. A measuring device for overlay error, characterized in that, The measuring device includes: processor; Memory used to store processor-executable instructions; The processor is configured to perform the measurement method as described in claim 15.

17. A non-transitory computer-readable storage medium, characterized in that, When the instructions in the storage medium are executed by the processor of the measurement device, the terminal is able to perform the measurement method as described in claim 15.

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