Multi-level processor reset method and system

Abstract

The multi-level processor reset method and system of the present invention relate to the technical field of multi-processor system reset technology. The method comprises a primary controller, a reset control unit, a power control unit, and a multi-level controller, each communicating with the primary controller. The multi-level controller is connected to a multi-level logic control unit and a dedicated controller according to preset criteria. The reset control unit is provided with a watchdog circuit, and the power control unit includes a power conversion unit, a first comparison unit, a second comparison unit, and a power-off control unit. Reset methods include power-on reset, software reset, manual reset, external watchdog timeout reset, and power-off recovery reset. The comprehensive application of the system and method of the present invention enables a hierarchical design of multi-level reset sources, reduces the coupling of reset sources, and achieves reliable system reset for multi-processor systems.

Description

Technical Field

[0001] The present invention belongs to the technical field of multi-processor system reset, and in particular relates to a multi-level processor reset method and system. Background Art

[0002] The increasing complexity of avionics equipment is driving higher demands on digitalization, processing speed, and performance. An increasing number of electronic and electrical devices are adopting multi-level controller architectures to implement diverse functions. A single electronic device may simultaneously integrate a PowerPC processor, a DSP processor, an FPGA logic control unit, and various microcontrollers. The difficulty in achieving hierarchical and layered control of the reset of these multiple processors while ensuring coordinated and consistent operation has become a design challenge. Furthermore, to enhance system reliability, the system incorporates multiple reset sources, making reliable and secure reset of these reset sources particularly crucial.

[0003] Traditional avionics systems employ internal or external watchdogs and implement real-time watchdog feeding to ensure timely detection and resolution of software anomalies. However, traditional watchdog reset source design fails to adequately consider the watchdog's own testing. Multiple reset sources can cause mutual coupling. Furthermore, traditional watchdog timeouts are typically implemented using hardware capacitors, which are significantly affected by environmental factors. This can lead to watchdog feeding failures and reduce the mission reliability of the avionics system. Summary of the Invention

[0004] In view of this, the present invention provides a multi-level processor reset system to overcome the shortcomings of the existing technology and realize the coordinated and reliable operation of multiple processors and multiple reset sources. Through the hierarchical design of the multi-level reset source, the coupling of the reset source is reduced. By setting power-on reset, software reset, manual reset, external watchdog timeout reset and power-off recovery reset, a highly reliable system reset is achieved.

[0005] A multi-stage processor reset system is provided, suitable for resetting a processor system of an avionics product. The system includes a primary controller and a reset control unit communicating with the primary controller, a power control unit, and a multi-stage controller. The multi-stage controller is connected to a multi-stage logic control unit and a dedicated controller according to preset criteria. The reset control unit is provided with a watchdog circuit. The power control unit includes a power conversion unit, a first comparison unit, a second comparison unit, and a power-off control unit, including:

[0006] The primary controller includes a loading / confirmation module, which is connected to multiple logic control units and a dedicated controller via a second logic "OR" unit;

[0007] The watchdog circuit is configured to send a "feed the dog" signal during a preset time period, receive a "feed the dog" signal sent by the primary controller during a preset time period, and indicate a dog feeding timeout by sending a "barking dog" signal to the primary controller;

[0008] The reset control unit is used to reset the avionics product processor system and monitor the voltage value of the power conversion unit;

[0009] The reset control unit monitors the output voltage of the power conversion unit and sends a reset signal when the power supply is abnormal;

[0010] The first comparison unit collects the output voltage of the electronic product, compares it with the power-off recovery reference, and inputs the comparison result to the power-off control unit;

[0011] The second comparison unit collects the output voltage of the electronic product, compares it with the power-off reference, and inputs the comparison result to the power-off control unit;

[0012] The power-off control unit sends the comparison results of the first comparison unit and the second comparison unit to the reset control unit through the first logic "OR" unit, and judges whether the comparison result of the first comparison unit generates a power-off recovery mark within 20ms, and judges whether the comparison result of the first comparison unit is a power-off recovery. If so, it is regarded as a normal power-off and a reset signal is sent to the electronic product processor; if not, it is an abnormal power-off and a power-off flag signal is sent to the processor;

[0013] The manual reset pin MR# of the reset control unit is connected to the output end of the first logic "OR" unit, and the power supply pin VCC is connected to the output end of the power conversion unit of the power control unit; the reset output pin RESET# is connected to the multi-stage controller and the input pin of the second logic "OR" unit;

[0014] The input pin WDI of the watchdog circuit is connected to the general input and output pin GPIO of the primary controller, and the output pin WDO# is connected to the non-maskable interrupt pin NMI of the primary controller;

[0015] The primary controller is connected to the logic control unit via a load or handshake confirmation signal; the watchdog "dog barking" software set inside the primary controller watches the watchdog test result through the output pin SWRT and is connected to the input end of the first logic "OR" unit;

[0016] The load or handshake confirmation output pin LRST of the primary controller is connected to the input end of the second logic "OR" unit, and the output of the second logic "OR" unit is connected to the reset input pin RSTIN connected to the power control unit and the multi-stage logic control unit respectively;

[0017] The input of the power control unit is connected to the power input, the power failure reference, and the power failure recovery reference respectively; the power failure recovery flag of the power control unit is connected to the input of the first logic "OR" unit;

[0018] The output of the power conversion unit is connected to the power input pin VCC of the reset control unit, and the output of the manual reset signal and the manual reset interlocking signal after logic operation is connected to the input pin of the first logic "OR" unit.

[0019] The technical beneficial effects of the present invention are:

[0020] The multi-level reset source design reduces the coupling of reset sources through a hierarchical design. Power-on reset, software reset, manual reset, external watchdog timeout reset, and power-off recovery reset are all available. Reset timing control enables coordinated reset of multiple reset sources, improving the reliability of reset systems in electronic products. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0022] Figure 1 A functional block diagram of a multi-stage processor reset system;

[0023] Figure 2 Reset system process for multi-level processors;

[0024] Figure 3 This is the working timing diagram of the reset control unit. DETAILED DESCRIPTION

[0025] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0026] The following describes the embodiments of the present disclosure through specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0027] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on this disclosure, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement an apparatus and / or practice a method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this apparatus and / or practice this method.

[0028] like Figure 1 The multi-stage processor reset system shown is suitable for resetting processor systems of avionics products. It is characterized by comprising a primary controller and a reset control unit communicating with the primary controller, a power control unit, and a multi-stage controller (including secondary controller 1, secondary controller 2, ..., secondary controller n, where n is a natural integer). The multi-stage controller is connected to a multi-stage logic control unit and a dedicated controller according to preset criteria. The primary controller is provided with a watchdog circuit. The power control unit comprises a power conversion unit, a first comparison unit 1, a second comparison unit 2, and a power-off control unit. The multi-stage logic control unit comprises logic control unit 1, logic control unit 2, ..., logic control unit n. Specifically,

[0029] The primary controller includes a loading / confirmation module, which is connected to multiple logic control units and a dedicated controller via a second logic OR unit 2;

[0030] A watchdog circuit is configured to send a "feed the dog" signal during a preset time period and is connected to a reset control unit via a first logic "OR" unit 1 and a second logic "OR" unit 2 connected to multiple logic control units;

[0031] The reset control unit is used to reset the processor system of the avionics product and monitor the voltage value of the power conversion unit (power conversion unit). When the voltage value supplied to the reset control unit does not reach the preset value, the processor system is in the reset state. When the voltage value reaches the preset value, it will be in the working state after a preset time interval (200ms).

[0032] Power conversion unit, used for converting secondary power (e.g., 24V to 5V) and supplying power to the processor system;

[0033] The reset control unit monitors the output voltage of the power conversion unit and sends a reset signal when the power supply is abnormal. The reset control unit is implemented by a dedicated reset chip or a single-chip microcomputer. For example, common dedicated reset chips include MAX706, MAX708, MAX791, SM706, SM708, SM791, SM3823 of Guowei Electronics Co., Ltd., etc.

[0034] The first comparison unit 1 collects the output voltage of the electronic product, compares it with the power-off recovery reference, and inputs the comparison result to the power-off control unit;

[0035] The second comparison unit 2 collects the output voltage of the electronic product, compares it with the power-off reference, and inputs the comparison result to the power-off control unit;

[0036] The power-off control unit sends the comparison results of the first comparison unit 1 and the second comparison unit 2 to the reset control unit through the first logic "OR" unit 1. The comparison result of the first comparison unit 1 determines whether a power-off recovery mark is generated within 20ms, and determines whether the comparison result of the first comparison unit 1 is a power-off recovery. If so, it is considered a normal power-off and a reset signal is sent to the electronic product processor. If not, it is an abnormal power-off and a power-off flag signal is sent to the level 1 processing.

[0037] The logic AND unit (the triangle in the figure) is used to receive the manual reset signal and the manual reset interlock signal transmitted by the avionics product, and is connected to the reset control unit through the first logic OR unit 1.

[0038] The reset control unit's manual reset pin MR# is connected to the output of the first logical OR unit 1. The reset control unit's power supply pin VCC is connected to the output of the power conversion unit of the power control unit. The reset control unit's watchdog input pin WDI is connected to the general-purpose input / output pin GPIO of the primary controller. The reset control unit's watchdog output pin WDO# is connected to the primary controller's non-maskable interrupt pin NMI. The reset control unit's reset output pin RESET# is connected to the input pins of the primary controller, secondary controller 1, secondary controller 2, ..., secondary controller n, and the second logical OR unit 2. The primary controller is connected to logical control units 1, 2, ..., n via a load or handshake confirmation signal. The primary controller's internal watchdog bark or software watchdog test result output pin SWRT is connected to the input of the first logical OR unit 1. The primary controller's load or handshake confirmation output pin LRST is connected to the input of the second logical OR unit 2. The output of the second logical OR unit 2 is connected to the reset input pin RSTIN of the power control unit, logic control units 1, 2, ..., n. The inputs of the power control unit are connected to the power input, power failure reference, and power failure recovery reference, respectively. The power failure recovery flag of the power control unit is connected to the input of the first logical OR unit 1. The output of the power conversion unit of the power control unit is connected to the power output pin VCC of the reset control unit. The output of the manual reset signal and the manual reset interlocking signal after logical operation is connected to the input pin of the first logical OR unit 1.

[0039] The multi-level reset source design reduces the coupling of reset sources through a hierarchical design. Power-on reset, software reset, manual reset, external watchdog timeout reset, and power-off recovery reset are all available. Reset timing control enables coordinated reset of multiple reset sources, improving the reliability of reset systems in electronic products.

[0040] Secondly, a multi-level processor reset method is provided. Using the above system, the reset methods include: power-on reset, software reset, manual reset, external watchdog timeout reset and power-off recovery reset. Specifically:

[0041] 1. The working principle of power-on reset is as follows: when the power supply voltage VCC of the reset control unit is lower than the power-on reset threshold, the reset output pin RESET# of the reset control unit outputs a low level, and the reset is valid; when the power supply voltage VCC of the reset control unit is higher than the reset threshold, the reset output signal RESET# remains low for a period of time and then outputs a high level, and the reset is invalid; when the power supply voltage VCC of the reset control unit drops from a stable state to the reset threshold, the reset signal RESET# output is low, and the reset is valid.

[0042] 2. The method or steps for software reset are as follows: when the internal watchdog of the first-level controller barks, the software watchdog is tested, or a software reset instruction from the upper computer is received, the first-level controller sets the output pin SWRT to a low level and sets the output of the first logic "OR" unit 1 to a low level, that is, the manual reset pin MR# of the reset control unit is low, the reset output pin RESET# of the reset control unit is output to a low level, and the reset is valid.

[0043] 3. The method or steps for manual reset are: the manual reset signal is valid and the manual reset interlocking signal is enabled, the output of the first logic "OR" unit 1 is set to a low level, that is, the manual reset pin MR# of the reset control unit is low, the reset output pin RESET# of the reset control unit is output to a low level, and the reset is valid.

[0044] 4. The method or steps for resetting the external watchdog timeout are as follows: when the reset control unit does not receive the watchdog feeding instruction WDI from the first-level controller within the specified period, the reset control unit will generate a watchdog timeout signal WDO#. When the first-level controller detects that WDO# is valid, it enters the non-maskable interrupt NMI. In the interrupt service program, the first-level controller sets the output pin SWRT to a low level, and the reset is valid.

[0045] 5. The method or steps for power-off recovery and reset are as follows: when the supply voltage of the power input is lower than the power-off reference benchmark and exceeds the specified time, when the supply voltage recovers to the power-off recovery reference benchmark, the power-off recovery flag is valid, and the output of the first logic "OR" unit 1 is set to a low level, that is, the manual reset pin MR# of the reset control unit is low, the reset output pin RESET# of the reset control unit is output to a low level, and the reset is valid.

[0046] Furthermore, in a method for powering on and resetting a multi-level logic control unit, after the first-level controller receives the FPGA loading completion or handshake confirmation signal of logic control unit 1, logic control unit 2...logic control unit n and the power control unit, the first-level controller sets the output pin LRST to a low level and the reset is valid.

[0047] Figure 2The multi-stage processor reset system process provided by the present invention includes power-on reset, software reset, manual reset, external watchdog timeout reset, and power-off recovery reset. After the secondary power supply is established, the primary processor, secondary processors 1, ..., and secondary processor n perform a power-on reset. After the primary processor reset is complete, upon receiving the FPGA loading completion or handshake confirmation signal from the logic control unit 1, ..., logic control unit m, and power control unit, the primary controller sets the output pin LRST to a low level, resetting the logic control unit FPGA. When the internal watchdog barks due to a software anomaly in the primary controller, an external watchdog test is performed, and a software reset command is received, the primary controller sets the output pin SWRT to a low level, performing a software reset. When the external watchdog barks due to a software anomaly in the primary controller, the reset control unit generates a watchdog timeout signal WDO#. When the primary controller detects that WDO# is valid, it initiates a non-maskable interrupt (NMI). Within the interrupt service routine, the primary controller sets the output pin SWRT to a low level, resetting the external watchdog timeout. When the power supply voltage of the power input is lower than the power-off reference benchmark and exceeds the specified time, when the power supply voltage recovers to the power-off recovery reference benchmark, the power-off recovery flag is valid, and the output of the first logic OR unit is set to a low level, that is, the manual reset pin MR# of the reset control unit is low, and the reset output pin RESET# of the reset control unit is output to a low level, and power-off recovery reset is performed.

[0048] Figure 3 The following figure shows the operating timing diagram of the reset control unit. The reset control unit's inputs include the power supply voltage VCC, the manual reset signal MR#, and the reset signal WDI. Its outputs include the barking signal WDO# and the reset signal REST#. When the power supply voltage VCC reaches the reset threshold voltage VTH, the reset signal REST# asserts and goes low. It remains low for the power-on reset time, placing the system in reset mode. After the power-on reset time expires, the output goes high. If the reset controller uses a dedicated reset chip such as the MAX791, the reset time is typically 200ms. If the reset controller uses a single-chip microcontroller, the power-on reset time is configurable by the reset controller software. At any time, when the manual reset signal MR# is asserted, the reset signal REST# remains low, placing the system in reset mode. When the primary controller enters normal mode, it sends a periodic reset signal WDI to the reset control unit to prevent software failures. If the reset control unit fails to receive the WDI signal within the reset time, it issues a barking signal WDO#, causing the primary controller to enter its interrupt service routine, log a fault, and initiate a software reset. The barking time of the reset control unit can be realized by software or hardware. The barking time is generally 2-5 times of the dog feeding time.

[0049] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A multi-stage processor reset system suitable for resetting the processor system of avionics products, characterized by: The system includes a primary controller and a reset control unit, a power control unit, and a multi-level controller communicating with the primary controller. The multi-level controller is connected to a multi-level logic control unit and a dedicated controller according to preset criteria. The reset control unit is provided with a watchdog circuit. The power control unit includes a power conversion unit, a first comparison unit, a second comparison unit, and a power-off control unit, including: The primary controller includes a loading / confirmation module, which is connected to multiple logic control units and a dedicated controller via a second logic "OR" unit; The watchdog circuit is used to receive a "feed the dog" signal sent by the primary controller during a preset time period, and to indicate a dog feeding timeout by sending a "barking dog" signal to the primary controller; The reset control unit is used to reset the avionics product processor system and monitor the voltage value of the power conversion unit; The power conversion unit is used for converting the secondary power supply and supplying power to the processor system; The reset control unit monitors the output voltage of the power conversion unit and sends a reset signal when the power supply is abnormal; The first comparison unit collects the output voltage of the electronic product, compares it with the power-off recovery reference, and inputs the comparison result to the power-off control unit; The second comparison unit collects the output voltage of the electronic product, compares it with the power-off reference, and inputs the comparison result to the power-off control unit; The power-off control unit sends the comparison results of the first comparison unit and the second comparison unit to the reset control unit through a first logical "OR" unit. The comparison result of the first comparison unit is used to determine whether a power-off recovery mark is generated within 20ms, and whether the comparison result of the first comparison unit is a power-off recovery. If so, it is considered a normal power-off and a reset signal is sent to the electronic product processor. If not, it is an abnormal power-off and a power-off flag signal is sent to the processor. The manual reset pin MR# of the reset control unit is connected to the output end of the first logic "OR" unit, and the power supply pin VCC is connected to the output end of the power conversion unit of the power control unit; the reset output pin RESET# is connected to the multi-stage controller and the input pin of the second logic "OR" unit; The input pin WDI of the watchdog circuit is connected to the general input and output pin GPIO of the primary controller, and the output pin WDO# is connected to the non-maskable interrupt pin NMI of the primary controller; The primary controller is connected to the logic control unit via a load or handshake confirmation signal; the watchdog barks or software set inside the primary controller outputs the watchdog test result through the output pin SWRT and connects it to the input end of the first logic "OR" unit; The load or handshake confirmation output pin LRST of the primary controller is connected to the input end of the second logic "OR" unit, and the output of the second logic "OR" unit is connected to the reset input pin RSTIN connected to the power control unit and the multi-stage logic control unit respectively; The input of the power control unit is connected to the power input, the power failure reference, and the power failure recovery reference respectively; the power failure recovery flag of the power control unit is connected to the input of the first logic "OR" unit; The output of the power conversion unit is connected to the power input pin VCC of the reset control unit, and the output of the manual reset signal and the manual reset chain signal after logical operation is connected to the input pin of the first logic "OR" unit.

2. The multi-level processor reset system according to claim 1, characterized in that ,The reset control unit is implemented by a dedicated reset chip or a single-chip microcomputer.

3. A multi-stage processor reset method, characterized in that: Using the multi-level processor reset system as claimed in claim 1, the reset methods include power-on reset, software reset, manual reset, external watchdog timeout reset and power-off recovery reset.

4. The multi-stage processor reset method according to claim 3, wherein: The method of the power-on reset operation is: When the power supply voltage VCC of the reset control unit is lower than the power-on reset threshold, the reset output pin RESET# of the reset control unit outputs a low level and the reset is valid; When the power supply voltage VCC of the reset control unit is higher than the reset threshold, the reset output signal is output at a high level after maintaining a low level for a preset time through the reset output pin RESET#, and the reset is invalid; When the power supply voltage VCC of the reset control unit drops from a stable state to a reset threshold, the reset signal is output as a low level through the reset output pin RESET#, and the reset is valid.

5. The multi-stage processor reset method according to claim 4, characterized in that: The method of software reset is: When the internal watchdog of the first-level controller "barks", the software watchdog test is performed, or a reset instruction from the upper computer software is received, the first-level controller sets the output pin SWRT to a low level and sets the output of the first logical "OR" unit to a low level, that is, the manual reset pin MR# of the reset control unit is low, and the reset output pin RESET# of the reset control unit is output at a low level, and the reset is valid.

6. The multi-stage processor reset method according to claim 5, characterized in that: The manual reset method is: The manual reset signal is valid and the manual reset interlocking signal is enabled, causing the first logic "OR" unit to output a low level, that is, the manual reset pin MR# of the reset control unit is low, the reset output pin RESET# of the reset control unit is output at a low level, and the reset is valid.

7. The multi-stage processor reset method according to claim 6, characterized in that: The method of resetting the external watchdog timeout is: When the reset control unit does not receive the watchdog feeding instruction WDI from the first-level controller within the specified period, the reset control unit will generate a watchdog timeout signal WDO#. When the first-level controller detects that WDO# is valid, it enters the non-maskable interrupt NMI. In the interrupt service program, the first-level controller sets the output pin SWRT to a low level, and the reset is valid.

8. The multi-stage processor reset method according to claim 7, wherein: The power-off recovery and reset method is as follows: When the supply voltage of the power input is lower than the power-off reference benchmark and exceeds the specified time, and the supply voltage recovers to the power-off recovery reference benchmark, the power-off recovery flag is valid, causing the first logic "OR" unit to output a low level, that is, the manual reset pin MR# of the reset control unit is low, and the reset output pin RESET# of the reset control unit is output at a low level, and the reset is valid.

9. The multi-stage processor reset method according to claim 8, characterized in that: After the primary controller completes the power-on reset and receives the loading completion or handshake confirmation signal from the multi-level logic control unit and the power control unit, the primary controller sets the output pin LRST to reset valid once.

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