Voltage conversion circuit and memory

Abstract

The present disclosure provides a voltage conversion circuit and a memory. The voltage conversion circuit includes: a driving circuit powered by a first voltage, with an output terminal outputting a first signal, the voltage of the high level of the first signal being less than the first voltage; a receiving circuit powered by the first voltage, a first input terminal receiving the first signal, and a second input terminal receiving a sampling signal, for outputting a second signal according to the sampling signal, the voltage of the high level of the second signal being equal to the first voltage. The voltage conversion circuit of the embodiments of the present disclosure has lower power and a smaller occupied area of components.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuits, and in particular, to a voltage conversion circuit and a memory applying the voltage conversion circuit. Background Art

[0002] In certain application scenarios of a memory, a level conversion unit is required to convert a signal with a relatively small level value into a signal with a relatively large level value, or convert a signal with a relatively large level value into a signal with a relatively small level value. As the requirements for power consumption, speed, and area of the memory become higher and higher, the existing level conversion circuits also need to continuously optimize power consumption, speed, and area.

[0003] Therefore, a voltage conversion circuit that can balance low power consumption and small component footprint is needed.

[0004] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0005] The purpose of the present disclosure is to provide a voltage conversion circuit and a memory applying the voltage conversion circuit, which are used to overcome, at least to a certain extent, the limitations and defects of the related art.

[0006] According to a first aspect of the present disclosure, a voltage conversion circuit is provided, including: a driving circuit powered by a first voltage, with an output terminal outputting a first signal, and the voltage of the high level of the first signal being less than the first voltage; a receiving circuit powered by the first voltage, with a first input terminal receiving the first signal and a second input terminal receiving a sampling signal, and being configured to output a second signal according to the sampling signal, and the voltage of the high level of the second signal being equal to the first voltage.

[0007] In an exemplary embodiment of the present disclosure, the receiving circuit includes: a first P-type transistor, with its gate connected to the first input terminal and its source connected to the first voltage; a second P-type transistor, with its gate electrically connected to the second input terminal through a first inverter and its source connected to the drain of the first P-type transistor; a first N-type transistor, with its gate connected to the first input terminal and its source grounded; a second N-type transistor, with its gate electrically connected to the second input terminal and its source connected to the drain of the first N-type transistor, and its drain connected to the drain of the second P-type transistor; the drain of the second N-type transistor is the output terminal of the receiving circuit.

[0008] In an exemplary embodiment of the present disclosure, the voltage conversion circuit further includes: a latching circuit, with its input terminal receiving the second signal and being configured to latch the second signal.

[0009] In an exemplary embodiment of the present disclosure, the latch circuit includes: a second inverter, an input end of the second inverter is connected to an output end of the receiving circuit, and an output end of the second inverter is connected to an output end of the latch circuit; a third inverter, an input end of the third inverter is connected to the output end of the latch circuit, and an output end of the third inverter is connected to the input end of the second inverter.

[0010] In an exemplary embodiment of the present disclosure, when the sampling signal is in an enabled state, the third inverter is in a closed state.

[0011] In an exemplary embodiment of the present disclosure, the enabling level of the sampling signal appears within a preset time when the first signal changes in level.

[0012] In an exemplary embodiment of the present disclosure, the maintaining time of the enabling level of the sampling signal is less than half of the high-level time in the first signal.

[0013] In an exemplary embodiment of the present disclosure, the sampling signal is a pulse signal with a set period.

[0014] In an exemplary embodiment of the present disclosure, the duty cycle of the enabling level in the sampling signal is less than 1 / 2.

[0015] In an exemplary embodiment of the present disclosure, the value of the high level of the first signal enables the pulling-up ability of the first P-type transistor to be greater than the pulling-down ability of the first N-type transistor.

[0016] In an exemplary embodiment of the present disclosure, the difference between the first voltage and the high level of the first signal is less than or equal to the threshold voltage of the first P-type transistor.

[0017] In an exemplary embodiment of the present disclosure, the driving circuit includes: a third N-type transistor and a fourth N-type transistor, a drain of the third N-type transistor is connected to the first voltage, a source of the third N-type transistor is connected to a drain of the fourth N-type transistor, a source of the fourth N-type transistor is grounded, and a drain of the fourth N-type transistor serves as an output end of the driving circuit.

[0018] In an exemplary embodiment of the present disclosure, a gate of the third N-type transistor receives a first control signal, a gate of the fourth N-type transistor receives a second control signal, and the first control signal and the second control signal are opposite in phase.

[0019] In an exemplary embodiment of the present disclosure, the size of the third N-type transistor is the same as the size of the fourth N-type transistor.

[0020] According to a second aspect of the present disclosure, a memory is provided, comprising the voltage conversion circuit as described in any one of the above items.

[0021] The disclosed embodiments use an N-type transistor powered by a first voltage to output a first signal, and use a receiving circuit to convert the first signal to generate a second signal with a high-level voltage equal to the first voltage, thereby reducing the overall power consumption of the circuit when outputting the second signal. Furthermore, by using a sampling signal in the receiving circuit to sample the lower-voltage first signal and then output the second signal, the lower-voltage first signal can be converted to a higher-voltage output signal using fewer components, reducing the area occupied by the components and the power consumption during the voltage conversion process.

[0022] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0024] Figure 1 Schematic diagram of a voltage conversion circuit in an exemplary embodiment of the present disclosure.

[0025] Figure 2 FIG. 2 is a circuit diagram of a receiving circuit 2 in an embodiment of the present disclosure.

[0026] Figure 3 yes Figure 2 The timing control diagram of the receiving circuit 2 in the embodiment shown is shown.

[0027] Figures 4A to 4D yes Figure 3 Under the timing control shown Figure 2 The equivalent circuit diagram of the receiving circuit 2 is shown.

[0028] Figure 5 FIG. 4 is a circuit diagram of the latch circuit 3 in one embodiment of the present disclosure.

[0029] Figures 6A to 6D yes Figure 5 The circuit of the embodiment shown is Figure 3 Schematic diagram of the equivalent circuit under the shown timing.

[0030] Figure 7 is a circuit diagram of a driving circuit in one embodiment of the present disclosure.

[0031] Figure 8 It is a schematic diagram of the overall circuit of the voltage conversion circuit in an embodiment of the present disclosure. Detailed implementation manners

[0032] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be more complete and comprehensive, and will fully convey the concept of the example embodiments to those skilled in the art. The features, structures, or characteristics described may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of the embodiments of the present disclosure. However, those skilled in the art will realize that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or may be implemented using other methods, components, devices, steps, etc. In other cases, well-known technical solutions are not shown or described in detail to avoid obscuring the various aspects of the present disclosure.

[0033] In addition, the accompanying drawings are only schematic illustrations of the present disclosure, and the same reference numerals in the drawings denote the same or similar parts, so repeated descriptions thereof will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0034] The example embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0035] Figure 1 It is a schematic structural diagram of the voltage conversion circuit in an exemplary embodiment of the present disclosure.

[0036] Referring to Figure 1 , the voltage conversion circuit 100 may include:

[0037] A driving circuit 1, powered by a first voltage Vcc, outputs a first signal S1 at its output terminal, and the voltage of the high level of the first signal S1 is less than the first voltage Vcc;

[0038] A receiving circuit 2, powered by the first voltage Vcc, receives the first signal S1 at its first input terminal IN1 and receives a sampling signal Ss at its second input terminal IN2, and is configured to output a second signal S2 according to the sampling signal Ss, and the voltage of the high level of the second signal S2 is equal to the first voltage Vcc.

[0039] Figure 2 It is a circuit diagram of the receiving circuit 2 in an embodiment of the present disclosure.

[0040] Reference Figure 2 , in one embodiment, the receiving circuit 2 may include:

[0041] A first P-type transistor M1, with its gate connected to the first input terminal IN1 and its source connected to the first voltage Vcc;

[0042] A second P-type transistor M2, with its gate electrically connected to the second input terminal IN2 through a first inverter OP1 and its source connected to the drain of the first P-type transistor M1;

[0043] A first N-type transistor M3, with its gate connected to the first input terminal IN1 and its source grounded;

[0044] A second N-type transistor M4, with its gate electrically connected to the second input terminal IN2, its source connected to the drain of the first N-type transistor M3, and its drain connected to the drain of the second P-type transistor M2; the drain of the second N-type transistor M4 is the output terminal OUT1 of the receiving circuit.

[0045] Due to its simple structure, the receiving circuit 2 provided by the embodiments of the present disclosure can be implemented with fewer components, greatly reducing the component occupation area and power consumption of the voltage conversion function.

[0046] In the embodiments of the present disclosure, the receiving circuit 2 operates under the first voltage Vcc. Therefore, the conversion signal (not shown, output through the drains of the above two transistors) generated by the first P-type transistor M1 and the first N-type transistor M3 according to the first signal S1 is a signal under the first voltage Vcc. By sampling this conversion signal through the second P-type transistor M2 and the second N-type transistor M4, a second signal S2 with a high level of the first voltage Vcc can be output, realizing the voltage boost of the first signal S1.

[0047] In one embodiment of the present disclosure, the enabling level of the sampling signal Ss may appear within a preset time when the level of the first signal S1 changes, that is, the sampling signal Ss can be triggered by the polarity change of the first signal S1, so that the timing of the second signal S2 is consistent with that of the first signal S1.

[0048] In another embodiment of the present disclosure, the sampling signal Ss may also be a pulsed signal with a set period, thereby converting the non-periodic first signal S1 into a periodic second signal S2, making the timing of the signal easier to control. Different timings of the first signal S1 can form a signal group with the same timing through the processing of the sampling signal, which is more conducive to the use of subsequent circuits.

[0049] In one embodiment, the enabling level of the sampling signal Ss is a high level, and this high level is equal to the first voltage Vcc. At this time, the gate of the second P-type transistor M2 is connected to the second input terminal IN2 through the first inverter OP1 (asFigure 2 As shown, the gate of the second N-type transistor M4 is connected to the second input terminal IN2. In another embodiment, the enable level of the sampling signal Ss is a low level, and this low level can be zero potential. At this time, the gate of the second P-type transistor M2 is connected to the second input terminal IN2 (not shown), and the gate of the second N-type transistor M4 is connected to the second input terminal IN2 through the first inverter OP1.

[0050] Next, the operating principle of the receiving circuit 2 of the illustrated embodiment will be described through the control timing. Figure 2 The operating principle of the receiving circuit 2 of the illustrated embodiment.

[0051] Figure 3 is Figure 2 The timing control diagram of the receiving circuit 2 in the illustrated embodiment.

[0052] In Figure 3 In the illustrated embodiment, the first signal S1 is a periodic signal, and the sampling signal Ss is also a periodic signal. The sampling signal Ss appears within a preset time when the first signal S1 undergoes a level change. The second signal S2 changes its level with the appearance of the sampling signal Ss. At this time, the level change range of the first signal S1 is from the second voltage Vcc_Low to zero potential (the second voltage Vcc_Low is less than the first voltage Vcc), and the level change ranges of the inverted signal Ss of the sampling signal Ss after passing through the first inverter OP1 and the second signal S2 are both from the first voltage Vcc to zero potential.

[0053] Figures 4A to 4D is Figure 3 Under the timing control shown Figure 2 The equivalent circuit schematic diagram of the receiving circuit 2 shown.

[0054] Referring to Figure 4A , when the first signal S1 is at a low level and the sampling signal Ss is at a high level, the first P-type transistor M1, the second P-type transistor M2, and the second N-type transistor M #4 are turned on, and the first N-type transistor M3 is turned off. At this time, the first voltage Vcc is output to the output terminal OUT1 through the first P-type transistor M1 and the second P-type transistor M2, generating a current I1, making the second signal S2 be Vcc, that is, a high level.

[0055] Referring to Figure 4B, when the first signal S1 is at a high level and the sampling signal Ss is at a high level, the second P-type transistor M2, the first N-type transistor M3, and the second N-type transistor M4 are turned on, and the first P-type transistor M1 is turned off (or at least the pulling-up ability of M1 is less than the pulling-down ability of M3). At this time, the output terminal OUT1 is grounded through the first N-type transistor M3 and the second N-type transistor M4, generating a discharge current I2, making the second signal S2 equal to 0, that is, a low level. It can be understood that since the high level of the first signal S1 is Vcc_Low, and Vcc_Low is less than Vcc (for example, Vcc_Low is 0.5V and Vcc is 1.2V), the first P-type transistor M1 may not be completely turned off, and there will be a certain charging current I3. The charging current I3 is from Vcc to the output terminal OUT1, and the discharge current I2 is from the output terminal OUT1 to the ground terminal.

[0056] In order to make the charging current I3 much smaller than the discharge current I2, so that the second signal S2 at the output terminal OUT1 reaches 0V, in the embodiments of the present disclosure, the value of the second voltage Vcc_Low needs to make the pulling-up ability of the first P-type transistor M1 less than the pulling-down ability of the first N-type transistor M3. In an exemplary embodiment of the present disclosure, the difference between the first voltage Vcc and the second voltage Vcc_Low can be less than or equal to the threshold voltage Vp1 of the first P-type transistor M1, and the value of Vp1 can be 0.5V, for example.

[0057] From Figure 4A and Figure 4B As can be seen from the illustrated embodiments, the receiving circuit 2 can convert the first signal S1 with a relatively low voltage change range (Vcc_Low~0) into the second signal S2 with a relatively high voltage change range (Vcc~0), and the phase of the second signal S2 is opposite to that of the first signal S1.

[0058] If it is necessary to set the phase of the second signal S2 to be the same as that of the first signal S1, an inverter can be connected to the output terminal OUT1, which is not elaborated herein in the present disclosure.

[0059] Referring to Figure 4C and Figure 4D , when the sampling signal Ss is at a low level, regardless of what kind of signal the first signal S1 is, there is no signal change at the output terminal OUT1. In order to make the phase of the second signal S2 at the output terminal OUT1 the same as that of the first signal S1, one way is to control the sampling signal Ss to be always at a high level. At this time, the second P-type transistor M2 and the second N-type transistor M4 can also be removed, but this way will continuously generate a charging current I3 to the ground when the first signal S1 is at a high level, resulting in an increase in circuit power consumption. Another way is to connect a latch after the output terminal OUT1 so that the output signal of the entire circuit can still remain unchanged when the sampling signal Ss is at a low level.

[0060] Figure 5 It is the circuit diagram of the latch circuit in another embodiment of the present disclosure.

[0061] Referring to Figure 5 , in another embodiment of the present disclosure, the voltage conversion circuit further includes a latch circuit 3. The input end of the latch circuit 3 receives the second signal S2 and is used to latch the second signal S2. As Figure 5 shown, in one embodiment, the latch circuit 3 may include:

[0062] A second inverter OP2. The input end of the second inverter OP2 is connected to the output end OUT1 of the receiving circuit 2, and the output end of the second inverter OP2 is connected to the output end OUT2 of the latch circuit 3;

[0063] A third inverter OP3. The input end of the third inverter OP3 is connected to the output end OUT2 of the latch circuit 3, and the output end of the third inverter OP3 is connected to the input end of the second inverter OP2.

[0064] In Figure 5 the shown embodiment, both the second inverter OP2 and the third inverter OP3 are connected to the first voltage Vcc, which is not shown in the figure.

[0065] Figures 6A to 6D It is Figure 5 the equivalent circuit schematic diagram of the circuit shown in Figure 3 the shown timing.

[0066] Referring to Figure 6A , when the first signal S1 is at a low level and the sampling signal Ss is at a high level, the first P-type transistor M1, the second P-type transistor M2, and the second N-type transistor M4 are turned on, and the first N-type transistor M3 is turned off (or at least the pulling-up ability of M1 is less than the pulling-down ability of M3). At this time, the first voltage Vcc is output to the output end OUT1 of the receiving circuit 2 through the first P-type transistor M1 and the second P-type transistor M2, generating a current I1, making the second signal S2 be Vcc, that is, a high level.

[0067] The second signal S2 enters the second inverter OP2 and outputs a low-level third signal S3 through the output end OUT2. The phase of the third signal S3 is synchronized with the phase of the sampling signal Ss. The third signal S3 output from the output end OUT2 returns to the output end OUT1 through the third inverter OP3 and is still at a high level. Since it is not necessary for the third inverter OP3 to work to maintain the voltage of the second signal S2 at this time, in order to reduce power consumption, the third inverter OP3 can be controlled to be in an off state in this state.

[0068] Referring to Figure 6B, when the first signal S1 is at a high level and the sampling signal Ss is at a high level, the second P-type transistor M2, the first N-type transistor M3, and the second N-type transistor M4 are turned on, and the first P-type transistor M1 is turned off. At this time, the drain of the second N-type transistor M4 is grounded through the first N-type transistor M3 and the second N-type transistor M4, generating a discharge current I2, making the second signal S2 equal to 0, that is, a low level. It can be understood that since the high level of the first signal S1 is Vcc_Low, the first P-type transistor M1 will not be completely turned off, and there will be a certain charging current I3.

[0069] The second signal S2 passes through the second inverter OP2 and outputs a high-level third signal S3 through the output terminal OUT2. The phase of the third signal S3 is synchronized with the phase of the sampling signal Ss. The third signal S3 returns to the output terminal OUT1 through the third inverter OP3 and is still at a low level. Since there is no need for the third inverter OP3 to work to maintain the voltage of the third signal S3 at this time, in order to reduce power consumption, the third inverter OP3 can be controlled to be in a closed state in this state. That is, when the sampling signal Ss is in an enabled state, the third inverter OP3 can be set to a closed state.

[0070] Reference Figure 6C , when the sampling signal Ss is at a low level, regardless of what kind of signal the first signal S1 is, there is no signal change at the output terminal OUT1. Before this state is formed, that is, before controlling the sampling signal Ss to be at a low level, the third inverter OP3 can be enabled to form a feedback path between the output terminal OUT1 and the output terminal OUT2. Since both the second inverter OP2 and the third inverter OP3 are active devices, the latch circuit 3 can maintain the voltage of the output terminal OUT1 when working, and thus maintain the voltage of the output terminal OUT2 unchanged. Figure 6D The same applies to the embodiments shown, and the present disclosure will not be elaborated herein.

[0071] Since a charging current I3 will be generated when the sampling signal Ss is in an enabled state and the first signal S1 is at a high level, increasing power consumption, when using the latch circuit 3 to maintain the output signal unchanged, the enabled state maintenance time of the sampling signal Ss can be reduced as much as possible to reduce the circuit power consumption.

[0072] In an embodiment of the present disclosure, when the enabled level of the sampling signal Ss appears within a preset time when the level of the first signal S1 changes, the maintenance time of the enabled level of the sampling signal Ss can be, for example, less than half of the high-level time in the first signal S1.

[0073] In another embodiment of the present disclosure, when the sampling signal Ss is a pulse signal with a set period, the duty cycle of the enable level in the sampling signal Ss can be less than 1 / 2, for example. To further reduce power consumption, the duty cycle of the sampling signal Ss can be even lower, for example, less than 1 / 4, less than 1 / 10, or less than 1 / 20.

[0074] The above values are only examples. In practical applications, those skilled in the art can set the maintenance time of the enable level of the sampling signal Ss according to the actual situation.

[0075] In addition, by reducing the sizes of the second P-type transistor M2 and the second N-type transistor M4, the charging current I3 can also be reduced.

[0076] Figure 7 is the circuit diagram of the driving circuit in an embodiment of the present disclosure.

[0077] Reference Figure 7 , in an embodiment of the present disclosure, the driving circuit 1 may include:

[0078] A third N-type transistor M5 and a fourth N-type transistor M6. The drain of the third N-type transistor M5 is connected to the first voltage Vcc. The source of the third N-type transistor M5 is connected to the drain of the fourth N-type transistor M6. The source of the fourth N-type transistor M6 is grounded. The drain of the fourth N-type transistor M6 serves as the output terminal of the driving circuit 1 and is connected to the first input terminal IN1 of the receiving circuit 2. In an exemplary embodiment of the present disclosure, the size of the third N-type transistor M5 is the same as that of the fourth N-type transistor M6.

[0079] In an exemplary embodiment of the present disclosure, the gate of the third N-type transistor M5 can receive a first control signal CON1, and the gate of the fourth N-type transistor M6 receives a second control signal CON2. The phases of the first control signal CON1 and the second control signal CON2 are opposite.

[0080] In Figure 7In the illustrated embodiment, both the first control signal CON1 and the second control signal CON2 are generated from the control signal output through the control port CON. A fourth inverter OP4 and a fifth inverter OP5 are provided between the control port CON and the gate of the third N-type transistor M5, and a sixth inverter OP6 is provided between the control port CON and the gate of the fourth N-type transistor M6, to ensure that the first control signal CON1 and the second control signal CON2 are inverted with respect to each other. In some other embodiments, an inverter may also be provided between the control port CON and the gate of the third N-type transistor M5, and two inverters may be provided between the control port CON and the gate of the fourth N-type transistor M6, to achieve the same purpose. Alternatively, in other embodiments of the present disclosure, the complete inversion of the first control signal CON1 and the second control signal CON2 may also be achieved by other means, and the present disclosure places no special restrictions thereon.

[0081] Figure 7 In the illustrated drive circuit 1, when the control signal at the control port CON is at a high level, the third N-type transistor M5 is turned on and the fourth N-type transistor M6 is turned off, and the voltage Vcc - VthN can be output through the source of the third N-type transistor M5, where VthN is the threshold voltage of the third N-type transistor M5 and is greater than zero. When the control signal at the control port CON is at a low level, the third N-type transistor M5 is turned off and the fourth N-type transistor M6 is turned on, and a low voltage (zero potential) can be output through the drain of the fourth N-type transistor M6. Further, the drive circuit 1 can output a first signal S1 with a high level of Vcc - VthN and a low level of zero potential according to the change of the control signal at the control port CON.

[0082] Compared with outputting a high level through a CMOS structure in the related art, Figure 7 in the illustrated embodiment, a high level is output through an NMOS (i.e., the pull-up transistor is changed from a PMOS to an NMOS), which can reduce the overall power consumption of the circuit.

[0083] Figure 8 is a schematic diagram of the overall circuit of the voltage conversion circuit in an embodiment of the present disclosure.

[0084] Referring to Figure 8 , since the drive circuit 1 outputs a high level through an N-type transistor, the overall power consumption of the drive circuit 1 can be reduced, and the output high level is less than the first voltage Vcc. In the embodiment of the present disclosure, a receiving circuit 2 as shown in Figure 2 or Figure 5 is connected after the drive circuit 1, and a second signal S2 with a high level of Vcc and a low level of zero potential can be generated according to the first signal S1.

[0085] In Figure 8In the illustrated circuit embodiment, it is possible to set the sampling signal Ss to output a sampling level in an enabling state after a preset time when the control signal CON0 input at the control port CON undergoes a level transition, and the duration of this sampling level is as short as possible. In this way, the first signal S1 generated according to the first control signal CON1 and the second control signal CON2 can be sampled by the sampling signal Ss, so as to output a third signal S3 at the output terminal OUT2, which has a fixed delay in phase with the control signal CON0, the same level direction, a high level of Vcc, and a low level of zero volts.

[0086] Since the receiving circuit 2 has a simple structure and low power consumption. Compared with the related art, the voltage conversion circuit provided by the embodiments of the present disclosure can output a signal with a high level of Vcc and a low level of zero potential through a simple structure and low power consumption, and greatly reduces the component occupation area of the voltage conversion circuit and shrinks the component volume.

[0087] According to the second aspect of the present disclosure, a memory is provided, including the voltage conversion circuit shown in any of the above embodiments. As can be seen from the above description, the memory provided with the voltage conversion circuit provided by the embodiments of the present disclosure can have low power consumption and a small component occupation area, and details thereof are not repeated herein.

[0088] It should be noted that although several modules or units of a device for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of the two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units. [[ID=X]]

[0089] Those skilled in the art will readily think of other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure, which follow the general principles of the present disclosure and include known common knowledge or conventional technical means in the technical field not disclosed by the present disclosure. The specification and embodiments are only regarded as exemplary, and the true scope and concept of the present disclosure are pointed out by the claims.

Claims

1. A voltage conversion circuit, characterized in that, Comprising: A driving circuit, powered by a first voltage, with its output terminal outputting a first signal, and the voltage of the high level of the first signal being less than the first voltage; A receiving circuit, powered by the first voltage, with its first input terminal receiving the first signal and its second input terminal receiving a sampling signal, and being configured to output a second signal according to the sampling signal, and the voltage of the high level of the second signal being equal to the first voltage; The receiving circuit includes: A first P-type transistor, with its gate connected to the first input terminal and its source connected to the first voltage; A second P-type transistor, with its gate electrically connected to the second input terminal through a first inverter and its source connected to the drain of the first P-type transistor; A first N-type transistor, with its gate connected to the first input terminal and its source grounded; A second N-type transistor, with its gate electrically connected to the second input terminal, its source connected to the drain of the first N-type transistor, and its drain connected to the drain of the second P-type transistor; The drain of the second N-type transistor is the output terminal of the receiving circuit.

2. The voltage conversion circuit according to claim 1, wherein Further comprising: A latching circuit, with its input terminal receiving the second signal and being configured to latch the second signal.

3. The voltage conversion circuit according to claim 2, characterized in that The latching circuit includes: A second inverter, with its input terminal connected to the output terminal of the receiving circuit and its output terminal connected to the output terminal of the latching circuit; A third inverter, with its input terminal connected to the output terminal of the latching circuit and its output terminal connected to the input terminal of the second inverter.

4. The voltage conversion circuit according to claim 3, wherein, When the sampling signal is in the enabled state, the third inverter is in the off state.

5. The voltage conversion circuit according to any one of claims 1 to 4, characterized in that, The enabling level of the sampling signal appears within a preset time when the level of the first signal changes.

6. The voltage conversion circuit according to claim 5, wherein The maintaining time of the enabling level of the sampling signal is less than half of the high-level time in the first signal.

7. The voltage conversion circuit according to any one of claims 1 to 4, characterized in that The sampling signal is a pulse signal with a set period.

8. The voltage conversion circuit according to claim 7, wherein, The duty cycle of the enabling level in the sampling signal is less than 1 / 2.

9. The voltage conversion circuit according to claim 1, characterized in that, The value of the high level of the first signal makes the pulling-up ability of the first P-type transistor less than the pulling-down ability of the first N-type transistor.

10. The voltage conversion circuit according to claim 1, wherein The difference between the first voltage and the high level of the first signal is less than or equal to the threshold voltage of the first P-type transistor.

11. The voltage conversion circuit according to claim 1, characterized in that, The driving circuit includes: A third N-type transistor and a fourth N-type transistor, with the drain of the third N-type transistor connected to the first voltage, the source of the third N-type transistor connected to the drain of the fourth N-type transistor, the source of the fourth N-type transistor grounded, and the drain of the fourth N-type transistor being the output terminal of the driving circuit.

12. The voltage conversion circuit according to claim 11, wherein The gate of the third N-type transistor receives a first control signal, the gate of the fourth N-type transistor receives a second control signal, and the first control signal and the second control signal have opposite phases.

13. The voltage conversion circuit according to claim 12, wherein, The size of the third N-type transistor is the same as the size of the fourth N-type transistor.

14. A memory, characterized in that, Including the voltage conversion circuit according to any one of claims 1 to 13.

Images