Power supply circuit and memory

Abstract

An embodiment of the present invention provides a power supply circuit and a memory. The power supply circuit includes: a voltage source and a plurality of power supply modules connected to the voltage source. If the voltage source is valid and the power supply module is in an enabled state, the voltage at the power supply terminal is raised to a preset voltage, and power is supplied to the load unit during the raising process; the first type of power supply module enters the enabled state if it receives a first enable signal, and the second type of power supply module enters the enabled state if it receives a second enable signal; a control module, configured to receive a flag signal and, if in a valid state, send a first enable signal, where the valid state indicates that the voltage source is valid; and is further configured to receive a plurality of external signals after sending the first enable signal, each of the external signals corresponding to one of the second type of power supply modules, and the start times of different external signals are different. If the flag signal and an external signal are received, a corresponding second enable signal is sent. The embodiment of the present invention is beneficial to ensuring the effective startup of the chip connected to the power supply terminal.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductors, and in particular, to a power supply circuit and a memory. Background Art

[0002] Multiple internal power supplies for different purposes are generated inside a Dynamic Random Access Memory (DRAM) chip. These internal power supplies are generated by boosting or bucking an externally input voltage (such as VDD / VPPEX). For example, a high voltage higher than VPPEX and a negative voltage can be generated through a charge pump, and various voltages lower than VDD or VPPEX can be generated through a low dropout regulator (LDO). The stability of the externally input voltage is the basis for normal chip startup. Summary of the Invention

[0003] Embodiments of the present invention provide a power supply circuit and a memory, which are beneficial to ensuring the effective startup of a functional circuit connected to a power supply terminal.

[0004] To solve the above problems, an embodiment of the present invention provides a power supply circuit, including: a voltage source and a multi-path power supply module connected to the voltage source. The power supply module has a power supply terminal and a load unit. If the voltage source is effective and the power supply module is in an enabled state, the power supply module raises the voltage of the power supply terminal to a preset voltage and supplies power to the load unit during the raising process; the power supply module includes a first type of power supply module and a second type of power supply module. The first type of power supply module is used to receive a first enable signal and enter the enabled state if the first enable signal is received. The second type of power supply module is used to receive a second enable signal and enter the enabled state if the second enable signal is received; a control module, configured to receive a flag signal and send the first enable signal to the first type of power supply module if the received flag signal is in an effective state, where the effective state indicates that the voltage source is effective; and further configured to receive a plurality of external signals after sending the first enable signal. Each external signal corresponds to one second type of power supply module, and the start times of different external signals are different. If the flag signal and the external signal are received, the second enable signal is sent to the corresponding second type of power supply module.

[0005] Correspondingly, an embodiment of the present invention further provides a memory including the power supply circuit of any one of the above.

[0006] Compared with the prior art, the technical solution provided by the embodiment of the present invention has the following advantages:

[0007] In the above technical solution, since the second enable signal is generated based on the flag signal and the external signal, by receiving a plurality of external signals after sending the first enable signal, the time-sharing startup of the first type of power supply module and the second type of power supply module can be realized. At the same time, since each external signal corresponds to a second type of power supply module, by controlling the starting moments of different external signals to be different, the time-sharing startup of different second type of power supply modules can be realized. In this way, it is beneficial to reduce the number of power supply modules started at the same moment, avoid the excessive overshoot current generated by starting simultaneously from pulling down the voltage of the voltage source, thereby ensuring that the voltage at the power supply end meets the requirements and ensuring the normal startup of the functional circuit connected to the power supply end. At the same time, if the time-sharing startup of the power supply module is controlled by an external signal, there is no need to set up a dedicated delay circuit, which is beneficial to saving chip area.

[0008] In addition, since the anti-fuse scan circuit is provided inside the DRAM chip, by directly using the anti-fuse address signal obtained by scanning the anti-fuse scan circuit as the external signal, there is no need to set up an additional module for generating or receiving the external signal, which is beneficial to saving chip area.

[0009] The details of one or more embodiments of the present application are set forth in the accompanying drawings and the description below. Other features and advantages of the present application will become apparent from the specification, the drawings, and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] One or more embodiments are illustrated by way of example in the accompanying drawings, which illustrations do not constitute a limitation of the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, unless otherwise stated, and the figures in the drawings do not constitute a proportional limitation. In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0011] Figure 1 is a schematic structural diagram of a power supply module;

[0012] Figure 2 and Figure 4 is a timing diagram of the power supply circuit operation provided by an embodiment of the present invention;

[0013] Figure 3 and Figure 6 is a schematic structural diagram of a power supply circuit provided by an embodiment of the present invention;

[0014] Figure 5 is Figure 3 a schematic structural diagram of the second enable unit in the power supply circuit shown;

[0015] Figure 7 Schematic diagram of the structure of the memory provided by the embodiment of the present invention. Specific embodiments

[0016] Whether it is a charge pump or an LDO, the load unit needs to be charged during startup, which may generate a surge current to the external input voltage VDD or VPPEX. Refer to Figure 1 , for example, when the LDO starts up, since the output voltage VEQ is initially low, far lower than the target voltage, the output voltage of the operational amplifier DIFF is also low. At this time, the gate-source voltage difference of the output PMOS transistor is large, resulting in a large conduction current of the output PMOS transistor, and the load unit C draws a large current from the external voltage source VPPEX.

[0017] Currently, refer to Figure 2 , after the flag signal POR indicating the effectiveness of the voltage source is in an effective state, multiple enable signals (DC1_EN... DC4_EN) for controlling the startup of the multi-channel power supply module are generated simultaneously. That is to say, after the voltage source is effective, the multi-channel power supply module starts up simultaneously. If the multi-channel power supply module starts up simultaneously, the overshoot currents generated by different power supply modules during startup will be superimposed on each other to generate a larger overshoot current. The excessive overshoot current will pull down the external input voltage VDD or VPPEX, resulting in the output voltage of the power supply module not meeting the requirements, and further may cause the functional circuit relying on the output voltage to start up abnormally, or even cause the chip startup to fail.

[0018] The embodiment of the present invention provides a power supply circuit and a memory. After sending the first enable signal for starting the first type of power supply module, multiple external signals are received. Since the second enable signal is generated based on the flag signal and the external signals, the startup time of the second type of power supply module is later than that of the first type of power supply module. At the same time, since each external signal corresponds to a second type of power supply module, by controlling the starting times of different external signals to be different, the second type of power supply modules can be started up at different times. In this way, it is beneficial to reduce the number of power supply modules started up at the same time and ensure the normal startup of the chip. At the same time, the embodiment of the present invention uses external signals to control the time-sharing startup of the power supply module, without the need to set up a dedicated delay circuit, which is beneficial to saving the chip area.

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present invention, many technical details are provided to help the reader better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions required to be protected by the present application can still be implemented.

[0020] Reference Figure 3 , the power supply circuit includes: a voltage source 10 and a multi-channel power supply module 11 connected to the voltage source 10. The power supply module 11 has a power supply terminal (not shown) and a load unit (not shown). If the voltage source 10 is effective and the power supply module 11 is in an enabled state, the power supply module 11 will boost the voltage of the power supply terminal to a preset voltage and supply power to the load unit during the boosting process; the power supply module 11 includes a first type of power supply module 111 and a second type of power supply module 112. The first type of power supply module 111 is used to receive a first enable signal 12a and enter the enabled state if the first enable signal 12a is received. The second type of power supply module 112 is used to receive a second enable signal 12b and enter the enabled state if the second enable signal 12b is received; a control module 12, which is used to receive a flag signal POR. If the received flag signal POR is in an effective state, it sends the first enable signal 12a to the first type of power supply module 111, and the effective state indicates that the voltage source 10 is effective; it is also used to receive a plurality of external signals 12c after sending the first enable signal 12a. Each external signal 12c corresponds to a second type of power supply module 112, and the starting times of different external signals 12c are different. If the flag signal POR and an external signal 12c are received, it sends the second enable signal 12b to the corresponding second type of power supply module 112.

[0021] Among them, the first type of power supply module 111 and the second type of power supply module 112 are distinguished according to the received enable signals. The first type of power supply module 111 includes at least one power supply module 11, and the second type of power supply module 112 includes at least two power supply modules; the main difference between the first enable signal 12a and the second enable signal 12b lies in different generation conditions, and the main difference between different second enable signals 12b lies in different starting times; the effectiveness of the voltage source 10 means that the voltage source 10 has a rated output voltage.

[0022] In some embodiments, reference Figure 4 , the flag signal POR is active high. The level of the flag signal POR rises as the voltage VDD / VPPEX of the voltage source 10 starts to rise. When the voltage of the voltage source 10 rises to the rated value, the level of the flag signal POR is at a high level, that is, the effective state. Subsequently, the level of the flag signal POR falls from the high level to the low level; in other embodiments, the flag signal POR is active low, or as long as the voltage of the voltage source 10 is at the rated value, the level of the flag signal POR is at a high level.

[0023] In some embodiments, the control module 12 includes a first enabling unit 121 and a plurality of second enabling units 122. The output end of each second enabling unit 122 is connected to the enabling end of a corresponding second type of power supply module 112. The first enabling unit 121 is configured to receive a flag signal POR, and send a first enabling signal 12a after the flag signal POR reaches an effective state. The second enabling unit 122 is configured to receive the flag signal POR and an external signal 12c and send a second enabling signal 12b, and the external signals 12c received by different second enabling units 122 are different. It can be understood that the functions of the first enabling unit 121 and the second enabling unit 122 are limited by the function of the control module 12. The first enabling unit 121 sends the first enabling signal 12a only after the flag signal POR is in an effective state, and the second enabling unit 122 sends the second enabling signal 12a only after receiving the flag signal POR and the external signal 12c.

[0024] In some embodiments, the flag signal POR, the external signal 12c, the first enabling signal 12a, and the second enabling signal 12b are high-level effective signals. The first enabling unit 121 generates the first enabling signal 12a based on the flag signal POR. The waveform parameters of the flag signal POR and the first enabling signal 12a may be the same or different, and the waveform parameters include the high-level duration. The second enabling unit 122 generates the second enabling signal 12b based on the flag signal POR and the external signal 12c. The device structure of the second enabling unit 122 can be adjusted according to the level of the flag signal POR at the starting moment of the external signal 12c. At the same time, the starting moment of the second enabling signal 12b may be the same as or different from the starting moment of the corresponding external signal 12c, as long as it is ensured that the starting moments of different second enabling signals 12b generated based on different external signals 12c are different, and the starting moment interval between adjacent second enabling signals 12b is greater than a preset duration.

[0025] Among them, the setting of the preset duration is related to the current-time variation relationship of the overshoot current generated by the startup of a single power module 11. In some embodiments, the preset duration is greater than or equal to the duration of the overshoot current during the startup of a power module 11. That is to say, after one power module 11 is fully started, another power module 11 is started. In this way, the overshoot current can be minimized to ensure the voltage stability of the voltage source 10. In other embodiments, the preset duration is less than the duration of the overshoot current generated during the startup of a single power module 11, but the sum of the overshoot currents of the two power modules 11 is less than the preset overshoot threshold of the voltage source 10. The preset overshoot threshold refers to the overshoot current with a current value less than this value that will not pull down the voltage of the voltage source 10. That is to say, before one power module 11 is fully turned on, another power module 11 is turned on, so that the two overshoot currents are superimposed, but the superimposed current value will not pull down the output voltage of the voltage source 10.

[0026] In some embodiments, the second enabling unit 122 includes an SR latch. Specifically, referring to Figure 5 , the SR latch includes: a first NOR gate 21 and a second NOR gate 22. The first input terminal of the first NOR gate 21 is used to receive an external signal 12c. The second input terminal of the first NOR gate 21 is connected to the output terminal of the second NOR gate 22. The output terminal of the first NOR gate 21 is connected to the first input terminal of the second NOR gate 22. The second input terminal of the second NOR gate 22 is used to receive a flag signal POR. The output terminal of the second NOR gate 22 serves as the output terminal of the second enabling unit 122. The output terminal of the second NOR gate 22 is used to output a second enabling signal 12b. It can be understood that when the external signal 12c is at a low level and the flag signal POR is at a high level, the second NOR gate 22 outputs a low level, the first NOR gate 21 outputs a high level, and the second enabling unit 122 outputs a low level. When the external signal 12c remains at a low level and the flag signal POR falls back to a low level, the second enabling unit 122 keeps outputting a low level. When the flag signal POR is at a low level and the external signal 12c rises to a high level, the first NOR gate 21 outputs a low level, the output terminal of the second NOR gate 22 outputs a high level, and the second enabling unit 122 outputs a high level, that is, a second enabling signal 12b is generated.

[0027] Among them, the external signal 12c being at a low level includes two cases: First, the first NOR gate 21 does not receive the external signal 12c and is pulled low in a floating state, thus showing a low level. Second, the external signal 12c received by the first NOR gate 21 is at a low level.

[0028] In some embodiments, continue to refer to Figure 4, the external signal 12c includes antifuse address signals, and the starting moments of different antifuse address signals are different. The antifuse address signal is a high-level signal inside the chip. Using the antifuse address signal as the external signal eliminates the need to set up additional modules inside the chip to generate the external signal, which helps save chip space. At the same time, there is no need to set up additional modules to receive external signals from outside the chip, which helps avoid chip startup failures caused by fluctuations in external signals and improves the stability of chip startup.

[0029] In some embodiments, the control module 12 is further configured to receive m antifuse address signals, denoted as the first antifuse address signals, and screen out n antifuse address signals from them, denoted as the second antifuse address signals. The starting moment intervals between adjacent second antifuse address signals are the same, and the starting moment interval between adjacent second antifuse address signals is greater than the starting moment interval between adjacent first antifuse address signals. The second antifuse address signals serve as the external signal 12c. That is to say, when the starting moment interval between adjacent first antifuse address signals is less than the above preset duration, or in other words, when the starting moment intervals between adjacent first antifuse address signals are unequal, the control module screens the first antifuse address signals so that the starting moment intervals between the selected adjacent second antifuse address signals meet the requirement of being greater than or equal to the preset duration.

[0030] It should be noted that an independent screening unit can be set inside the control module 12. The screening unit screens the m antifuse address signals according to the requirements of the starting moment intervals, and the requirements include the equality and specific values of the adjacent starting moment intervals.

[0031] In some embodiments, referring to Figure 6 , the control module 12 is also connected to the antifuse scanning unit 14. The antifuse scanning unit 14 is configured to scan the address information of the antifuse array and generate antifuse address signals XADD, and the control module 12 is configured to receive the antifuse address signals XADD generated by the antifuse scanning unit 14.

[0032] In some embodiments, the anti-fuse scanning unit 14 is also used to receive a reset signal Reset_n, which is used to trigger the anti-fuse scanning unit 14 to scan the address information of the anti-fuse array, and the receiving time of the reset signal Reset_n is later than the receiving time of the valid state of the flag signal POR. The control module 12 can first receive the flag signal POR in the valid state, and generate a first enable signal 12a based on the flag signal POR in the valid state to enable the first type of power module 111, and then receive the external signal 12c, and generate a second enable signal 12b based on the external signal 12c and the flag signal POR to enable the second type of power module 112, that is, it can effectively control the first type of power module 111 and the second type of power module 112 to start in time.

[0033] In some embodiments, the control module 12 is also connected to the anti-fuse scanning unit 14 through the local latch 13. The anti-fuse scanning unit 14 is also used to transmit the generated anti-fuse address signal XADD to the local latch 13. The control module 12 is also used to receive the anti-fuse address signal XADD from the local latch 13.

[0034] In some embodiments, the load unit includes a filter capacitor. For example, the power module 11 may be an LDO structure, and the filter capacitor may be connected to a power terminal of the power module 11.

[0035] In some embodiments, the control unit 12 is used to send a first enable signal 12a and a second enable signal 12b before the clock enable signal CKE is generated, so as to enable the first type power module 111 and the second type power module 112. Before the clock enable signal CKE is generated, the DRAM has not started to perform read, write or refresh operations, and it is not necessary for all power modules 11 to be enabled. Therefore, it is sufficient to enable all power modules 11 before the CKE signal is generated.

[0036] The following will be combined Figures 4 to 6 A specific embodiment of the present invention is explained in detail. In this specific embodiment, the first type of power module 111 includes one power module 11, which is recorded as the first power module, and the second type of power module 112 includes three power modules, which are recorded as the second power module, the third power module and the fourth power module.

[0037] After the flag signal POR is in the valid state, the first enabling unit 111 sends a first enabling signal 12a, namely DC1_EN, to the first power module; after the reset signal Reset_n is generated, the control module 12 obtains, through the local latch 13, the anti-fuse address signal XADD at a high level scanned by the anti-fuse scanning unit 14, such as XADD<0:4>; after obtaining the anti-fuse address signal XADD, the control module 12 filters out 3 groups from it, specifically XADD<0>, XADD<2>, XADD<4>; since the flag signal POR is at a low level after obtaining the anti-fuse address signal XADD, therefore, the second enabling unit 122 can generate second enabling signals 12b respectively based on the filtered anti-fuse address signal XADD and the flag signal POR, specifically DC2_EN, DC3_EN, DC4_EN. The starting moment of DC2_EN is the same as that of XADD<0>, the starting moment of DC3_EN is the same as that of XADD<2>, and the starting moment of DC4_EN is the same as that of XADD<4>; send DC2_EN to the second power module to enable the second power module, send DC3_EN to the third power module to enable the third power module, and send DC4_EN to the fourth power module to enable the fourth power module, so as to realize the time-sharing startup of the second power module, the third power module and the fourth power module.

[0038] In this embodiment, since the second enabling signal is generated based on the flag signal and the external signal, by receiving multiple external signals after sending the first enabling signal, the time-sharing startup of the first type of power module and the second type of power module can be realized. At the same time, since each external signal corresponds to a second type of power module, by controlling the starting moments of different external signals to be different, the time-sharing startup of different second type of power modules can be realized. In this way, it is beneficial to reduce the number of power modules started at the same moment, avoid the overshoot current at the same time startup from pulling down the voltage of the voltage source, so as to ensure that the voltage at the power supply end meets the requirements and ensure the normal startup of the functional current connected to the power supply end; at the same time, using the external signal to control the time-sharing startup of the power module eliminates the need to set up a dedicated delay circuit, which is beneficial to saving chip area.

[0039] Correspondingly, an embodiment of the present invention further provides a memory, including the power supply circuit of any one of the above.

[0040] In some embodiments, referring to Figure 7 , the power supply circuit 33 is located in the peripheral circuit area 32 between adjacent memory banks 31, and the memory bank 31 is a memory array area composed of memory cells; further, in the extending direction of the peripheral circuit area 32, a plurality of power supply circuits 32 are evenly distributed.

[0041] In this embodiment, multiple power supply circuits in the memory are started in time-sharing manner, the voltage of the voltage source has high stability, the power supply terminal voltage of the power module can meet the driving requirements, and the functional circuit connected to the power supply terminal can be started normally and effectively.

[0042] Those skilled in the art will appreciate that the above embodiments are specific examples of the present invention, and in practical applications, various changes may be made to the embodiments in form and detail without departing from the spirit and scope of the present invention. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present invention, and therefore the scope of protection of the present invention shall be subject to the scope defined in the claims.

Claims

1. A power supply circuit, characterized in that, Including: A voltage source and a multi-channel power supply module connected to the voltage source. The power supply module has a power supply terminal and a load unit. If the voltage source is effective and the power supply module is in an enabled state, the power supply module raises the voltage of the power supply terminal to a preset voltage and supplies power to the load unit during the raising process. The power supply module includes a first type of power supply module and a second type of power supply module. The first type of power supply module is used to receive a first enable signal and enter the enabled state if the first enable signal is received. The second type of power supply module is used to receive a second enable signal and enter the enabled state if the second enable signal is received. A control module, which is used to receive a flag signal and send the first enable signal to the first type of power supply module if the received flag signal is in an effective state. The effective state indicates that the voltage source is effective. It is also used to receive a plurality of external signals after sending the first enable signal. Each external signal corresponds to a second type of power supply module, and the starting times of different external signals are different. If the flag signal and the external signal are received, the second enable signal is sent to the corresponding second type of power supply module. The external signal includes an anti-fuse address signal, and the starting times of different anti-fuse address signals are different. The control module is further used to receive m first anti-fuse address signals and screen out n second anti-fuse address signals from them. The starting time intervals between adjacent second anti-fuse address signals are the same, and the starting time interval between adjacent second anti-fuse address signals is greater than the starting time interval between adjacent first anti-fuse address signals. The second anti-fuse address signals are used as the external signals.

2. The power supply circuit according to claim 1, wherein The control module includes a first enable unit and a plurality of second enable units. The output end of each second enable unit is connected to the enable end of a corresponding second type of power supply module. The first enable unit is used to receive the flag signal and send the first enable signal after the flag signal reaches the effective state. The second enable unit is used to receive the flag signal and the external signal and send the second enable signal, and the external signals received by different second enable units are different.

3. The power supply circuit according to claim 2, wherein The flag signal, the external signal, the first enable signal, and the second enable signal are high-level effective signals.

4. The power supply circuit according to claim 3, wherein The second enable unit includes an SR latch.

5. The power supply circuit according to claim 4, wherein, The SR latch includes a first NOR gate and a second NOR gate. The first input end of the first NOR gate is used to receive the external signal. The second input end of the first NOR gate is connected to the output end of the second NOR gate. The output end of the first NOR gate is connected to the first input end of the second NOR gate. The second input end of the second NOR gate is used to receive the flag signal. The output end of the second NOR gate is used as the output end of the second enable unit, and the output end of the second NOR gate is used to output the second enable signal.

6. The power supply circuit according to claim 1, wherein The control module is also connected to an anti-fuse scanning unit, which is configured to scan the address information of the anti-fuse array and generate the anti-fuse address signal, and the control module is configured to receive the anti-fuse address signal generated by the anti-fuse scanning unit.

7. The power supply circuit according to claim 6, wherein The anti-fuse scanning unit is further configured to receive a reset signal, which is used to trigger the anti-fuse scanning unit to scan the address information of the anti-fuse array, and the receiving time of the reset signal is later than the receiving time of the valid state of the flag signal.

8. The power supply circuit according to claim 6, wherein The control module is also connected to the anti-fuse scanning unit through a local latch, the anti-fuse scanning unit is further configured to transmit the generated anti-fuse address signal to the local latch, and the control module is also configured to receive the anti-fuse address signal from the local latch.

9. The power supply circuit according to claim 1, wherein The load unit includes a filter capacitor.

10. The power supply circuit according to claim 1, wherein The control module is configured to send the first enable signal and the second enable signal before the generation of the clock enable signal to enable the first type of power supply module and the second type of power supply module.

11. A memory, characterized in that, A power supply circuit according to any one of claims 1 to 10 is included.

12. The memory according to claim 11, wherein, The power supply circuit is located in the peripheral circuit area between adjacent memory banks.

13. The memory according to claim 12, wherein In the extending direction of the peripheral circuit area, a plurality of the power supply circuits are evenly distributed.

Images