Packaging structure and method of manufacture

Abstract

The application discloses a packaging structure and a preparation method. The packaging structure comprises a semiconductor chip, a first non-conductive layer covering the front surface of the semiconductor chip and part of the sidewall of the semiconductor chip, and a second non-conductive layer. The second non-conductive layer is located on the upper surface of the first non-conductive layer and covers at least part of the sidewall of the first non-conductive layer. The melt viscosity of the first non-conductive layer is greater than that of the second non-conductive layer. The packaging structure further comprises a substrate and a solder mask layer. The solder mask layer is located on the surface of the substrate and has a first opening. The semiconductor chip is flip-chip bonded to the substrate. The surface of the second non-conductive layer away from the first non-conductive layer and the surface of the solder mask layer away from the substrate are bonding surfaces. The second non-conductive layer fills the first opening without pores. The second non-conductive layer with low melt viscosity expels air from the packaging structure. The first non-conductive layer with high melt viscosity holds the second non-conductive layer and inhibits overflow of the second non-conductive layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing, and in particular to a packaging structure and its preparation method. Background Technology

[0002] With the rapid development of semiconductor memory technology, the market has placed higher demands on the storage capacity and chip packaging of semiconductor memory products. For Dynamic Random Access Memory (DRAM), after the DRAM chip is constructed, it needs to be packaged to improve its durability.

[0003] However, in traditional packaging structures, a non-conductive film layer covers the chip, and the chip with the non-conductive film layer is bonded to the substrate through a thermal compression bonding (TCB) process. The non-conductive film layer fills the opening area between the chip and the substrate. However, due to the susceptibility to process conditions, some air may be trapped in the opening area, resulting in voids in the packaging structure. This leads to quality problems with the solder bridges formed after subsequent reflow soldering. Summary of the Invention

[0004] Therefore, it is necessary to provide a packaging structure and manufacturing method to address the problems mentioned in the background technology, thereby filling the opening area, eliminating voids, and improving the quality and reliability of the packaging structure.

[0005] To address the aforementioned technical problems, the first aspect of this application proposes a packaging structure, comprising:

[0006] Semiconductor chips;

[0007] A first non-conductive layer covers the front side of the semiconductor chip and part of the sidewall of the semiconductor chip;

[0008] A second non-conductive layer is located on the upper surface of the first non-conductive layer and at least covers a portion of the sidewalls of the first non-conductive layer; wherein the melt viscosity of the first non-conductive layer is greater than the melt viscosity of the second non-conductive layer.

[0009] substrate;

[0010] A solder resist layer is located on the surface of the substrate, and the solder resist layer has a first opening;

[0011] The semiconductor chip is flip-chip bonded to the substrate, and the surface of the second non-conductive layer away from the first non-conductive layer and the surface of the solder resist layer away from the substrate are the bonding surfaces; the second non-conductive layer has no pores and fills the first opening.

[0012] In the packaging structure provided in the above embodiments, a semiconductor chip is disposed; a first non-conductive layer covers the front side of the semiconductor chip and part of the sidewalls of the semiconductor chip; a second non-conductive layer covers the upper surface of the first non-conductive layer and at least covers part of the sidewalls of the first non-conductive layer; wherein, the melt viscosity of the first non-conductive layer is greater than the melt viscosity of the second non-conductive layer; a substrate; a solder resist layer located on the surface of the substrate, the solder resist layer having a first opening; the semiconductor chip is flip-chip bonded to the substrate, the surface of the second non-conductive layer away from the first non-conductive layer and the surface of the solder resist layer away from the substrate are the bonding surfaces; the second non-conductive layer has no pores and fills the first opening. Two non-conductive film layers with different melt viscosities are used. The lower layer, a second non-conductive layer with low melt viscosity, covers the first non-conductive layer. The second non-conductive layer has good fluidity and can easily fill the first opening, expelling air from the packaging structure and eliminating voids. The first non-conductive layer with high melt viscosity covers the semiconductor chip. The first non-conductive layer holds the second non-conductive layer in place, suppressing the overflow of the second non-conductive layer. This ensures that the second non-conductive layer overflows the semiconductor chip due to its high fluidity, preventing voids from reappearing in the packaging structure and improving the quality and reliability of the packaging structure.

[0013] In one embodiment, the melt viscosity of the first non-conductive layer is 2000 Pa·s to 3000 Pa·s, and the melt viscosity of the second non-conductive layer is less than or equal to 1000 Pa·s.

[0014] In one embodiment, the semiconductor chip includes a chip body, a first dielectric layer, a second dielectric layer, and metal bumps; the chip body, the first dielectric layer, and the second dielectric layer are stacked sequentially; a device structure is formed on the front side of the chip body, and the first dielectric layer and the second dielectric layer have second openings that expose the device structure; the metal bumps are electrically connected to the device structure; and the first non-conductive layer is located on the surface of the second dielectric layer.

[0015] In one embodiment, the metal bump includes a metal pillar and solder balls, the solder balls being located on the surface of the metal pillar; the metal pillar is connected to the device structure.

[0016] In one embodiment, the surface of the substrate has pads, and the first opening exposes the pads; the metal bumps are in contact with the pads.

[0017] In one embodiment, there are multiple metal bumps and multiple pads, and the multiple pads are arranged in a one-to-one correspondence with the multiple metal bumps.

[0018] In one embodiment, the thickness of the second non-conductive layer is less than or equal to the thickness of the solder resist layer.

[0019] In one embodiment, the material of the solder resist layer includes solder resist green paint.

[0020] The second aspect of this application provides a method for fabricating a packaging structure, comprising:

[0021] Provide semiconductor chips;

[0022] A first non-conductive layer is formed on the front side of the semiconductor chip;

[0023] A second non-conductive layer is formed on the upper surface of the first non-conductive layer; wherein the melt viscosity of the first non-conductive layer is greater than the melt viscosity of the second non-conductive layer;

[0024] A substrate is provided, wherein a solder resist layer is formed on the surface of the substrate, and a first opening is formed within the solder resist layer;

[0025] The semiconductor chip is flip-chip bonded to the substrate, and the surface of the second non-conductive layer away from the first non-conductive layer and the surface of the solder resist layer away from the substrate are the bonding surfaces; the second non-conductive layer has no pores and fills the first opening.

[0026] In one embodiment, the melt viscosity of the first non-conductive layer is 2000 Pa·s to 3000 Pa·s, and the melt viscosity of the second non-conductive layer is less than or equal to 1000 Pa·s.

[0027] In one embodiment, the semiconductor chip is flip-chip bonded to the substrate using a thermo-press bonding process.

[0028] In one embodiment, before flip-bonding the semiconductor chip onto the substrate, the method further includes:

[0029] The substrate is preheated at a temperature of 130°C to 200°C.

[0030] In one embodiment, pads are formed on the surface of the substrate, and the first opening exposes the pads; the substrate is provided, and a solder resist layer is formed on the surface of the substrate, with the first opening formed within the solder resist layer, including:

[0031] A pad is formed on the surface of the substrate;

[0032] A solder resist layer is formed on the surface of the substrate and on the solder pads;

[0033] The solder resist layer is patterned, and a portion of the solder resist layer is removed to obtain the solder resist layer; the area corresponding to the removed portion of the solder resist layer is the first opening.

[0034] In one embodiment, a wet etching process is used to remove a portion of the solder resist layer located on the surface of the substrate.

[0035] In one embodiment, the thickness of the second non-conductive layer is less than or equal to the thickness of the solder resist layer.

[0036] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, the preferred embodiments of this application are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0037] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other embodiments can be obtained from these drawings without creative effort.

[0038] Figure 1 This is a schematic flowchart of a method for preparing a packaging structure provided in one embodiment of this application;

[0039] Figure 2 This is a partial cross-sectional schematic diagram of the structure obtained after forming a chip body with a device structure in the preparation method of the packaging structure provided in one embodiment of this application;

[0040] Figure 3 This is a partial cross-sectional schematic diagram of the structure obtained after forming the first dielectric material layer in the preparation method of the encapsulation structure provided in one embodiment of this application;

[0041] Figure 4 This is a partial cross-sectional schematic diagram of the structure obtained after forming the second dielectric material layer in the preparation method of the encapsulation structure provided in one embodiment of this application;

[0042] Figure 5 This is a partial cross-sectional schematic diagram of the structure obtained after forming a second opening to expose the device structure in a method for fabricating the packaging structure provided in one embodiment of this application;

[0043] Figure 6 This is a partial cross-sectional schematic diagram of the structure obtained after forming metal bumps in the method for preparing the packaging structure provided in one embodiment of this application;

[0044] Figure 7 This is a partial cross-sectional schematic diagram of the structure obtained after forming the first non-conductive layer in the preparation method of the encapsulation structure provided in an embodiment of this application;

[0045] Figure 8This is a partial cross-sectional schematic diagram of the structure obtained after forming the second non-conductive layer in the preparation method of the encapsulation structure provided in one embodiment of this application;

[0046] Figure 9 This is a partial cross-sectional schematic diagram of the structure obtained after providing a substrate in the fabrication method of the packaging structure provided in one embodiment of this application;

[0047] Figure 10 This is a partial cross-sectional schematic diagram of the structure obtained after forming the pads in the method for preparing the packaging structure provided in one embodiment of this application;

[0048] Figure 11 This is a partial cross-sectional schematic diagram of the structure obtained after forming a solder resist layer in the preparation method of the packaging structure provided in one embodiment of this application;

[0049] Figure 12 This is a partial cross-sectional schematic diagram of the structure obtained after forming the solder resist layer and the first opening in the preparation method of the packaging structure provided in one embodiment of this application;

[0050] Figure 13 This is a partial cross-sectional schematic diagram of the structure obtained after flip-bonding a semiconductor chip to a substrate in a method for fabricating a packaging structure provided in an embodiment of this application.

[0051] Figure 14 This is a partial cross-sectional schematic diagram of the structure obtained after forming a plastic encapsulation layer in the preparation method of the encapsulation structure provided in one embodiment of this application.

[0052] Explanation of reference numerals in the attached figures: 10-semiconductor chip, 11-chip body, 111-circuit structure, 12-device structure, 121-second opening, 13-first dielectric layer, 131-first dielectric material layer, 14-second dielectric layer, 141-second dielectric material layer;

[0053] 15-Metal bump, 151-Metal pillar, 152-Solder ball;

[0054] 21-First non-conductive layer, 22-Second non-conductive layer;

[0055] 23-Substrate, 24-Pad, 25-Solder resist layer, 251-Solder resist material layer, 26-First opening;

[0056] 27 - Sealing layer. Detailed Implementation

[0057] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0059] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0060] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0061] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0062] Embodiments of the application are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures). Thus, variations from the illustrated shape can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. The regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of regions of the device and are not intended to limit the scope of the application.

[0063] In one embodiment of this application, such as Figure 1 As shown, a method for fabricating a packaging structure is provided, comprising the following steps:

[0064] Step S10: Provide a semiconductor chip;

[0065] Step S20: Form a first non-conductive layer on the front side of the semiconductor chip;

[0066] Step S30: A second non-conductive layer is formed on the upper surface of the first non-conductive layer; wherein the melt viscosity of the first non-conductive layer is greater than the melt viscosity of the second non-conductive layer;

[0067] Step S40: Provide a substrate, on the surface of which a solder resist layer is formed, and a first opening is formed within the solder resist layer;

[0068] Step S50: The semiconductor chip is flip-chip bonded to the substrate, and the surface of the second non-conductive layer away from the first non-conductive layer and the surface of the solder resist layer away from the substrate are the bonding surfaces; the second non-conductive layer has no pores and fills the first opening.

[0069] In the packaging structure provided in the above embodiments, a semiconductor chip is provided; a first non-conductive layer is formed on the front side of the semiconductor chip; a second non-conductive layer is formed on the upper surface of the first non-conductive layer; wherein the melt viscosity of the first non-conductive layer is greater than the melt viscosity of the second non-conductive layer; a substrate is provided, a solder resist layer is formed on the surface of the substrate, and a first opening is formed in the solder resist layer; the semiconductor chip is flip-chip bonded to the substrate, and the surface of the second non-conductive layer away from the first non-conductive layer and the surface of the solder resist layer away from the substrate are the bonding surfaces; the second non-conductive layer fills the first opening without any pores. Two non-conductive film layers with different melt viscosities are used. The lower layer, the second non-conductive layer with low melt viscosity, covers the first non-conductive layer. The second non-conductive layer has better fluidity and easily fills the first opening, expelling air from the packaging structure. The higher melt viscosity of the first non-conductive layer covers the semiconductor chip. The first non-conductive layer holds the second non-conductive layer, suppressing the overflow of the second non-conductive layer and ensuring that the second non-conductive layer overflows the semiconductor chip due to its higher fluidity, thus preventing voids from reappearing in the packaging structure and improving the quality and reliability of the packaging structure.

[0070] In one embodiment, providing the semiconductor chip in step S10 includes the following steps:

[0071] Step S11: Provide a main chip 11, on the front side of which a device structure 12 is formed; the main chip 11 includes a circuit structure 111, which is electrically connected to the device structure 12, such as... Figure 2 As shown;

[0072] Step S12: A first dielectric layer 13 and a second dielectric layer 14 are sequentially formed on the front side of the main chip 11, such as... Figure 3 and Figure 4 As shown; a second opening 121 is formed within the first dielectric layer 13 and the second dielectric layer 14, and the second opening 121 exposes the device structure 12, as shown. Figure 5 As shown;

[0073] Step S13: A metal bump 15 is formed on the device structure 12 on the front side of the main chip 11. The metal bump 15 is electrically connected to the device structure 12, such as... Figure 6 As shown.

[0074] In one embodiment, multiple device structures 12 can be formed on the front side of each main chip 11, and each device structure 12 is correspondingly arranged with a metal bump 15. The metal bump 15 includes metal pillars 151 and solder balls 152. The metal pillars 151 are electrically connected to the device structures 12, and the solder balls 152 are located on the upper surface of the metal pillars 151. As an example, the material of the metal pillars 151 may include, but is not limited to, copper, tungsten, tin, or alloys formed by any combination of the above metals. The material of the solder balls 152 may include, but is not limited to, copper, tungsten, tin, or alloys formed by any combination of the above metals.

[0075] In one embodiment, step S12: a first dielectric layer 13 and a second dielectric layer 14 are sequentially formed on the front side of the main chip 11, and a second opening 121 is formed in the first dielectric layer 13 and the second dielectric layer 14, exposing the device structure 12, including the following steps:

[0076] Step S121: Form a first dielectric material layer 131 on the front side of the main chip 11, such as... Figure 3 As shown;

[0077] Step S121: A second dielectric material layer 141 is formed on the surface of the first dielectric material layer 131 away from the front side of the host chip 11, such as... Figure 4 As shown;

[0078] Step S121: Graphically visualize the first dielectric material layer 131 and the second dielectric material layer 141, and remove a portion of the first dielectric material layer 131 and the second dielectric material layer 141 to obtain the first dielectric layer 13 and the second dielectric layer 14; the area corresponding to the removed portion of the first dielectric material layer 131 and the second dielectric material layer 141 is the second opening 121, such as... Figure 5 As shown.

[0079] As an example, the material of the first dielectric layer 13 may include, but is not limited to, silicon oxide or silicon nitride, etc.; the material of the second dielectric layer 14 may include, but is not limited to, silicon oxide or silicon nitride, etc.; the materials of the first dielectric layer 13 and the second dielectric layer 14 may be the same or different.

[0080] In one embodiment, such as Figure 7 and Figure 8 As shown, in step S20, the first non-conductive layer 21 covers the front side of the semiconductor chip 10 and encapsulates the solder balls 152. In step S30, the second non-conductive layer 22 covers the upper surface of the first non-conductive layer 21 but does not cover the sidewalls of the semiconductor chip 10. When the semiconductor chip 10 is operating, the chip body 11 generates heat. If the second non-conductive layer 22 covers the sidewalls of the semiconductor chip 10, the heat generated by the chip body 11 will accelerate the flow of the second non-conductive layer 22, causing voids to reappear within the substrate 23.

[0081] In one embodiment, the melt viscosity of the first non-conductive layer is 2000 Pa·s to 3000 Pa·s, and the melt viscosity of the second non-conductive layer is less than or equal to 1000 Pa·s. Specifically, the melt viscosity of the first non-conductive layer is 2000 Pa·s, 2100 Pa·s, 2200 Pa·s, 2300 Pa·s, 2400 Pa·s, 2500 Pa·s, 2600 Pa·s, 2700 Pa·s, 2800 Pa·s, 2900 Pa·s, or 3000 Pa·s, etc.; and the melt viscosity of the second non-conductive layer is 100 Pa·s, 200 Pa·s, 300 Pa·s, 400 Pa·s, 500 Pa·s, 600 Pa·s, 700 Pa·s, 800 Pa·s, 900 Pa·s, or 1000 Pa·s, etc. The materials of the first non-conductive layer 21 and the second non-conductive layer 22 are both viscous adhesives. It is acceptable for the first non-conductive layer 21 to have high melt viscosity and the second non-conductive layer 22 to have low melt viscosity. The specific materials are not limited.

[0082] In one embodiment, such as Figure 9 As shown, the substrate 23 provided in step S40 may include, but is not limited to, a silicon substrate. Pads 24 are formed on the surface of the substrate 23.

[0083] Step S40: Providing a substrate 23, wherein a solder resist layer 25 is formed on the surface of the substrate 23, and a first opening 26 is formed within the solder resist layer 25, including the following steps:

[0084] Step S41: Form pads 24 on the surface of substrate 23, such as Figure 10 As shown;

[0085] Step S42: A solder resist layer 251 is formed on the surface of the substrate 23 and on the pads 24, the solder resist layer 251 covering the pads 24, as shown. Figure 11 As shown;

[0086] Step S43: The solder resist layer 251 is patterned, and a portion of the solder resist layer 251 is removed to obtain the solder resist layer 25; the area corresponding to the removed portion of the solder resist layer 251 is the first opening 26, and the first opening 26 exposes the pads 24, as shown. Figure 12 As shown.

[0087] Specifically, a wet etching process is used to remove part of the solder resist layer 251 located on the surface of the substrate 23.

[0088] In one embodiment, the thickness of the second non-conductive layer 22 is less than or equal to the thickness of the solder resist layer 25. After the semiconductor chip 10 is subsequently flip-chip bonded to the substrate 23, the second non-conductive layer 22, with a thickness less than or equal to the solder resist layer 25, can fill the first opening 26 while reducing the overflow of the second non-conductive layer material. The solder resist layer 25 is made of solder resist green paint. There can be multiple pads 24, and each pad 24 corresponds to one of the multiple metal bumps 15.

[0089] In one embodiment, step S50: the semiconductor chip 10 is flip-chip bonded to the substrate 23, and the structure obtained after the second non-conductive layer 22 fills the first opening 26 without any pores is as follows. Figure 13 As shown, the pad 24 is in contact with the metal bump 15, that is, the solder ball 152 is in contact with the pad 24; wherein, the first non-conductive layer 21 covers part of the sidewall of the semiconductor chip 10 and part of the sidewall of the chip body 11; the portion of the first non-conductive layer 22 covering the sidewall of the chip body 11 extends at least beyond the interface of the circuit structure 111 within the chip body 11, thereby better protecting the semiconductor chip 10. The second non-conductive layer 22 fills the first opening 26 without any pores and at least covers part of the sidewall of the first non-conductive layer 22.

[0090] Specifically, the semiconductor chip 10 is flip-chip bonded to the substrate 23 using a thermo-press bonding (TCB) process. Step S50: Before flip-chip bonding the semiconductor chip 10 to the substrate 23, the process further includes:

[0091] Step S401: Preheat the substrate 23 to a temperature of 130℃~200℃ to expel air from the area of ​​the first opening 26 by utilizing the low melt viscosity of the second non-conductive layer 22. Specifically, the preheating temperature is 130℃, 140℃, 150℃, 160℃, 170℃, 180℃, 190℃, or 200℃, etc. After the air is completely expelled, perform hot pressing. Within a first preset temperature range, the second non-conductive layer 22 flows while the first non-conductive layer 21 solidifies; within a second preset temperature range, the second non-conductive layer 22 solidifies and flows while the first non-conductive layer 21 begins to flow.

[0092] In one embodiment, in step S50: the semiconductor chip 10 is flip-chip bonded to the substrate 23, and the surface of the second non-conductive layer 22 away from the first non-conductive layer 21 and the surface of the solder resist layer 25 away from the substrate 23 are the bonding surfaces; after the second non-conductive layer 22 fills the first opening 26 without any pores, the following steps are also included:

[0093] Step S60: A molding compound 27 is formed on the upper surface of the solder resist layer 25. The molding compound 27 encapsulates the semiconductor chip 10, the first non-conductive layer 21, and the second non-conductive layer 22, as shown below. Figure 14As shown. The sidewalls of the first dielectric layer 23 and the second dielectric layer 14 are completely covered by the first non-conductive layer 21 and do not directly contact the molding layer 27. Therefore, there will be no reliability problems caused by excessive differences in the coefficient of expansion.

[0094] In one embodiment of this application, a packaging structure is also proposed, comprising: a semiconductor chip 10; a first non-conductive layer 21 covering the front side of the semiconductor chip 10 and a portion of the sidewalls of the semiconductor chip 10; a second non-conductive layer 22 located on the upper surface of the first non-conductive layer 21 and at least covering a portion of the sidewalls of the first non-conductive layer 21; wherein the melt viscosity of the first non-conductive layer 21 is greater than the melt viscosity of the second non-conductive layer 22; a substrate 23; a solder resist layer 25 located on the surface of the substrate 23, the solder resist layer 25 having a first opening 26; the semiconductor chip 10 being flip-chip bonded to the substrate 23, the surface of the second non-conductive layer 22 away from the first non-conductive layer 21 and the surface of the solder resist layer 25 away from the substrate 23 being the bonding surfaces; the second non-conductive layer 22 filling the first opening 26 without pores.

[0095] In the packaging structure provided in the above embodiments, a semiconductor chip is disposed; a first non-conductive layer covers the front side of the semiconductor chip and part of the sidewalls of the semiconductor chip; a second non-conductive layer covers the upper surface of the first non-conductive layer and at least covers part of the sidewalls of the first non-conductive layer; wherein, the melt viscosity of the first non-conductive layer is greater than the melt viscosity of the second non-conductive layer; a substrate; a solder resist layer located on the surface of the substrate, the solder resist layer having a first opening; the semiconductor chip is flip-chip bonded to the substrate, the surface of the second non-conductive layer away from the first non-conductive layer and the surface of the solder resist layer away from the substrate are the bonding surfaces; the second non-conductive layer has no pores and fills the first opening. Two non-conductive film layers with different melt viscosities are used. The lower layer, a second non-conductive layer with low melt viscosity, covers the first non-conductive layer. The second non-conductive layer has good fluidity and can easily fill the first opening and expel air. The first non-conductive layer with high melt viscosity covers the semiconductor chip. The first non-conductive layer holds the second non-conductive layer and suppresses the overflow of the second non-conductive layer. This ensures that the second non-conductive layer overflows the semiconductor chip due to its high fluidity, avoids the re-emergence of voids in the packaging structure, and improves the quality and reliability of the packaging structure.

[0096] In one embodiment, the melt viscosity of the first non-conductive layer 21 is 2000 Pa·s to 3000 Pa·s, and the melt viscosity of the second non-conductive layer 22 is less than or equal to 1000 Pa·s. Specifically, the melt viscosity of the first non-conductive layer 21 is 2000 Pa·s, 2100 Pa·s, 2200 Pa·s, 2300 Pa·s, 2400 Pa·s, 2500 Pa·s, 2600 Pa·s, 2700 Pa·s, 2800 Pa·s, 2900 Pa·s, or 3000 Pa·s, etc.; the melt viscosity of the second non-conductive layer 22 is 100 Pa·s, 200 Pa·s, 300 Pa·s, 400 Pa·s, 500 Pa·s, 600 Pa·s, 700 Pa·s, 800 Pa·s, 900 Pa·s, or 1000 Pa·s, etc. The materials of the first non-conductive layer 21 and the second non-conductive layer 22 are both viscous adhesives. It is acceptable for the first non-conductive layer 21 to have high melt viscosity and the second non-conductive layer 22 to have low melt viscosity. The specific materials are not limited.

[0097] In one embodiment, the semiconductor chip 10 includes a chip body 11, a first dielectric layer 13, a second dielectric layer 14, and metal bumps 15; the chip body 11, the first dielectric layer 13, and the second dielectric layer 14 are stacked sequentially; a device structure 12 is formed on the front side of the chip body 11, and the first dielectric layer 13 and the second dielectric layer 14 have second openings 121 that expose the device structure 12; the metal bumps 15 are electrically connected to the device structure 12; and a first non-conductive layer 21 is located on the surface of the second dielectric layer 14.

[0098] As an example, the material of the first dielectric layer 13 may include, but is not limited to, silicon oxide or silicon nitride, etc.; the material of the second dielectric layer 14 may include, but is not limited to, silicon oxide or silicon nitride, etc.; the materials of the first dielectric layer 13 and the second dielectric layer 14 may be the same or different.

[0099] In one embodiment, the metal bump 15 includes a metal pillar 151 and solder balls 152, the solder balls 152 being located on the surface of the metal pillar 151; the metal pillar 151 is connected to the device structure 12. As an example, the material of the metal pillar 151 may include, but is not limited to, copper, tungsten, tin, or alloys formed from any combination of the above metals. The material of the solder balls 152 may include, but is not limited to, copper, tungsten, tin, or alloys formed from any combination of the above metals.

[0100] In one embodiment, the surface of the substrate 23 has pads, and a first opening 26 exposes the pads 24; metal bumps 15 are in contact with the pads 24. Specifically, solder balls 152 are in contact with the pads 24; there are multiple metal bumps 15 and pads 24, and the multiple pads 24 are arranged in a one-to-one correspondence with the multiple metal bumps 15.

[0101] In one embodiment, the thickness of the second non-conductive layer 22 is less than or equal to the thickness of the solder resist layer 25. After the semiconductor chip 10 is flip-bonded onto the substrate 23, the second non-conductive layer 22, with a thickness less than or equal to the solder resist layer 25, can fill the first opening 26 while reducing material overflow of the second non-conductive layer.

[0102] In one embodiment, the material of the solder resist layer 25 includes solder resist green paint.

[0103] In one embodiment, the packaging structure further includes a molding compound 27, which encapsulates the semiconductor chip 10, the first non-conductive layer 21, and the second non-conductive layer 22. The sidewalls of the first dielectric layer 23 and the second dielectric layer 14 are completely covered by the first non-conductive layer 21 and do not directly contact the molding compound 27, thus avoiding reliability issues caused by excessive differences in their coefficients of thermal expansion.

[0104] As an example, the material of the molding layer 27 may include, but is not limited to, any one or any combination of epoxy molding compound (EMC), polyimide, silicone, polymer-based materials and resin-based materials, to enhance the bonding strength between the semiconductor chip 10 and the substrate 23, improve the stability of the packaging structure, and protect the semiconductor chip 10.

[0105] Please note that the above embodiments are for illustrative purposes only and do not imply any limitation on this application.

[0106] It should be understood that, unless otherwise expressly stated herein, there is no strict order in which the steps are performed, and these steps may be performed in other orders. Moreover, at least some of the steps may include multiple sub-steps or multiple stages, which are not necessarily completed at the same time, but may be performed at different times, and the execution order of these sub-steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0107] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0108] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A package structure, characterized by, Comprising: a semiconductor chip; a first non-conductive layer covering a front surface of the semiconductor chip and part of a sidewall of the semiconductor chip; a second non-conductive layer on an upper surface of the first non-conductive layer and covering at least part of the sidewall of the first non-conductive layer; wherein a melt viscosity of the first non-conductive layer is greater than a melt viscosity of the second non-conductive layer; a substrate; a solder resist layer on a surface of the substrate, the solder resist layer having a first opening therein; the semiconductor chip is flip-chip bonded to the substrate, a surface of the second non-conductive layer away from the first non-conductive layer and a surface of the solder resist layer away from the substrate being bonding surfaces; the second non-conductive layer fills the first opening without voids; wherein the semiconductor chip comprises a chip body, a first dielectric layer, a second dielectric layer, and a metal bump; the chip body, the first dielectric layer, and the second dielectric layer are sequentially stacked; the first non-conductive layer is on a surface of the second dielectric layer; sidewalls of the first dielectric layer and the second dielectric layer are covered by the first non-conductive layer.

2. The packaging structure according to claim 1, wherein: the melt viscosity of the first non-conductive layer is 2000 Pa·s to 3000 Pa·s, and the melt viscosity of the second non-conductive layer is less than or equal to 1000 Pa·s.

3. The packaging structure according to claim 1, wherein: a front surface of the chip body forms a device structure, the first dielectric layer and the second dielectric layer have a second opening therein, the second opening exposes the device structure; and the metal bump is electrically connected to the device structure.

4. The packaging structure according to claim 3, wherein: the metal bump comprises a metal column and a solder ball, the solder ball is on a surface of the metal column; and the metal column is connected to the device structure.

5. The packaging structure according to claim 3, wherein: a surface of the substrate has a pad, the first opening exposes the pad; and the metal bump is in contact with the pad.

6. The packaging structure according to claim 5, wherein: the metal bump and the pad are both a plurality of, a plurality of the pads and a plurality of the metal bumps are one-to-one correspondingly arranged.

7. The packaging structure according to any one of claims 1 to 6, wherein: a thickness of the second non-conductive layer is less than or equal to a thickness of the solder resist layer.

8. The packaging structure according to any one of claims 1 to 6, wherein: a material of the solder resist layer comprises solder resist green paint.

9. The packaging structure according to any one of claims 1 to 6, wherein: the packaging structure comprises a plastic encapsulation layer, the plastic encapsulation layer covers the semiconductor chip, the first non-conductive layer, and the second non-conductive layer.

10. A method for preparing a packaging structure, characterized in that, Comprising: providing a semiconductor chip; forming a first non-conductive layer on a front surface of the semiconductor chip; forming a second non-conductive layer on an upper surface of the first non-conductive layer; wherein a melt viscosity of the first non-conductive layer is greater than a melt viscosity of the second non-conductive layer; providing a substrate, a surface of the substrate forms a solder resist layer, the solder resist layer has a first opening therein; The semiconductor chip is flip-chip bonded on the substrate, surfaces of the second non-conductive layer away from the first non-conductive layer and the anti-solder layer away from the substrate are bonding surfaces; the second non-conductive layer fills the first opening without pores. The semiconductor chip comprises a chip body, a first dielectric layer, a second dielectric layer and a metal bump; the chip body, the first dielectric layer and the second dielectric layer are sequentially stacked; the first non-conductive layer is located on a surface of the second dielectric layer; sidewalls of the first dielectric layer and the second dielectric layer are covered by the first non-conductive layer.

11. The method of claim 10, wherein, The melt viscosity of the first non-conductive layer is 2000 Pa·s to 3000 Pa·s, and the melt viscosity of the second non-conductive layer is less than or equal to 1000 Pa·s.

12. The method of claim 10, wherein, The semiconductor chip is flip-chip bonded on the substrate by a thermal compression bonding process.

13. The method of claim 10, wherein, Before the semiconductor chip is flip-chip bonded on the substrate, the method further comprises: The substrate is preheated, and the preheating temperature is 130°C to 200°C.

14. The method of claim 10, wherein, The surface of the substrate is formed with a pad, and the first opening exposes the pad; the substrate is provided, and the surface of the substrate is formed with an anti-solder layer, and the anti-solder layer is formed with a first opening, comprising: The pad is formed on the surface of the substrate; The anti-solder material layer is formed on the surface of the substrate and the pad; The anti-solder material layer is patterned to remove part of the anti-solder material layer to obtain the anti-solder layer; the removed part of the anti-solder material layer corresponds to the first opening.

15. The method of claim 14, wherein, The part of the anti-solder material layer on the surface of the substrate is removed by a wet etching process.

16. The method of claim 10, wherein, The thickness of the second non-conductive layer is less than or equal to the thickness of the anti-solder layer.

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