A carbon nanotube and zinc oxide hybrid TFT CMOS logic circuit and its preparation method

Abstract

The present invention relates to a TFT CMOS logic circuit comprising a mixture of two semiconductor materials: carbon nanotubes (CNTs) and zinc oxide (ZnO), and a method for fabricating the same. The CMOS circuit structure comprises an equal number of PMOS and NMOS transistors. The CMOS is fabricated using planar thin-film growth and patterning techniques. The PMOS active layer is CNT, and the NMOS active layer is ZnO. The PMOS source and drain electrodes are gold, and the gate is ITO. The three NMOS electrodes are all ITO, and the gate oxide layers of both the PMOS and NMOS are Al2O3. The TFT CMOS logic circuit of the present invention can be used to fabricate small and medium-sized integrated circuits. The hybrid material CMOS logic circuit of the present invention has low cost, simple fabrication, and excellent electrical performance. Compared to conventional enhancement-mode, depletion-mode, and pseudo-CMOS transistors, it offers advantages such as low power consumption, high noise tolerance, high gain, simple structure, and high integration.

Description

Technical Field

[0001] The present invention relates to a TFT CMOS logic circuit, in particular to a carbon nanotube and zinc oxide mixed TFT CMOS logic circuit and a preparation method thereof. Background Art

[0002] CMOS is the basic structure of modern digital logic circuits, which is integrated with equal numbers of NMOS and PMOS. Usually, one end of the NMOS source and drain electrode is output and the other end is ground, one end of the PMOS is power supply and the other end is ground. The N / PMOS gates are connected together as inputs. When the logic circuit is working, only one of the N / PMOS will be turned on. The current in the entire circuit is determined by the off-state current of the closed transistor. The low power consumption of CMOS has become the basis for large-scale integrated circuits to operate with low power consumption.

[0003] Thin-film transistors (TFTs), with their flexible material selection and simple manufacturing processes, are increasingly being used in display driver circuits, sensors, and other applications. Zinc oxide (ZnO) TFTs, in particular, have garnered significant attention due to their high electron mobility, low manufacturing cost, and high transparency. However, during the zinc oxide growth and annealing process, oxygen vacancy defects are generated. When these defects accumulate to a certain level, they form donor energy levels in the band gap, causing ZnO TFTs to shift toward the n-type. Consequently, conventional load-mode or depletion-mode logic circuits are typically fabricated using ZnO TFTs, and there have been no reports of successful fabrication of CMOS logic circuits. The material's inability to fabricate CMOS circuits further limits its application in digital logic. Summary of the Invention

[0004] Aiming at the defective characteristics of existing materials, the present invention provides a high-performance, low-power CMOS logic circuit based on a mixture of two different semiconductor materials TFTs and a preparation method thereof.

[0005] The present invention provides a high-performance, low-power CMOS logic circuit based on a hybrid of two different semiconductor materials, TFTs. The CMOS circuit structure is composed of an equal number of PMOS and NMOS transistors. The upper transistor (PMOS) of the CMOS logic circuit has a bottom-gate structure, while the lower transistor (NMOS) of the CMOS logic circuit has a top-gate structure. The PMOS and NMOS transistors (TFTs) are connected between the power supply and ground of the CMOS logic circuit. The input of the CMOS logic circuit is connected to the gates of the PMOS and NMOS transistors, and the output is connected to the junction of the PMOS and NMOS transistors.

[0006] The PMOS TFT active layer is CNT, and the NMOS active layer is ZnO;

[0007] The source and drain electrodes of the PMOS TFT are gold, the gate is ITO, and the three electrodes of the NMOS are all ITO;

[0008] The P / NMOS TFT comprises an electrode, an active layer and a gate oxide layer.

[0009] Furthermore, the CNT is a single-arm semiconductor carbon nanotube, which is structurally formed by curling a single layer of graphene, has a band gap width between 0.8-1.2 eV, a diameter distribution of 1.2-1.8 nm, and a length distribution of 0.8-3.2 um.

[0010] Furthermore, the CMOS structure, from bottom to top, is ITO (NMOS source and drain, PMOS gate), ZnO (NMOS active layer), Al2O3 (gate oxide layer), ITO (NMOS gate), Au (PMOS source and drain), and CNT (PMOS active layer).

[0011] Furthermore, the hybrid CMOS logic circuit can be used to manufacture some small and medium-scale digital logic integrated circuits.

[0012] The present invention utilizes the complementary properties of materials to solve the problem that semiconducting CNT is unsuitable for NMOS due to the adsorption of water and oxygen in the air, and that ZnO is unsuitable for PMOS due to oxygen vacancy defects in the lattice. This changes the situation in the past where a single material could only be used to make depletion-type load logic circuits and pseudo-CMOS, and improves the application of the two semiconductor materials in the field of digital logic circuits. The bottom tube NMOS of the complementary CMOS circuit can, to a certain extent, compensate for the poor consistency of TFT devices caused by the disordered network film of the CNT channel. The noise tolerance of the CMOS logic circuit itself can also effectively solve the consistency problem of CNT TFT devices caused by the random distribution of the CNT network film. The interconnection of the top-gate NMOS and bottom-gate PMOS structures can maximize the material properties, thereby further improving the performance of the CMOS logic circuit.

[0013] The present invention also provides a method for preparing a TFT CMOS logic circuit that is a mixture of two semiconductor materials, carbon nanotubes (CNTs) and zinc oxide (ZnO). The CMOS logic circuit is manufactured based on planar thin film growth and patterning technology. The specific steps are as follows:

[0014] (1) All processes are carried out on a glass substrate, which is first cleaned and dried;

[0015] (2) depositing ITO on a glass substrate by magnetron sputtering, and then etching the ITO with aqua regia to make corresponding electrode patterns to obtain the source and drain electrodes of the NMOS and the gate electrode of the PMOS;

[0016] (3) growing a ZnO active layer and a protective layer of Al2O3 by atomic layer deposition (ALD), and forming an NMOS active layer by hydrofluoric acid etching;

[0017] (4) Continue to grow Al2O3 as the gate oxide layer of N / PMOS by ALD, and also use hydrofluoric acid to etch contact holes to facilitate testing and make top and bottom gate structure interconnections;

[0018] (5) Depositing ITO by magnetron sputtering again and making NMOS gate pattern by lift-off process;

[0019] (6) Gold (Au) is deposited by magnetron sputtering, and the source and drain electrodes of the PMOS are made by the lift-off process. Many studies have shown that the P-type characteristics of CNT TFTs are related to the source and drain electrode materials, and gold (Au) is one of the suitable candidate materials.

[0020] (7) Place the structure obtained in step (6) flatly in a culture dish, evenly apply a semiconducting CNT solution containing toluene as a solvent onto the structure, and cover the culture dish with a lid to prevent evaporation;

[0021] (8) After one day of rest, the CNTs have been deposited on the substrate (through van der Waals adsorption). The unnecessary parts are etched away by oxygen plasma, leaving the active layer of the PMOS, completing the entire process.

[0022] The semiconducting carbon nanotube solution using toluene as solvent selected in step (7) is a commercial solution, and its specific parameters are as follows: concentration 10ug / ml, semiconductor purity 99.99%, carbon nanotube diameter distribution 1.2-1.8nm, carbon nanotube length distribution 0.8-3.2um.

[0023] A basic logic unit of a TFT CMOS circuit based on the hybrid material can be used to manufacture digital integrated circuits. The basic logic devices in the digital integrated circuit include an inverter (INV), a NAND gate (NAND), and a NOR gate (NOR). The specific working principle is as follows:

[0024] The inverter is composed of a pair of N / PMOS transistors connected in series. The PMOS is connected between the power supply and output of the inverter structure, and the NMOS is connected between the output and ground of the inverter structure. The input of the inverter is the gate of the two transistors. When the input is low, the PMOS is turned on and the NMOS is turned off, and the output is connected to the power supply at a high level. When the input is high, the PMOS is turned off and the NMOS is turned on, and the output is connected to the ground at a low level, thus achieving an inverting effect; the NAND gate is composed of two pairs of N / PMOS transistors. The two PMOS are connected in parallel between the power supply and the output, and the two NMOS are connected in series between the output and the ground. The two inputs are connected to the gates of a pair of N / PMOS respectively. At this time, only when both inputs are high at the same time will the series NMOS be turned on at the same time and the output be grounded, realizing the NAND logic; the NOR gate is similar to the NAND gate, with two PMOS connected in series and two NMOS connected in parallel. Only when both inputs are low at the same time will the output be connected to the power supply at a high level, realizing the NOR logic.

[0025] A radio frequency identification (RFID) chip based on a TFT CMOS circuit using the hybrid material comprises five components: a ring oscillator, a frequency divider counter, a ROM, a decoder, and an encoder. All components of the chip are fabricated using the aforementioned CMOS process, enabling the continuous reading, encoding, and output of data from the ROM. The specific operating principle is as follows:

[0026] After receiving power, a ring oscillator consisting of an odd number of inverters connected end to end starts working and outputs a periodic waveform of a specific frequency; this waveform is input into an asynchronous frequency division counter composed of five D flip-flops for frequency division and shaping; then square waves of different frequencies are separated and input into the decoder, which continuously reads the data originally stored in the ROM in sequence; the data is finally shaped by a unipolar D flip-flop, input into the encoder for encoding, and then output.

[0027] Compared with the prior art, the present invention has the following advantages:

[0028] (1) The NMOS in the present invention has a top-gate structure, while the PMOS has a bottom-gate structure, which can fully utilize the advantages of both CNT and ZnO materials. ZnO cannot come into contact with water and oxygen, so a top-gate structure is used to bury it at the bottom. The P-type characteristics of CNT TFTs are partly related to the contact between the CNT in the channel and air, so a bottom-gate structure is used to place it at the top. At the same time, the different structures also avoid mutual influence on the process.

[0029] (2) The present invention will continue to make aluminum oxide after making zinc oxide, which will serve as a gate oxide layer on the one hand and protect the zinc oxide on the other hand. CNT is made last to avoid the influence between the two materials.

[0030] (3) The present invention uses two materials to make TFT CMOS, which has the advantages of low power consumption, large noise tolerance, high gain, simple structure and high integration compared to the commonly used enhancement type, depletion type and pseudo CMOS of TFT. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 Schematic diagram of a TFT made of two different materials, CNT and ZnO, according to Example 1 of the present invention;

[0032] Figure 2 It is a schematic diagram of the cross-sectional structure of a CMOS-based inverter made of a mixture of CNT and ZnO materials according to Example 2 of the present invention. DETAILED DESCRIPTION

[0033] In order to make the objectives, technical solutions and advantages of the present invention more clear, preferred embodiments are listed herewith and the present invention is further described in detail with reference to the accompanying drawings.

[0034] The present invention relates to a CMOS circuit and process technology based on a combination of TFTs made of two different materials, carbon nanotubes and zinc oxide. The TFTs made of the two different materials are simultaneously produced on a substrate after the entire process is completed, serving as P / NMOS. The P / NMOS have bottom-gate and top-gate structures, respectively. When they form a CMOS, they are interconnected through contact holes on a gate oxide layer. The entire process, from bottom to top, comprises ITO (NMOS source and drain, PMOS gate), ZnO (NMOS active layer), Al2O3 (gate oxide layer), ITO (NMOS gate), Au (PMOS source and drain), and CNT (PMOS active layer).

[0035] Example 1

[0036] like Figure 1 The left image shows a ZnO TFT with an aspect ratio of 5:5, a top-gate structure, where the gate is the topmost layer of the entire transistor. The right image shows a CNT TFT with an aspect ratio of 20:10, a bottom-gate structure, where the gate is the bottommost layer of the entire transistor. Transistors made of both materials will be fabricated simultaneously after the entire process is completed.

[0037] Example 2

[0038] like Figure 2This is a cross-sectional view of a TFT CMOS basic inverter that is a mixture of CNT and ZnO materials. The hybrid TFT CMOS inverter consists of a total of six thin film layers. First, ITO is deposited on a glass substrate and wet-etched to form the first layer of electrodes (including the source and drain electrodes of the NMOS and the gate electrode of the PMOS). Then, a ZnO active layer and an Al2O3 protective layer are grown on top, and then the active layer and protective layer are etched. An Al2O3 gate oxide layer is then grown on top and contact holes are etched. ITO is deposited and the electrode pattern is formed using a lift-off process to form the NMOS gate. Similarly, gold is deposited and patterned using a lift-off process to form the source and drain electrodes of the PMOS. Finally, CNTs are deposited by drop coating and then etched using oxygen plasma to form the channel.

[0039] The entire process involves six thin film depositions, six photolithography passes, four etching steps, and two lift-off steps. The channel layers of the P / NMOS in the inverter are made of carbon nanotubes and zinc oxide, respectively.

[0040] Example 3

[0041] Using the same process described in Example 2, a small- to medium-scale digital logic integrated circuit (such as an RFID tag chip) can be fabricated. This integrated circuit consists of approximately 300 transistors and includes a ring oscillator, D-type flip-flop, mask ROM, decoder, and encoder. The ring oscillator generates a global clock, which is divided and shaped by the D-type flip-flop before being output to various components. This allows the decoder to continuously read data from the ROM, input it to the encoder, and then encode and output it.

[0042] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope of the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A TFT CMOS logic circuit comprising a mixture of two semiconductor materials, carbon nanotubes (CNT) and zinc oxide (ZnO), characterized in that: The upper transistor of the CMOS logic circuit, namely the PMOS, has a bottom-gate structure, and the lower transistor of the CMOS logic circuit, namely the NMOS, has a top-gate structure; the PMOS and NMOS TFTs are connected between the power supply and the ground of the CMOS logic circuit; the input of the CMOS logic circuit is connected to the gates of the PMOS and NMOS TFTs, and the output of the CMOS logic circuit is connected to the junction of the PMOS and NMOS TFTs; The N / PMOS TFT includes a gate, a source, a drain electrode, an active layer and a gate oxide layer; The top gate structure has the source and drain electrodes at the bottom and the gate at the top; the bottom gate structure is the opposite; the two are connected by an etched through hole; The gate oxide layers of the N / PMOS TFT are aluminum oxide, the three electrodes of the NMOS TFT are ITO, the gate electrode of the PMOS TFT is ITO, and the source and drain electrodes are gold; the active layer of the PMOS TFT is CNT, and the active layer of the NMOS TFT is ZnO.

2. The CNT-ZnO hybrid TFT CMOS logic circuit according to claim 1, characterized in that: The CNT is a single-arm semiconductor carbon nanotube, which is structurally formed by curling a single layer of graphene. The band gap of the CNT is between 0.8 and 1.2 eV, the diameter distribution is 1.2-1.8 nm, and the length distribution is 0.8-3.2 μm.

3. The CNT-ZnO hybrid TFT CMOS logic circuit according to claim 1 or 2, characterized in that: The CMOS logic circuit can be used as a basic logic unit of any device including an inverter, a NAND gate, a NOR gate, an oscillator, and a trigger.

4. A method for preparing a CNT-ZnO hybrid TFT CMOS logic circuit according to claim 1 or 2, characterized in that: The specific steps are as follows: (1) Cleaning and drying the glass substrate; (2) ITO was deposited on a glass substrate by magnetron sputtering; (3) Etching electrodes on the ITO layer, which serves as the source and drain electrodes of the NMOS and the gate electrode of the PMOS; (4) A ZnO active layer and an Al2O3 protective layer are grown on top by ALD, and then etched to form the active layer of the NMOS; (5) ALD is then used to grow Al2O3 as the gate oxide layer of the N / PMOS, and through holes are etched to facilitate testing and to make top and bottom gate structure interconnections; (6) Depositing ITO by magnetron sputtering again and making the gate electrode of NMOS by lift-off process; (7) Depositing gold by magnetron sputtering and making the source and drain electrodes of PMOS by lift-off process; (8) dripping the CNT solution onto the structure obtained in step (7) and letting it stand for one day to allow the CNTs in the solution to fully settle; (9) The CNT is etched by oxygen plasma to retain the active layer of the PMOS, thereby obtaining the logic circuit.

5. The method for preparing a CNT-ZnO hybrid TFT CMOS logic circuit according to claim 4, characterized in that: The CNT solution is a semiconductor carbon nanotube solution using toluene as a solvent, with a CNT concentration of 10 ug / ml and a semiconductor purity of 99.99%.

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