A display panel, a preparation method thereof, and an electronic device

Abstract

The present disclosure provides a display panel, a manufacturing method thereof, and an electronic device. The display panel prepares a gate layer by using a first material with low resistance. While reducing the gate resistance in the display area, the second gate pattern in the peripheral area is used as an auxiliary electrode to effectively reduce the resistance voltage drop of the cathode, that is, the uniformity of the display panel in both the horizontal and vertical directions is achieved simultaneously, and the display effect of the display panel, especially the large-size display panel, is effectively improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof, and an electronic device. Background Art

[0002] In recent years, OLED (Organic Light-Emitting Diode), as a new type of display device, has attracted much attention due to its advantages such as self-luminescence, light weight, wide viewing angle, fast response time, high luminous efficiency, low driving voltage, low power consumption, simple manufacturing process and application in the field of flexible displays.

[0003] In the traditional top-emitting AMOLED (Active Matrix OLED, active matrix organic light-emitting diode), the cathode structure is crucial, and the thickness of the cathode directly determines the transmittance. For small-sized AMOLED, in order to ensure sufficient transmittance, the metal cathode is made very thin. Although the resistance of the cathode has an impact on the uniformity of the OLED panel, it is precisely because of the small size that the impact of the cathode resistance is within an acceptable range. However, for large-sized AMOLED, the metal cathode has a serious resistance voltage drop (IR drop), which leads to poor uniformity of the OLED panel and poor viewing effect, thereby affecting the application of this process method in large sizes. At the same time, due to the increase in the size of the display panel, the length of the gate line connected to the sub-pixel including the OLED light-emitting device becomes longer. Since the gate line itself has a certain resistance, the length of the gate line becomes longer, resulting in a larger gate line resistance, resulting in a delay in the scanning signal on the gate line, resulting in insufficient opening time of the thin film transistor (Thin Film Transistor, TFT) in the sub-pixel, and the display effect of the display panel is poor. Summary of the invention

[0004] The purpose of the embodiments of the present disclosure is to provide a display panel and a method for manufacturing the same, and an electronic device, so as to solve the problem of poor display effect caused by large resistance voltage drop and gate resistance in large-size OLED panels in the prior art.

[0005] Embodiments of the present disclosure adopt the following technical solutions: A display panel includes at least the following layers sequentially arranged from bottom to top: a substrate, the substrate includes a display area and a peripheral area surrounding the display area; a semiconductor layer, the semiconductor layer is disposed in the display area; a first insulating layer, the first insulating layer completely covers the semiconductor layer; a gate layer, the gate layer includes a first gate pattern formed in the display area and a second gate pattern formed in the peripheral area, the first gate pattern and the second gate pattern are insulated from each other, a positive projection of the first gate pattern on the substrate is completely covered by a positive projection of the semiconductor layer on the substrate, and the gate layer is made of a first material with a resistivity less than a first preset value; a second insulating layer, the second insulating layer completely covers the gate layer; a metal layer, the metal layer includes a first metal pattern and a second metal pattern formed in the display area, the first metal pattern and the second metal pattern are insulated from each other, and the first metal pattern is connected to the semiconductor layer based on a first through hole, the second metal pattern is connected to the semiconductor layer through a second through hole, and both the first through hole and the second through hole penetrate the first insulating layer and the second insulating layer; a third insulating layer, the third insulating layer completely covers the metal layer; an anode layer, the anode layer includes a plurality of anode units located in the display area; a pixel definition layer, the pixel definition layer is provided with a plurality of pixel openings penetrating the pixel definition layer, a positive projection of the pixel opening on the substrate is located within a positive projection of the anode unit on the substrate; an organic light-emitting layer, the organic light-emitting layer includes a plurality of light-emitting units, the light-emitting units are located within the pixel openings; a cathode layer, the cathode layer covers the pixel openings and the light-emitting units, there is an overlapping area between a positive projection of the cathode layer on the substrate and a positive projection of the second gate pattern on the substrate, and the cathode layer is connected to the second gate pattern through a third through hole, the third through hole penetrates the second insulating layer and the third insulating layer.

[0006] In some embodiments, the first preset value is 3 uΩ·cm.

[0007] In some embodiments, the first material includes at least any one metal or an alloy of multiple metals among aluminum, gold, silver, and copper.

[0008] In some embodiments, the second gate pattern is a rectangular ring surrounding the display area.

[0009] In some embodiments, the metal layer further includes a third metal pattern formed in the peripheral region. There is an overlapping area between the orthographic projection of the third metal pattern on the substrate and the orthographic projection of the second gate pattern on the substrate. The third metal pattern is connected to the second gate pattern through a fourth via hole, and the cathode layer is connected to the third metal pattern through a fifth via hole. Wherein, the fourth via hole penetrates through the second insulating layer, and the fifth via hole penetrates through the third insulating layer.

[0010] An embodiment of the present disclosure further includes a method for manufacturing a display panel, comprising: providing a substrate, the substrate including a display area and a peripheral area surrounding the display area; manufacturing a semiconductor layer in the display area; manufacturing a first insulating layer on the surface of the substrate, the first insulating layer completely covering the semiconductor layer; manufacturing a gate layer on the surface of the first insulating layer away from the substrate based on a first material having a resistivity less than a first preset value, wherein the gate layer includes a first gate pattern formed in the display area and a second gate pattern formed in the peripheral area, the first gate pattern and the second gate pattern being insulated from each other, and a positive projection of the first gate pattern on the substrate being completely covered by a positive projection of the semiconductor layer on the substrate; manufacturing a second insulating layer on the surface of the gate layer away from the first insulating layer, the second insulating layer completely covering the gate layer; opening a first through hole and a second through hole in the display area, the first through hole and the second through hole penetrating through the first insulating layer and the second insulating layer, and a positive projection of the first through hole and the second through hole on the substrate coinciding with a positive projection of the semiconductor layer on the substrate; manufacturing a metal layer on the surface of the second insulating layer away from the gate layer, the metal layer including a first metal pattern and a second metal pattern formed in the display area, the first metal pattern and the second metal pattern being insulated from each other, the first metal pattern being connected to the semiconductor layer based on the first through hole, and the second metal pattern being connected to the semiconductor layer through the second through hole; manufacturing a third insulating layer on the surface of the metal layer away from the second insulating layer, the third insulating layer completely covering the metal layer; manufacturing an anode layer on the surface of the third insulating layer away from the metal layer, the anode layer including a plurality of anode units located in the display area; manufacturing a pixel definition layer on the surface of the anode layer away from the third insulating layer and opening a plurality of pixel openings penetrating through the pixel definition layer, a positive projection of the pixel openings on the substrate being located within a positive projection of the anode units on the substrate; opening a third through hole in the peripheral area, the third through hole penetrating through the second insulating layer and the third insulating layer, and a positive projection of the third through hole on the substrate coinciding with a positive projection of the second gate pattern on the substrate; manufacturing an organic light-emitting layer, the organic light-emitting layer including a plurality of light-emitting units, the light-emitting units being located within the pixel openings; manufacturing a cathode layer, the cathode layer covering the pixel openings and the light-emitting units, a positive projection of the cathode layer on the substrate having an overlapping area with a positive projection of the second gate pattern on the substrate, and the cathode layer being connected to the second gate pattern through the third through hole.

[0011] In some embodiments, the first material includes at least any one metal or an alloy of multiple metals among aluminum, gold, silver, and copper.

[0012] In some embodiments, the second gate pattern is a rectangular ring surrounding the display area.

[0013] In some embodiments, after forming a second insulating layer on a surface of the gate layer away from the first insulating layer, the method further includes: forming a fourth through hole in the peripheral area, the fourth through hole penetrating the second insulating layer, and there being an overlapping area between a positive projection of the fourth through hole on the substrate and a positive projection of the second gate pattern on the substrate; forming the metal layer on a surface of the second insulating layer located in the peripheral area, the metal layer at least including a third metal pattern, the third metal pattern being connected to the second gate pattern through the fourth through hole; forming a third insulating layer on a surface of the metal layer away from the second insulating layer and forming a fifth through hole, the fifth through hole penetrating the third insulating layer, and there being an overlapping area between a positive projection of the fifth through hole on the substrate and a positive projection of the third metal pattern on the substrate; sequentially forming the anode layer, the organic light-emitting layer, and the cathode layer, the cathode layer being connected to the third metal pattern through the fifth through hole.

[0014] An embodiment of the present disclosure further includes an electronic device, at least including the display panel as described above.

[0015] The beneficial effects of the embodiments of the present disclosure are as follows: By using the first material with low resistance to form the gate layer simultaneously, while reducing the gate resistance in the display area, the second gate pattern in the peripheral area is used as an auxiliary electrode to effectively reduce the resistance voltage drop of the cathode, that is, the uniformity of the display panel in both the horizontal and vertical directions is achieved simultaneously, and the display effect of the display panel, especially the large-size display panel, is effectively improved. Description of the Drawings

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments recorded in the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0017] Figure 1 It is a schematic diagram of the hierarchical structure of the display panel in the first embodiment of the present disclosure;

[0018] Figure 2 It is another schematic diagram of the hierarchical structure of the display panel in the first embodiment of the present disclosure;

[0019] Figure 3 It is a flowchart of the method for manufacturing the display panel in the second embodiment of the present disclosure. Detailed Embodiments

[0020] The various aspects and features of the present disclosure are described herein with reference to the accompanying drawings.

[0021] It should be understood that various modifications can be made to the embodiments applied herein. Therefore, the above description should not be regarded as limiting, but merely as an example of the embodiments. Those skilled in the art will think of other modifications within the scope and spirit of the present disclosure.

[0022] The accompanying drawings, which are included in and form a part of this specification, illustrate embodiments of the present disclosure and, together with the general description of the present disclosure given above and the detailed description of the embodiments given below, serve to explain the principles of the present disclosure.

[0023] These and other features of the present disclosure will become apparent from the following description of the preferred forms of the embodiments, given by way of non-limiting example with reference to the accompanying drawings.

[0024] It should also be understood that although the present disclosure has been described with reference to some specific examples, those skilled in the art can surely implement many other equivalent forms of the present disclosure, which have the features as claimed and thus are all within the scope of protection defined thereby.

[0025] When combined with the accompanying drawings, the above and other aspects, features and advantages of the present disclosure will become more apparent in view of the following detailed description.

[0026] Specific embodiments of the present disclosure are hereinafter described with reference to the accompanying drawings; however, it should be understood that the embodiments applied are merely examples of the present disclosure and can be implemented in various ways. Well-known and / or repetitive functions and structures are not described in detail to avoid obscuring the present disclosure with unnecessary or redundant details. Therefore, the specific structural and functional details applied herein are not intended to be limiting, but merely as a basis and representative basis for the claims to teach those skilled in the art to use the present disclosure in substantially any suitable detailed structure in a variety of ways.

[0027] This specification may use the phrases "in one embodiment", "in another embodiment", "in yet another embodiment" or "in other embodiments", which may each refer to one or more of the same or different embodiments according to the present disclosure.

[0028] In recent years, as a new type of display device, OLED has attracted much attention due to its advantages such as self-luminescence, light weight, wide viewing angle, fast response time, high luminous efficiency, low driving voltage, low power consumption, simple manufacturing process, and the ability to be applied to the field of flexible displays.

[0029] In a traditional top-emission structure AMOLED, the cathode structure is crucial, and the thickness of the cathode directly determines the light transmittance. For small-size AMOLEDs, in order to ensure sufficient light transmittance, the metal cathode is made very thin. Although the resistance of the cathode has an impact on the uniformity of the OLED panel, due to the small size, the influence of the cathode resistance is within an acceptable range. However, for large-size AMOLEDs, due to severe resistance voltage drop (IR drop) of the metal cathode, the uniformity of the OLED panel is poor, the viewing effect is not good, and thus the application of this process method in large sizes is affected. Currently, the following two main solutions are used in conventional technologies to solve the voltage drop problem:

[0030] Solution 1: Use transparent metal oxides such as indium zinc oxide (IZO) as the cathode. Since the thin film material of the transparent metal oxide has a high transmittance, even when the thickness is large, its resistance can meet the performance requirements of the device. However, since the transparent metal oxide material needs to be prepared by processes such as sputtering, and the energy during sputtering is large, it is easy to damage the organic material layer in the OLED device, thereby affecting the injection efficiency, lifespan and other performances of the OLED device. Therefore, the method of using transparent metal oxides as the cathode is also limited.

[0031] Solution 2: Use CPM organic materials and modified magnesium metal materials provided by a specific company. The CPM material is evaporated onto the light-emitting area through the FMM, and the modified Mg material is evaporated through the Open Mask. By using the mutually exclusive characteristics of the modified Mg material and the CPM organic material, it is realized that the modified Mg only adheres to the non-light-emitting area, that is, the patterning of the modified Mg, to achieve an auxiliary cathode. However, the CPM material remains in the light-emitting area, which will affect the light extraction to a certain extent and the light-emitting efficiency of the device.

[0032] At the same time, due to the increase in the size of the display panel, the length of the gate line routing connected to the sub-pixels including the OLED light-emitting device becomes longer. Since the gate line itself has a certain resistance, the increase in the routing length of the gate line results in an increase in the gate line resistance, resulting in a delay in the scanning signal on the gate line and insufficient turn-on time of the thin film transistor in the sub-pixel, and the display effect of the display panel is poor.

[0033] To solve the above problems, the first embodiment of the present disclosure provides a display panel, mainly an OLED display panel. By improving the structure of the OLED display panel, the gate resistance and the cathode voltage drop are reduced at the same time, thereby ensuring that the display panel presents a uniform display effect.

[0034] Figure 1 Shows the schematic diagram of the hierarchical structure of the display panel in this embodiment. As Figure 1As shown, the display panel mainly includes a substrate 100, a semiconductor layer 210, a first insulating layer 220, a gate layer 230, a second insulating layer 240, a metal layer 250, a third insulating layer 260, an anode layer 310, a pixel definition layer 320, an organic light-emitting layer 330, and a cathode layer 340, which are sequentially arranged from bottom to top. Specifically, the substrate 100 includes a display area and a peripheral area surrounding the display area. Figure 1 To the left of the dashed line in Figure 1 is the display area, and to the right of the dashed line is the peripheral area; in the display area, the semiconductor layer 210, the first insulating layer 220, the gate layer 230, the second insulating layer 240, the metal layer 250, and the third insulating layer 260 are correspondingly arranged to form a driving control structure of a pixel unit, that is, a TFT structure. The anode layer 310, the pixel definition layer 320, the organic light-emitting layer 330, and the cathode layer 340 form pixel units in the display area to emit light under the control of the TFT to achieve a display effect; while the peripheral area is mainly used to set various traces, including but not limited to data lines, gate control lines, etc. (not shown in the figure).

[0035] In this embodiment, the semiconductor layer 210 is mainly arranged in the display area part on the surface of the substrate 100; the first insulating layer 220 mainly serves as a gate insulating layer GI, which covers the entire substrate 100 during preparation and realizes the encapsulation of the semiconductor layer 210; the gate layer 230 is arranged in both the display area and the peripheral area during preparation, and different patterns are formed in the display area and the peripheral area respectively. Among them, the gate layer 230 forms a first gate pattern 231 in the display area according to the setting of the pixel unit. The orthographic projection of the first gate pattern 231 on the substrate 100 is located within the orthographic projection of the semiconductor layer 210 on the substrate 100 to form a channel on the semiconductor layer 210 when the gate is energized to turn on the TFT; the gate layer 230 forms a second gate pattern 232 in the peripheral area. Using the second gate pattern 232 as an auxiliary electrode of the display panel, after connecting with the cathode layer 340, it is used to reduce the IR Drop of the cathode layer 340, thereby improving the uniformity of the display of the display panel.

[0036] Furthermore, when preparing the gate layer 230, a first material with a resistivity less than a first preset value should be selected for preparation to reduce the resistance of the first gate pattern 231 used as a gate line, thereby reducing the gate scan signal delay time, ensuring sufficient gate opening time, and improving the brightness uniformity of the display panel when the pixel units at various positions in the display panel have substantially the same lighting time; especially for large-size display panels with bilateral driving (i.e., gate control signals are input simultaneously on the left and right sides of the screen), it is possible to avoid inconsistent horizontal display such as color differences between the middle and the edges of the display panel caused by the shorter gate opening time in the middle of the display panel than that at the edges (mainly the left and right edges). At the same time, the second gate pattern 232 prepared using the first material also has a relatively low resistance. After it is connected to the cathode layer 340, its low-resistance characteristic can effectively reduce the IR Drop of the cathode, further improving the display uniformity of the display panel.

[0037] For the conventional TFT gate, metal molybdenum (Mo) is mainly selected for preparation. The resistivity of molybdenum is 5.2 Ω·cm, and after it is made into a relatively thin metal film layer, its film resistivity increases to 13.86 μΩ·cm. In the actual implementation of this embodiment, the first preset value can be set to 3 μΩ·cm. That is, when selecting the first material, a metal material or alloy material with a resistivity below 3 μΩ·cm is mainly selected. For example, the first material can be any one or a combination of aluminum (Al), gold (Au), silver (Ag), and copper (Cu). When using the same preparation process to prepare metal film layers of the same thickness, the maximum film resistivity of the above materials is only 5 μΩ·cm, which is much lower than that of the commonly used metal molybdenum, achieving a significant reduction in resistivity. At the same time, through test verification, compared with the conventional structure, the cathode voltage drop of the display panel structure provided by this embodiment is reduced by 53%, and the overall power consumption of the display panel is also reduced by 9%. While improving the display effect uniformity, it reduces the product energy consumption and enhances the product competitiveness.

[0038] The second insulating layer 240 is used as an interlayer insulating layer ILD covering the gate layer 230; a metal layer 250 is provided on the surface of the second insulating layer 240. The metal layer 250 forms a first metal pattern 251 and a second metal pattern 252 that are insulated from each other in the display area, which are used as the source and drain of the TFT structure respectively. One end of the source and drain is connected to the data line, and the other end is connected to the anode of the pixel unit. Under the control of the first gate pattern 231, the signal input from the data line is transmitted to the anode to light up the pixel. Among them, the first metal pattern 251 is connected to the semiconductor layer 210 through a first through hole 51, and the second metal pattern 252 is connected to the semiconductor layer 210 through a second through hole 52. Both the first through hole 51 and the second through hole 52 are through holes penetrating the first insulating layer 220 and the second insulating layer 240, but it should be ensured that the positions where they are opened avoid the position of the first gate pattern 231 to ensure insulation between the metal layer 250 and the gate layer 230.

[0039] A third insulating layer 260 is further provided on the surface of the metal layer 250, which is mainly used as a planarization layer PDL. The flat surface formed after the preparation of the third insulating layer 260 facilitates the preparation of each layer of the pixel unit. Specifically, the anode layer 310 includes a plurality of anode units 311 located in the display area. Each anode unit 311 corresponds to a pixel unit, and its specific position can be set according to actual needs. The anode unit 311 is connected to any one of the metal patterns through a through hole penetrating the third insulating layer, such as Figure 1 the anode unit 311 is connected to the second metal pattern 252 in the figure; the pixel definition layer 320 is located on the side of the anode layer 310 away from the third insulating layer 260, and after its preparation, a plurality of pixel openings 321 penetrating the pixel definition layer 320 are opened. The orthographic projection of the pixel openings 321 on the substrate 100 is located within the orthographic projection of the anode unit 311 on the substrate 100, that is, by opening the pixel openings 321, the surface of the anode unit 311 is exposed, and the light-emitting unit 331 is prepared in each pixel opening 321 to form the organic light-emitting layer 330.

[0040] The cathode layer 340 is a surface electrode. When it is prepared, it can cover all the pixel openings 321 and the light-emitting units 331 at the same time, and the covered position extends to the peripheral area, so that there is an overlapping area between the orthographic projection of the cathode layer 340 on the substrate 100 and the orthographic projection of the second gate pattern 232 on the substrate 100. A third through hole 53 penetrating the second insulating layer 240 and the third insulating layer 260 is opened in the overlapping area of the two projections, so that when the cathode layer 340 is prepared, it can be directly connected to the second gate pattern 232 based on the third through hole 53, realizing the reduction of the IR Drop of the auxiliary electrode to the cathode layer 340.

[0041] In this embodiment, the gate layer is prepared by using the first material with low resistance. While reducing the gate resistance in the display area, the second gate pattern in the peripheral area is used as an auxiliary electrode to effectively reduce the resistance voltage drop of the cathode, that is, the uniformity of the display panel in both the horizontal and vertical directions is achieved simultaneously, and the display effect of the display panel, especially the large-size display panel, is effectively improved.

[0042] In actual implementation, the second gate pattern 232 is a rectangular ring formed around the display area, and the corresponding third through hole 53 is opened as a rectangular ring-shaped groove, so that the cathode layer 340 can be tightly connected to the second gate pattern 232 during preparation, so as to improve the effect of the auxiliary electrode on reducing the cathode voltage drop.

[0043] Figure 2 Another schematic diagram of the hierarchical structure of the display panel according to this embodiment is shown. As Figure 2 shown, the hierarchical structure in its display area is the same as Figure 1 and will not be repeated here. In the peripheral area of the display panel shown in Figure 2 , the metal layer 250 forms a third metal pattern 253 in the peripheral area, so that there is an overlapping area between the orthographic projection of the third metal pattern 253 on the substrate 100 and the orthographic projection of the second gate pattern 232 on the substrate 100, and the connection between the third metal pattern 253 and the second gate pattern 232 is realized through the fourth through hole 54 penetrating the second insulating layer 240. At this time, a fifth through hole 55 penetrating the third insulating layer 260 is opened on the third insulating layer 260 to realize the connection between the cathode layer 340 and the third metal pattern 253 through the fifth through hole 55 during preparation. At this time, the third metal layer 253 is used as a jump to realize the connection between the cathode layer 340 and the second gate pattern 232. It should be noted that, using the Figure 2 shown hierarchical structure, in actual implementation, the voltage drop reduction effect of the cathode 340 may be slightly lower than that of the Figure 1 shown structure due to the resistivity of the metal layer 250. However, the third through hole 53 needs to penetrate two insulating layers simultaneously during preparation, and the preparation of the third through hole 53 is relatively difficult in terms of the preparation process, while the preparation processes of the fourth through hole 54 and the fifth through hole 55 only need to penetrate one insulating layer respectively. Therefore, the Figure 2 shown structure is simpler during preparation. In actual use, manufacturers can choose to use the Figure 1 shown structure or the Figure 2 shown structure according to process conditions and actual requirements.

[0044] Based on the same inventive concept, the second embodiment of the present disclosure provides a method for manufacturing a display panel. As Figure 3 shown, the method for manufacturing the display panel includes:

[0045] S301. Provide a substrate, where the substrate includes a display area and a peripheral area surrounding the display area, and prepare a semiconductor layer in the display area;

[0046] S302. Prepare a first insulating layer on the surface of the substrate, and the first insulating layer completely covers the semiconductor layer;

[0047] S303. Prepare a gate layer on the surface of the first insulating layer away from the substrate based on a first material with a resistivity less than a first preset value. Wherein, the gate layer includes a first gate pattern formed in the display area and a second gate pattern formed in the peripheral area, and the first gate pattern and the second gate pattern are insulated from each other. The orthographic projection of the first gate pattern on the substrate is completely covered by the orthographic projection of the semiconductor layer on the substrate;

[0048] S304. Prepare a second insulating layer on the surface of the gate layer away from the first insulating layer, and the second insulating layer completely covers the gate layer;

[0049] S305. Open a first through hole and a second through hole in the display area, penetrating through the first insulating layer and the second insulating layer. The orthographic projections of the first through hole and the second through hole on the substrate coincide with the orthographic projection of the semiconductor layer on the substrate;

[0050] S306. Prepare a metal layer on the surface of the second insulating layer away from the gate layer. The metal layer includes a first metal pattern and a second metal pattern formed in the display area, and the first metal pattern and the second metal pattern are insulated from each other. The first metal pattern is connected to the semiconductor layer based on the first through hole, and the second metal pattern is connected to the semiconductor layer through the second through hole;

[0051] S307. Prepare a third insulating layer on the surface of the metal layer away from the second insulating layer, and the third insulating layer completely covers the metal layer;

[0052] S308. Prepare an anode layer on the surface of the third insulating layer away from the metal layer. The anode layer includes a plurality of anode units located in the display area;

[0053] S309. Prepare a pixel defining layer on the surface of the anode layer away from the third insulating layer, and open a plurality of pixel openings penetrating through the pixel defining layer. The orthographic projections of the pixel openings on the substrate are located within the orthographic projections of the anode units on the substrate;

[0054] S310. Open a third through hole in the peripheral area, penetrating through the second insulating layer and the third insulating layer. The orthographic projection of the third through hole on the substrate coincides with the orthographic projection of the second gate pattern on the substrate;

[0055] S311. Prepare an organic light-emitting layer, where the organic light-emitting layer includes a plurality of light-emitting units, and the light-emitting units are located within the pixel openings;

[0056] S312. Prepare a cathode layer that covers the pixel openings and the light-emitting units. There is an overlapping area between the orthographic projection of the cathode layer on the substrate and the orthographic projection of the second gate pattern on the substrate, and the cathode layer is connected to the second gate pattern through a third via hole.

[0057] In this embodiment, the gate layer is prepared simultaneously with the first material having a low resistance. While reducing the gate resistance in the display area, the second gate pattern in the peripheral area is used as an auxiliary electrode to effectively reduce the resistance voltage drop of the cathode, that is, the uniformity of the horizontal and vertical displays of the display panel is achieved simultaneously, effectively improving the display effect of the display panel, especially the large-size display panel.

[0058] It should be noted that step S310 can be implemented after S309 or after the third insulating layer is formed after S307 is executed. As long as it is ensured that the third via hole is opened after the third insulating layer is prepared and before the cathode layer is prepared. In addition, regarding the preparation process used in the preparation of the above-mentioned layers, conventional evaporation, deposition and other preparation processes can be directly used, and only the shape of the mask plate needs to be adjusted according to the different patterns formed by different layers. Especially for the gate layer prepared with the first material, good film layer preparation can also be achieved by directly using the evaporation method, without using preparation methods such as sputtering that may damage other layer structures.

[0059] In some embodiments, the first material includes at least any one metal or an alloy of multiple metals among aluminum, gold, silver, and copper. In some embodiments, the second gate pattern is a rectangular ring surrounding the display area.

[0060] During actual execution Figure 3 When implementing the shown preparation method, after the second insulating layer is prepared, a fourth via hole can also be opened in its corresponding peripheral area to penetrate the second insulating layer, and there is an overlapping area between the orthographic projection of the fourth via hole on the substrate and the orthographic projection of the second gate pattern on the substrate; subsequently, when the metal layer is prepared, a third metal pattern is formed in the peripheral area, and the third metal pattern is connected to the second gate pattern through the fourth via hole; correspondingly, after the third insulating layer is formed, a fifth via hole is opened in the peripheral area within the third insulating layer to penetrate the third insulating layer, and there is an overlapping area between the orthographic projection of the fifth via hole on the substrate and the orthographic projection of the third metal pattern on the substrate. Subsequently, the anode layer, the organic light-emitting layer, and the cathode layer are prepared in sequence, and the cathode layer is connected to the third metal pattern through the fifth via hole, so as to realize the connection between the cathode layer and the second gate pattern through the third metal pattern as a jump.

[0061] The third embodiment of the present disclosure provides an electronic device, which can be any device with a display function, especially a television, a computer monitor, etc. with a large-size display requirement. The electronic device in this embodiment at least includes the display panel provided in the first embodiment of the present disclosure, so that a better display effect can be presented on the display screen of the electronic device. At the same time, in addition to the display panel, other hardware structures included in the electronic device can be set according to the actual functional requirements of the electronic device, and this embodiment does not make detailed restrictions.

[0062] The above has described multiple embodiments of the present disclosure in detail, but the present disclosure is not limited to these specific embodiments. Those skilled in the art can make various variations and modifications to the embodiments based on the concept of the present disclosure, and these variations and modifications should all fall within the scope required to be protected by the present disclosure.

Claims

1. A display panel, characterized in that, At least include the following levels arranged from bottom to top: A substrate, the substrate including a display area and a peripheral area surrounding the display area; A semiconductor layer, the semiconductor layer being disposed in the display area; A first insulating layer, the first insulating layer completely covering the semiconductor layer; A gate layer, the gate layer including a first gate pattern formed in the display area and a second gate pattern formed in the peripheral area, the first gate pattern and the second gate pattern being insulated from each other, a positive projection of the first gate pattern on the substrate being completely covered by a positive projection of the semiconductor layer on the substrate, and the gate layer being made of a first material having a resistivity less than a first preset value; A second insulating layer, the second insulating layer completely covering the gate layer; A metal layer, the metal layer including a first metal pattern and a second metal pattern formed in the display area, the first metal pattern and the second metal pattern being insulated from each other, and the first metal pattern being connected to the semiconductor layer based on a first through hole, the second metal pattern being connected to the semiconductor layer through a second through hole, both the first through hole and the second through hole penetrating through the first insulating layer and the second insulating layer; A third insulating layer, the third insulating layer completely covering the metal layer; An anode layer, the anode layer including a plurality of anode units located in the display area; A pixel defining layer, the pixel defining layer being provided with a plurality of pixel openings penetrating through the pixel defining layer, a positive projection of the pixel openings on the substrate being located within a positive projection of the anode units on the substrate; An organic light emitting layer, the organic light emitting layer including a plurality of light emitting units, the light emitting units being located within the pixel openings; A cathode layer, the cathode layer covering the pixel openings and the light emitting units, a positive projection of the cathode layer on the substrate having an overlapping area with a positive projection of the second gate pattern on the substrate, and the cathode layer being connected to the second gate pattern through a third through hole, the third through hole penetrating through the second insulating layer and the third insulating layer.

2. The display panel according to claim 1, wherein The first preset value is 3 uΩ·cm.

3. The display panel according to claim 1, wherein The first material at least includes any one metal or an alloy of multiple metals among aluminum, gold, silver, and copper.

4. The display panel according to claim 1, wherein The second gate pattern is a rectangular ring surrounding the display area.

5. The display panel according to any one of claims 1 to 4, characterized in that, The metal layer further includes a third metal pattern formed in the peripheral area, a positive projection of the third metal pattern on the substrate having an overlapping area with a positive projection of the second gate pattern on the substrate, the third metal pattern being connected to the second gate pattern through a fourth through hole, the cathode layer being connected to the third metal pattern through a fifth through hole, wherein the fourth through hole penetrates through the second insulating layer, and the fifth through hole penetrates through the third insulating layer.

6. A method for manufacturing a display panel, characterized in that, Including: Providing a substrate, the substrate including a display area and a peripheral area surrounding the display area; Preparing a semiconductor layer in the display area; Preparing a first insulating layer on the surface of the substrate, the first insulating layer completely covering the semiconductor layer; A gate layer is prepared on the surface of the first material with a resistivity less than a first preset value on the side of the first insulating layer away from the substrate. The gate layer includes a first gate pattern formed in the display area and a second gate pattern formed in the peripheral area. The first gate pattern and the second gate pattern are insulated from each other, and the orthographic projection of the first gate pattern on the substrate is completely covered by the orthographic projection of the semiconductor layer on the substrate. A second insulating layer is prepared on the surface of the gate layer on the side away from the first insulating layer, and the second insulating layer completely covers the gate layer. A first through hole and a second through hole are opened in the display area, penetrating through the first insulating layer and the second insulating layer. The orthographic projections of the first through hole and the second through hole on the substrate coincide with the orthographic projection of the semiconductor layer on the substrate. A metal layer is prepared on the surface of the second insulating layer on the side away from the gate layer. The metal layer includes a first metal pattern and a second metal pattern formed in the display area. The first metal pattern and the second metal pattern are insulated from each other. The first metal pattern is connected to the semiconductor layer based on the first through hole, and the second metal pattern is connected to the semiconductor layer through the second through hole. A third insulating layer is prepared on the surface of the metal layer on the side away from the second insulating layer, and the third insulating layer completely covers the metal layer. An anode layer is prepared on the surface of the third insulating layer on the side away from the metal layer. The anode layer includes a plurality of anode units located in the display area. A pixel definition layer is prepared on the surface of the anode layer on the side away from the third insulating layer, and a plurality of pixel openings penetrating through the pixel definition layer are opened. The orthographic projections of the pixel openings on the substrate are located within the orthographic projections of the anode units on the substrate. A third through hole is opened in the peripheral area, penetrating through the second insulating layer and the third insulating layer. The orthographic projection of the third through hole on the substrate coincides with the orthographic projection of the second gate pattern on the substrate. An organic light-emitting layer is prepared. The organic light-emitting layer includes a plurality of light-emitting units, and the light-emitting units are located within the pixel openings. A cathode layer is prepared. The cathode layer covers the pixel openings and the light-emitting units. There is an overlapping area between the orthographic projection of the cathode layer on the substrate and the orthographic projection of the second gate pattern on the substrate, and the cathode layer is connected to the second gate pattern through the third through hole.

7. The preparation method according to claim 6, characterized in that, The first material includes at least any one metal or an alloy of multiple metals among aluminum, gold, silver, and copper.

8. The preparation method according to claim 6, characterized in that, The second gate pattern is a rectangular ring surrounding the display area.

9. The preparation method according to any one of claims 6 to 8, characterized in that, After preparing the second insulating layer on the surface of the gate layer on the side away from the first insulating layer, it further includes: A fourth through hole is opened in the peripheral area, penetrating through the second insulating layer. There is an overlapping area between the orthographic projection of the fourth through hole on the substrate and the orthographic projection of the second gate pattern on the substrate. The metal layer is fabricated on the surface of the second insulating layer located in the peripheral region. The metal layer includes at least a third metal pattern, and the third metal pattern is connected to the second gate pattern through the fourth through hole. A third insulating layer is fabricated on the surface of the metal layer away from the second insulating layer, and a fifth through hole is formed. The fifth through hole penetrates the third insulating layer, and there is an overlapping area between the orthographic projection of the fifth through hole on the substrate and the orthographic projection of the third metal pattern on the substrate. The anode layer, the organic light-emitting layer, and the cathode layer are sequentially fabricated, and the cathode layer is connected to the third metal pattern through the fifth through hole.

10. An electronic device, characterized in that, It includes at least the display panel according to any one of claims 1 to 5.

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