Slope generation circuit

Abstract

Embodiments of the present disclosure provide a ramp generation circuit, belonging to the field of integrated circuit technology. The ramp generation circuit includes: a clock selection circuit configured to obtain a second clock signal and a clock selection signal based on a frequency selection signal and a first clock signal, and provide the second clock signal to a ramp voltage output circuit via a first node, and provide the clock selection signal to a PWM signal output circuit via a second node; a ramp voltage output circuit configured to obtain a ramp voltage signal based on the frequency selection signal, the first clock signal, and the second clock signal, and provide the ramp voltage signal to the PWM signal output circuit via a third node; a PWM signal output circuit configured to output a PWM signal corresponding to the frequency selection signal from a signal output terminal according to a comparison result between an output voltage signal of an error amplifier and the ramp voltage signal, and the clock selection signal. Embodiments of the present disclosure are applicable to the generation process of PWM signals in a boost-type DC-DC system.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of integrated circuits, and in particular to a ramp generating circuit. Background Art

[0002] In a boost DC-DC system, the loop needs to pass the output voltage V of the error amplifier EA. EAO With the ramp voltage V RAMP Comparison is performed to generate a PWM (Pulse Width Modulation) signal. In some application scenarios, such as LED drivers and battery charging chips, the DC-DC output voltage V OUT There is a process of slowly increasing from low voltage, and the power stage drive signal will have an extreme duty cycle (that is, the duty cycle is close to 0), so the PWM signal duty cycle is extremely small, causing the NMOS power tube to be close to not open or critically open. In this case, the PWM comparator is still required to generate a stable wave, otherwise V OUT It is easy to generate ripples of varying sizes. In addition, in engineering applications, in order to balance system efficiency and output voltage ripple, the frequency of the PWM signal needs to be optional and require high frequency accuracy. In order to output PWM signals of different frequencies, V RAMP , so the ramp generating circuit needs to be improved. Summary of the Invention

[0003] An object of the embodiments of the present disclosure is to provide a ramp generating circuit that generates different clock signals and corresponding ramp voltage signals without increasing the circuit structure, thereby realizing a predictable PWM signal.

[0004] To achieve the above-mentioned objectives, an embodiment of the present disclosure provides a ramp generation circuit, comprising: a clock selection circuit, a ramp voltage output circuit, and a pulse width modulation (PWM) signal output circuit. The clock selection circuit is configured to obtain a second clock signal and a clock selection signal based on a frequency selection signal and a first clock signal, and to provide the second clock signal to the ramp voltage output circuit via a first node, and to provide the clock selection signal to the PWM signal output circuit via a second node. The ramp voltage output circuit is configured to obtain a ramp voltage signal based on the frequency selection signal, the first clock signal, and the second clock signal, and to provide the ramp voltage signal to the PWM signal output circuit via a third node. The PWM signal output circuit is configured to output a PWM signal corresponding to the frequency selection signal from a signal output terminal based on a comparison result of an output voltage signal of an error amplifier with the ramp voltage signal and the clock selection signal.

[0005] In some embodiments of the present disclosure, the clock selection circuit includes: a first inverter, a D flip-flop, a first NAND gate, and a data selector. Wherein, an input end of the first inverter is coupled to a first clock signal input end, and an output end of the first inverter is coupled to a clock input end of the D flip-flop; a D signal input end of the D flip-flop is coupled to a non-Q output end of the D flip-flop, and a reset end of the D flip-flop is coupled to a frequency selection signal input end; a first input end of the first NAND gate is coupled to the non-Q output end of the D flip-flop, a second input end of the first NAND gate is coupled to the first clock signal input end, and an output end of the first NAND gate is coupled to the first node; a control end of the data selector is coupled to the frequency selection signal input end, a first input end of the data selector is coupled to the first clock signal input end, a second input end of the data selector is coupled to the first node, and an output end of the data selector is coupled to the second node.

[0006] In some embodiments of the present disclosure, the ramp voltage output circuit includes: a ramp voltage control circuit and a ramp voltage selection circuit. Wherein, the ramp voltage control circuit is configured to obtain a ramp voltage low-level control signal according to the frequency selection signal, the first clock signal, and the second clock signal, and provide the ramp voltage low-level control signal to the ramp voltage selection circuit via a fourth node; the ramp voltage selection circuit is configured to obtain the ramp voltage signal corresponding to the frequency selection signal according to the frequency selection signal and the ramp voltage low-level control signal.

[0007] In some embodiments of the present disclosure, the ramp voltage control circuit includes: a second inverter, a first negative pulse flip-flop, a third inverter, a first OR gate, a fourth inverter, a second negative pulse flip-flop, a second NAND gate, and a first AND gate. Wherein, an input end of the second inverter is coupled to the first node, and an output end of the second inverter is coupled to an input end of the first negative pulse flip-flop; an output end of the first negative pulse flip-flop is coupled to an input end of the third inverter; an output end of the third inverter is coupled to a first input end of the first OR gate; a second input end of the first OR gate is coupled to a frequency selection signal input end, and an output end of the first OR gate is coupled to a first input end of the first AND gate; an input end of the fourth inverter is coupled to a first clock signal input end, and an output end of the fourth inverter is coupled to an input end of the second negative pulse flip-flop; an output end of the second negative pulse flip-flop is coupled to a second input end of the second NAND gate; a first input end of the second NAND gate is coupled to the frequency selection signal input end, and an output end of the second NAND gate is coupled to a second input end of the first AND gate; an output end of the first AND gate is coupled to the fourth node.

[0008] In some embodiments of the present disclosure, the ramp voltage selection circuit includes: a first current source, a second current source, a fifth inverter, a first transistor, a second transistor, a third transistor, and a first capacitor. Wherein, a first terminal of the first current source is coupled to a first voltage terminal, and a second terminal of the first current source is coupled to a first pole of the first transistor; a first terminal of the second current source is coupled to the first voltage terminal, and a second terminal of the second current source is coupled to a first pole of the second transistor; an input terminal of the fifth inverter is coupled to a frequency selection signal input terminal, and the input terminal of the fifth inverter is coupled to a control pole of the first transistor; a second pole of the first transistor is coupled to the third node; a control pole of the second transistor is coupled to the frequency selection signal input terminal, and a second pole of the second transistor is coupled to the third node; a control pole of the third transistor is coupled to the fourth node, a first pole of the third transistor is coupled to the third node, and a second pole of the third transistor is coupled to a second voltage terminal; a first terminal of the first capacitor is coupled to the third node, and a second terminal of the first capacitor is coupled to the second voltage terminal.

[0009] In some embodiments of the present disclosure, the PWM signal output circuit includes: a PWM comparator. Wherein, a control terminal of the PWM comparator is coupled to the second node, a first input terminal of the PWM comparator is coupled to the third node, a second input terminal of the PWM comparator is coupled to an output voltage signal terminal of the error amplifier, and an output terminal of the PWM comparator is coupled to the signal output terminal.

[0010] In some embodiments of the present disclosure, when a high-level signal is input to the frequency selection signal input terminal, the clock selection signal is the first clock signal; when a low-level signal is input to the frequency selection signal input terminal, the clock selection signal is the second clock signal.

[0011] In some embodiments of the present disclosure, when a high-level signal is input to the frequency selection signal input terminal, the first transistor is turned on, and the current in the first current source charges the first capacitor, and the ramp voltage signal is related to the first current source; when a low-level signal is input to the frequency selection signal input terminal, the second transistor is turned on, and the current in the second current source charges the first capacitor, and the ramp voltage signal is related to the second current source.

[0012] In some embodiments of the present disclosure, when a high-level signal is input to the frequency selection signal input terminal and the first clock signal changes from high level to low level, or when a low-level signal is input to the frequency selection signal input terminal and the second clock signal changes from high level to low level, the third transistor is turned on, the first capacitor discharges, and the ramp voltage signal is a low-level signal.

[0013] In some embodiments of the present disclosure, the rising edge of the PWM signal is synchronized with the rising edge of the clock selection signal, and the falling edge of the PWM signal is determined by the comparison result between the output voltage signal of the error amplifier and the rising edge of the ramp voltage signal.

[0014] The ramp generation circuit according to the embodiments of the present disclosure generates different clock signals and corresponding ramp voltage signals, realizing a predictable PWM signal, without the need for additional trimming circuits and voltage buffers, saving circuit area.

[0015] Other features and advantages of the embodiments of the present disclosure will be described in detail in the subsequent detailed description section. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings are used to provide a further understanding of the embodiments of the present disclosure, and constitute a part of the specification. Together with the following detailed description, they are used to explain the embodiments of the present disclosure, but do not constitute a limitation to the embodiments of the present disclosure. In the drawings:

[0017] Figure 1 is a schematic diagram of signal waveforms corresponding to a PWM signal generation circuit;

[0018] Figure 2 is a schematic diagram of signal waveforms corresponding to another PWM signal generation circuit;

[0019] Figure 3 is a schematic block diagram of a ramp generation circuit according to an embodiment of the present disclosure;

[0020] Figure 4 is an exemplary circuit diagram of a ramp generation circuit according to an embodiment of the present disclosure;

[0021] Figure 5 is a schematic diagram of signal waveforms of a ramp generation circuit according to an embodiment of the present disclosure.

[0022] The elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION

[0023] In order to make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of the present disclosure without creative efforts shall also fall within the scope of protection of the present disclosure.

[0024] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Further will be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless expressly defined otherwise herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0025] In all embodiments of the present disclosure, since the source and drain of a metal-oxide-semiconductor (MOS) transistor are symmetric, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, in the embodiments of the present disclosure, the controlled intermediate terminal of the MOS transistor is referred to as the control electrode, and the remaining two terminals of the MOS transistor are respectively referred to as the first electrode and the second electrode. The transistors employed in the embodiments of the present disclosure are mainly switching transistors. In addition, for the sake of unified description, in the context, the base of a bipolar junction transistor (BJT) is referred to as the control electrode, the emitter of the BJT is referred to as the first electrode, and the collector of the BJT is referred to as the second electrode. Additionally, terms such as "first" and "second" are only used to distinguish one component (or a part of a component) from another component (or another part of a component).

[0026] Figure 1 A schematic diagram of the signal waveforms corresponding to a PWM signal generation circuit is shown. In Figure 1 the example, when the ramp voltage V RAMP signal touches the reference voltage (including V REF1 and V REF2 ), thereby triggering the clock signal CLK to flip, the accuracy of this clock signal often needs to be adjusted by a trimming circuit. Additionally, the ramp voltage V RAMP signal is directly used as the signal compared with the output voltage V EAO of the error amplifier EA. When the rising edge of the ramp voltage V RAMP signal touches V EAO , a falling edge of the PWM signal is generated. When the PWM signal approaches a 0 duty ratio, V EAO approaches the valley value of the ramp voltage V RAMP signal. Therefore, in order to ensure the loop gain, it is necessary to ensure that the valley value of the ramp voltage V RAMP signal is controllable and not too low. However, in the case where the frequency of this PWM signal generation circuit is fixed and the maximum duty ratio of the PWM signal (i.e., the duty ratio of the clock signal CLK) is determined, if V REF2 is low, then the ramp voltage V RAMPThe slope of the signal is small, resulting in an increase in the loop gain and causing the loop to be unstable. If a larger V is to be generated REF2 , an additional voltage buffer is required. Additionally, in engineering applications, the frequency of the PWM signal and the ramp voltage V RAMP signal may need to be reset to 0.5 times the original value (or lower, which can improve system efficiency). At this time, the charging current I ref1 and I ref2 values need to be changed. To ensure frequency accuracy, an additional trimming circuit is required. Therefore, for the above PWM signal generation circuit, an additional voltage buffer and trimming circuit are needed, resulting in an increase in system area.

[0027] Figure 2 FIG. shows a schematic diagram of the signal waveforms corresponding to another PWM signal generation circuit. In Figure 2 's example, an additional circuit is used to generate the required ramp voltage V RAMP signal, which can effectively avoid the problems mentioned in the Figure 1 -shown manner. The lowest value of the ramp voltage V RAMP signal is clamped by the V REF3 generated by the voltage buffer. When it is necessary to reduce the frequencies of the PWM signal and the ramp voltage V RAMP signal, only a frequency division circuit and combinational logic are used to generate a clock signal, and then the charging current I ref3 is appropriately adjusted to generate a suitable ramp voltage signal. However, this PWM signal generation circuit requires an additional voltage buffer. Additionally, in the case of the extreme duty cycle, before the clock signal CLK1 goes high, V EAO and the ramp voltage V RAMP1 signals are very close, and the comparator may not be able to compare the normal value and is in an uncertain intermediate state, resulting in an uncertain flip delay t_delay of the comparator and generating a PWM signal with an uncertain pulse width, ultimately causing the NMOS transistor to turn on in a skip cycle.

[0028] Embodiments of the present disclosure propose a ramp generation circuit. This ramp generation circuit does not require an additional trimming circuit and voltage buffer, and can enable the loop in the boost-type DC-DC system to stably operate in the case of the extreme duty cycle. Additionally, the optional charging current realizes an optional ramp voltage signal, and thus realizes a PWM signal with an optional frequency. Figure 3 FIG. shows a schematic block diagram of a ramp generation circuit 300 according to an embodiment of the present disclosure. As Figure 2 shown, the ramp generation circuit 300 may include: a clock selection circuit 310, a ramp voltage output circuit 320, and a PWM signal output circuit 330.

[0029] The clock selection circuit 310 can be coupled to the ramp voltage output circuit 320, the PWM signal output circuit 330, the first clock signal input terminal CLK1, and the frequency selection signal input terminal fre_sel. The clock selection circuit 310 can be configured to obtain a second clock signal CLK2 and a clock selection signal CLK0 according to the frequency selection signal fre_sel and the first clock signal CLK1, and provide the second clock signal CLK2 to the ramp voltage output circuit 320 via the first node N1, and provide the clock selection signal CLK0 to the PWM signal output circuit 330 via the second node N2. The user can obtain the clock selection signal CLK0 corresponding to different requirements by setting different frequency selection signals fre_sel according to the frequency requirement of the PWM signal.

[0030] The ramp voltage output circuit 320 can be coupled to the clock selection circuit 310, the PWM signal output circuit 330, the first clock signal input terminal CLK1, the frequency selection signal input terminal fre_sel, the first voltage terminal V1, and the second voltage terminal V2. The ramp voltage output circuit 320 can be configured to obtain a ramp voltage signal V according to the frequency selection signal fre_sel, the first clock signal CLK1, and the second clock signal CLK2 RAMP and provide the ramp voltage signal V to the PWM signal output circuit 330 via the third node N3 RAMP .

[0031] The PWM signal output circuit 330 can be coupled to the clock selection circuit 310, the ramp voltage output circuit 320, the output voltage signal terminal V of the error amplifier EAO and the signal output terminal OUT. The PWM signal output circuit 330 is configured to output a PWM signal corresponding to the frequency selection signal fre_sel from the signal output terminal OUT according to the comparison result between the output voltage signal V of the error amplifier EAO and the ramp voltage signal V RAMP and the clock selection signal CLK0.

[0032] The ramp generation circuit according to an embodiment of the present disclosure generates different clock signals and corresponding ramp voltage signals, realizing a predictable PWM signal. Therefore, compared with Figure 1 and Figure 2 the PWM signal generation circuit, the ramp generation circuit according to an embodiment of the present disclosure does not require an additional trimming circuit and a voltage buffer, saving circuit area.

[0033] Figure 4 FIG. shows an exemplary circuit diagram of the ramp generation circuit 300 according to an embodiment of the present disclosure. As Figure 4As shown, the clock selection circuit 310 may include: a first inverter D1, a D flip-flop DFF, a first NAND gate G1, and a multiplexer mux. Among them, the input terminal of the first inverter D1 is coupled to the first clock signal input terminal CLK1, and the output terminal of the first inverter D1 is coupled to the clock input terminal Clk of the D flip-flop DFF. The D signal input terminal of the D flip-flop DFF is coupled to the Q-bar output terminal of the D flip-flop DFF, and the reset terminal Reset of the D flip-flop DFF is coupled to the frequency selection signal input terminal fre_sel. The first input terminal of the first NAND gate G1 is coupled to the Q-bar output terminal of the D flip-flop DFF, the second input terminal of the first NAND gate G1 is coupled to the first clock signal input terminal CLK1, and the output terminal of the first NAND gate G1 is coupled to the first node N1. The control terminal of the multiplexer mux is coupled to the frequency selection signal input terminal fre_sel, the first input terminal of the multiplexer mux is coupled to the first clock signal input terminal CLK1, the second input terminal of the multiplexer mux is coupled to the first node N1, and the output terminal of the multiplexer mux is coupled to the second node N2.

[0034] The ramp voltage output circuit 320 may include: a ramp voltage control circuit 321 and a ramp voltage selection circuit 322. Among them, the ramp voltage control circuit 321 is configured to obtain a ramp voltage low-level control signal according to the frequency selection signal fre_sel, the first clock signal CLK1, and the second clock signal CLK2, and provide the ramp voltage low-level control signal to the ramp voltage selection circuit 322 via the fourth node N4. The ramp voltage selection circuit 322 is configured to obtain the ramp voltage signal V corresponding to the frequency selection signal fre_sel according to the frequency selection signal fre_sel and the ramp voltage low-level control signal. RAMP .

[0035] Among them, the ramp voltage control circuit 321 may include: a second inverter D2, a first negative pulse flip-flop P1, a third inverter D3, a first OR gate G2, a fourth inverter D4, a second negative pulse flip-flop P2, a second NAND gate G3, and a first AND gate G4. Among them, the input end of the second inverter D2 is coupled to the first node N1, and the output end of the second inverter D2 is coupled to the input end of the first negative pulse flip-flop P1. The output end of the first negative pulse flip-flop P1 is coupled to the input end of the third inverter D3. The output end of the third inverter D3 is coupled to the first input end of the first OR gate G2. The second input end of the first OR gate G2 is coupled to the frequency selection signal input end fre_sel, and the output end of the first OR gate G2 is coupled to the first input end of the first AND gate G4. The input end of the fourth inverter D4 is coupled to the first clock signal input end CLK1, and the output end of the fourth inverter D4 is coupled to the input end of the second negative pulse flip-flop P2. The output end of the second negative pulse flip-flop P2 is coupled to the second input end of the second NAND gate G3. The first input end of the second NAND gate G3 is coupled to the frequency selection signal input end fre_sel, and the output end of the second NAND gate G3 is coupled to the second input end of the first AND gate G4. The output end of the first AND gate G4 is coupled to the fourth node N4.

[0036] The ramp voltage selection circuit 322 may include: a first current source I1, a second current source I2, a fifth inverter D5, a first transistor M1, a second transistor M2, a third transistor M3, and a first capacitor C1. Among them, the first end of the first current source I1 is coupled to the first voltage terminal V1, and the second end of the first current source I1 is coupled to the first pole of the first transistor M1. The first end of the second current source I2 is coupled to the first voltage terminal V1, and the second end of the second current source I2 is coupled to the first pole of the second transistor M2. The input end of the fifth inverter D5 is coupled to the frequency selection signal input end fre_sel, and the input end of the fifth inverter D5 is coupled to the control pole of the first transistor M1. The second pole of the first transistor M1 is coupled to the third node N3. The control pole of the second transistor M2 is coupled to the frequency selection signal input end fre_sel, and the second pole of the second transistor M2 is coupled to the third node N3. The control pole of the third transistor M3 is coupled to the fourth node N4, the first pole of the third transistor M3 is coupled to the third node N3, and the second pole of the third transistor M3 is coupled to the second voltage terminal V2. The first end of the first capacitor C1 is coupled to the third node N3, and the second end of the first capacitor C1 is coupled to the second voltage terminal V2.

[0037] The PWM signal output circuit 330 may include: a PWM comparator. Wherein, a control terminal of the PWM comparator is coupled to the second node N2, a first input terminal of the PWM comparator is coupled to the third node N3, a second input terminal of the PWM comparator is coupled to an output voltage signal terminal V of the error amplifier EAO , and an output terminal of the PWM comparator is coupled to the signal output terminal OUT.

[0038] In Figure 4 the example, a high-voltage signal is input from the first voltage terminal V1, and the second voltage terminal V2 is grounded. A clock signal CLK1 with a certain frequency and duty cycle generated by an oscillator after being trimmed by a trimming circuit is input to the first clock signal input terminal CLK1, and the frequency accuracy of this signal is relatively high. In addition, the second clock signal CLK2 is generated by frequency division of a D flip-flop DFF, so the frequency accuracy is also relatively high. The frequency selection signal fre_sel is the required operating frequency selected by the user. The first transistor M1 and the second transistor M2 are both PMOS transistors, and the third transistor M3 is an NMOS transistor. The first negative pulse flip-flop P1 and the second negative pulse flip-flop P2 are both 2 ns short pulse flip-flops. Those skilled in the art should understand that variations made to the Figure 4 circuit shown should also fall within the protection scope of the present disclosure. In this variation, the above-mentioned transistors and voltage terminals may also have settings different from those in the Figure 4 example shown.

[0039] Next, the working process of the ramp generation circuit 300 according to an embodiment of the present disclosure will be described with reference to the Figure 4 and Figure 5 example.

[0040] When a high-level signal is input to the frequency selection signal input terminal fre_sel, that is, fre_sel = 1, the input to the reset terminal Reset of the D flip-flop DFF is 1, then the Q non-output terminal of the D flip-flop DFF does not change with the change of the signal input to its clock input terminal, and the Q non-output terminal remains 1. The output of the first node N1, that is, the second clock signal CLK2, changes with the high and low levels of the first clock signal CLK1.

[0041] When fre_sel = 1, the clock selection signal output by the data selector mux is the first clock signal CLK1. The rising edge of the PWM signal is synchronized with the rising edge of the first clock signal CLK1, and the falling edge of the PWM signal is determined by the comparison result between the output voltage signal V of the error amplifier EAO and the ramp voltage signal V RAMP , that is, when V EAO and the ramp voltage signal V RAMPWhen the rising edges are equal, the PWM signal flips downward to a falling edge, while the ramp voltage signal V RAMP is determined by the ramp voltage output circuit 320.

[0042] When fre_sel = 1, the first transistor M1 is turned on, and the current of the first current source I1 charges the first capacitor C1. Therefore, the ramp voltage signal V RAMP is related to the first current source I1, and the slope of the ramp voltage signal V RAMP is determined by the first current source I1 and the first capacitor C1, as Figure 5 shown. When fre_sel = 1, the input of the second input terminal of the first OR gate G2 is 1, then the input of the first input terminal of the first AND gate G4 is 1, and the input of the first input terminal of the second NAND gate G3 is 1. Therefore, whether the first capacitor C1 discharges is determined by the change of the first clock signal CLK1. When the first clock signal CLK1 changes from high level to low level, the output of the fourth inverter D4 changes from low level to high level, and the second negative pulse flip-flop P2 outputs a low pulse. Then the output of the second NAND gate G3 is 1, the output of the first AND gate G4 is 1, the third transistor M3 is turned on, and the first capacitor C1 discharges, then the ramp voltage signal V RAMP is pulled low to a low level signal.

[0043] When a low level signal is input to the frequency selection signal input terminal fre_sel, that is, fre_sel = 0, the reset terminal Reset of the D flip-flop DFF inputs 0. At this time, the D flip-flop DFF can receive the signal input to the clock input terminal. When a rising edge is received at the clock input terminal, the inverted signal of the D signal input terminal is sent to the Q non-output terminal. Then the second clock signal CLK2 output from the Q non-output terminal of the D flip-flop DFF will change with the change of the signal input to its clock input terminal.

[0044] When fre_sel = 0, the clock selection signal output by the data selector mux is the second clock signal CLK2. The rising edge of the PWM signal is synchronized with the rising edge of the second clock signal CLK2, while the falling edge of the PWM signal is determined by the comparison result of the output voltage signal V EAO of the error amplifier and the ramp voltage signal V RAMP That is, when V EAO is equal to the rising edge of the ramp voltage signal V RAMP the PWM signal flips downward to a falling edge, while the ramp voltage signal V RAMP is determined by the ramp voltage output circuit 320.

[0045] When fre_sel = 0, the second transistor M2 is turned on, and the current of the second current source I2 charges the first capacitor C1. Therefore, the ramp voltage signal VRAMP associated with the second current source I2, the slope of the ramp voltage signal V RAMP is determined by the second current source I2 and the first capacitor C1, as Figure 5 shown. When fre_sel = 0, the input of the first input terminal of the second NAND gate G3 is 0. Therefore, the input of the second input terminal of the first AND gate G4 is 1, and the input of the second input terminal of the first OR gate G2 is 0. Then, whether the first capacitor C1 discharges is determined by the change of the second clock signal CLK2. When the second clock signal CLK2 changes from high level to low level, the output of the second inverter D2 changes from low level to high level, and the first negative pulse flip-flop P1 outputs a low pulse. Then, the input of the first input terminal of the first OR gate G2 is 1, and the input of the first input terminal of the first AND gate G4 is 1. Then, its output is 1, the third transistor M3 is turned on, and the first capacitor C1 discharges, and the ramp voltage signal V RAMP is pulled down to be a low level signal.

[0046] In addition, in order to distinguish the different signals generated by the two clock signals and the two current sources, the ramp voltage signal V RAMP obtained by charging the first capacitor C1 with the first current source I1 is called V RAMP1 , and the PWM signal when the first clock signal CLK1 and the corresponding V RAMP1 act simultaneously is called PWM1; the ramp voltage signal V RAMP obtained by charging the first capacitor C1 with the second current source I2 is called V RAMP2 , and the PWM signal when the second clock signal CLK2 and the corresponding V RAMP2 act simultaneously is called PWM2.

[0047] To sum up, when fre_sel = 1, the rising edge of the PWM1 signal is synchronized with the rising edge of the first clock signal CLK1, and its falling edge is determined by the comparison result of the output voltage signal V EAO of the error amplifier and the ramp voltage signal V RAMP1 , that is, when the rising edges of V EAO and V RAMP1 are equal, the PWM1 signal flips down to a falling edge. When fre_sel = 0, the rising edge of the PWM2 signal is synchronized with the rising edge of the second clock signal CLK2, and its falling edge is determined by the comparison result of the output voltage signal V EAO of the error amplifier and the ramp voltage signal V RAMP2 , that is, when the rising edges of V EAO and V RAMP2 are equal, the PWM2 signal flips down to a falling edge.

[0048] According to an embodiment of the present disclosure, a ramp generation circuit generates a ramp voltage signal by charging an additional capacitor with an additional current. When it is necessary to expand the PWM frequency, for example, when the frequency becomes 0.5 times the original frequency, only the corresponding current source needs to be selected to obtain a suitable ramp voltage signal, so that no additional trimming circuit is required. In addition, the minimum value of the ramp voltage signal in the embodiment of the present disclosure is 0, so no additional voltage buffer is required to clamp the minimum voltage. And, since the second input terminal of the PWM comparator is coupled to the output voltage signal terminal of the error amplifier, the input signal V EAO at the input terminal can be regarded as a fixed reference voltage within a switching period, and the input signal at the first input terminal is a continuously rising ramp voltage signal V RAMP . Therefore, the PWM signal output at the output terminal of the PWM comparator is either high level or low level, and there will be no "intermediate state" as shown in Figure 2 . In this way, it can be ensured that the delay t_delay of each period is the same, the PWM can stably generate waves when working at the limit duty cycle, and the NMOS can be prevented from turning on or off in a skipping cycle. The ramp generation circuit of the embodiment of the present disclosure can enable the loop in the boost-type DC-DC system to stably operate at the limit duty cycle.

[0049] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of devices and methods according to multiple embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of an instruction, and the module, program segment, or part of an instruction contains one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than marked in the accompanying drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, as well as the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system that performs the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0050] Unless otherwise explicitly stated in the context, the singular forms of words used in this specification and the appended claims include the plural, and vice versa. Thus, when referring to the singular, the corresponding plural is usually included. Similarly, the terms "comprising" and "including" will be interpreted as inclusive rather than exclusive. Likewise, the term "including" and "or" should be interpreted as inclusive, unless such an interpretation is explicitly prohibited in this specification. Where the term "example" is used in this specification, especially when it is located after a group of terms, the "example" is merely exemplary and explanatory, and should not be considered exclusive or extensive.

[0051] Further aspects and scopes of adaptability will become apparent from the description provided herein. It should be understood that the various aspects of the present application can be implemented alone or in combination with one or more other aspects. It should also be understood that the description herein and the specific embodiments are for illustrative purposes only and are not intended to limit the scope of the present application.

[0052] The above has described in detail several embodiments of the present disclosure. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the appended claims.

Claims

1. A ramp generation circuit, characterized in that, Comprising: a clock selection circuit, a ramp voltage output circuit, and a pulse width modulation (PWM) signal output circuit, wherein the clock selection circuit is configured to obtain a second clock signal and a clock selection signal based on a frequency selection signal and a first clock signal, and provide the second clock signal to the ramp voltage output circuit via a first node, and provide the clock selection signal to the PWM signal output circuit via a second node; the ramp voltage output circuit is configured to obtain a ramp voltage signal based on the frequency selection signal, the first clock signal, and the second clock signal, and provide the ramp voltage signal to the PWM signal output circuit via a third node; the PWM signal output circuit is configured to output a PWM signal corresponding to the frequency selection signal from a signal output terminal based on a comparison result between an output voltage signal of an error amplifier and the ramp voltage signal, and the clock selection signal.

2. The ramp generation circuit according to claim 1, wherein The clock selection circuit includes: a first inverter, a D flip-flop, a first NAND gate, and a data selector, wherein an input terminal of the first inverter is coupled to a first clock signal input terminal, and an output terminal of the first inverter is coupled to a clock input terminal of the D flip-flop; a D signal input terminal of the D flip-flop is coupled to a Q-bar output terminal of the D flip-flop, and a reset terminal of the D flip-flop is coupled to a frequency selection signal input terminal; a first input terminal of the first NAND gate is coupled to the Q-bar output terminal of the D flip-flop, a second input terminal of the first NAND gate is coupled to the first clock signal input terminal, and an output terminal of the first NAND gate is coupled to the first node; a control terminal of the data selector is coupled to the frequency selection signal input terminal, a first input terminal of the data selector is coupled to the first clock signal input terminal, a second input terminal of the data selector is coupled to the first node, and an output terminal of the data selector is coupled to the second node.

3. The ramp generation circuit according to claim 1, wherein The ramp voltage output circuit includes: a ramp voltage control circuit and a ramp voltage selection circuit, wherein the ramp voltage control circuit is configured to obtain a ramp voltage low-level control signal based on the frequency selection signal, the first clock signal, and the second clock signal, and provide the ramp voltage low-level control signal to the ramp voltage selection circuit via a fourth node; the ramp voltage selection circuit is configured to obtain the ramp voltage signal corresponding to the frequency selection signal based on the frequency selection signal and the ramp voltage low-level control signal.

4. The ramp generation circuit according to claim 3, characterized in that, The ramp voltage control circuit includes: a second inverter, a first negative pulse flip-flop, a third inverter, a first OR gate, a fourth inverter, a second negative pulse flip-flop, a second NAND gate, and a first AND gate, wherein an input terminal of the second inverter is coupled to the first node, and an output terminal of the second inverter is coupled to an input terminal of the first negative pulse flip-flop; an output terminal of the first negative pulse flip-flop is coupled to an input terminal of the third inverter; an output terminal of the third inverter is coupled to a first input terminal of the first OR gate; The second input terminal of the first OR gate is coupled to the frequency selection signal input terminal, and the output terminal of the first OR gate is coupled to the first input terminal of the first AND gate; The input terminal of the fourth inverter is coupled to the first clock signal input terminal, and the output terminal of the fourth inverter is coupled to the input terminal of the second negative pulse flip-flop; The output terminal of the second negative pulse flip-flop is coupled to the second input terminal of the second NAND gate; The first input terminal of the second NAND gate is coupled to the frequency selection signal input terminal, and the output terminal of the second NAND gate is coupled to the second input terminal of the first AND gate; The output terminal of the first AND gate is coupled to the fourth node.

5. The ramp generation circuit according to claim 3, wherein The ramp voltage selection circuit includes: a first current source, a second current source, a fifth inverter, a first transistor, a second transistor, a third transistor, and a first capacitor, wherein, the first end of the first current source is coupled to the first voltage terminal, and the second end of the first current source is coupled to the first pole of the first transistor; The first end of the second current source is coupled to the first voltage terminal, and the second end of the second current source is coupled to the first pole of the second transistor; The input terminal of the fifth inverter is coupled to the frequency selection signal input terminal, and the input terminal of the fifth inverter is coupled to the control pole of the first transistor; The second pole of the first transistor is coupled to the third node; The control pole of the second transistor is coupled to the frequency selection signal input terminal, and the second pole of the second transistor is coupled to the third node; The control pole of the third transistor is coupled to the fourth node, the first pole of the third transistor is coupled to the third node, and the second pole of the third transistor is coupled to the second voltage terminal; The first end of the first capacitor is coupled to the third node, and the second end of the first capacitor is coupled to the second voltage terminal.

6. The ramp generation circuit according to claim 1, wherein The PWM signal output circuit includes: a PWM comparator, wherein, the control terminal of the PWM comparator is coupled to the second node, the first input terminal of the PWM comparator is coupled to the third node, the second input terminal of the PWM comparator is coupled to the output voltage signal terminal of the error amplifier, and the output terminal of the PWM comparator is coupled to the signal output terminal.

7. The ramp generation circuit according to claim 2, wherein When a high-level signal is input to the frequency selection signal input terminal, the clock selection signal is the first clock signal; when a low-level signal is input to the frequency selection signal input terminal, the clock selection signal is the second clock signal.

8. The ramp generation circuit according to claim 5, wherein When a high-level signal is input to the frequency selection signal input terminal, the first transistor is turned on, and the current in the first current source charges the first capacitor, and the ramp voltage signal is related to the first current source; When a low-level signal is input to the frequency selection signal input terminal, the second transistor is turned on, and the current in the second current source charges the first capacitor, and the ramp voltage signal is related to the second current source.

9. The ramp generation circuit according to claim 5, wherein When a high-level signal is input to the frequency selection signal input terminal and the first clock signal changes from high level to low level, or when a low-level signal is input to the frequency selection signal input terminal and the second clock signal changes from high level to low level, the third transistor is turned on, the first capacitor discharges, and the ramp voltage signal is a low-level signal.

10. The ramp generation circuit according to claim 6, wherein The rising edge of the PWM signal is synchronized with the rising edge of the clock selection signal, and the falling edge of the PWM signal is determined by the comparison result between the output voltage signal of the error amplifier and the rising edge of the ramp voltage signal.

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