A memristor based on silicon carbide nanowires and a preparation method thereof

Abstract

The present invention provides a memristor based on silicon carbide nanowires and a preparation method thereof, which sequentially includes a bottom electrode, a silicon carbide nanowire thin film, a PMMA thin film, and a top electrode from bottom to top. The preparation method includes: Step 1, covering a silicon carbide nanowire thin film on the conductive surface of the bottom electrode; Step 2: Coating a PMMA solution on the silicon carbide nanowire thin film obtained in Step 1, pressing the top electrode with its conductive surface facing down onto the PMMA solution, and thermally pressing to solidify the PMMA to obtain the memristor. A two-terminal structure silicon carbide nanowire memristor is prepared by a simple and rapid method, which can well simulate the basic functions of brain synapses and can also simulate the functions of more complex dendritic nerves.

Description

Technical Field

[0001] The present invention belongs to the technical field of memristor neural synapse preparation. Specifically, it relates to a memristor based on silicon carbide nanowires and a preparation method thereof. Background Art

[0002] Currently, the development of computers with the von Neumann architecture has encountered bottlenecks. As the size of transistors continues to decrease, the uncertainty of electron movement within transistors gradually increases, making it more difficult to manufacture chips with smaller sizes and larger integration scales. Moreover, in a computer with the von Neumann architecture, storage and computing are separated and connected by a bus. This also means that a piece of data needs to be transmitted back and forth between the processor and the memory two or more times to complete data processing, which cannot meet the requirements of a new generation of intelligent robots. Therefore, a new type of processor device is needed to meet this requirement.

[0003] As an emerging device, a memristor has high-resistance and low-resistance states similar to those of traditional memories, and can achieve information storage. Moreover, memristors have great potential in simulating the functions of neural synapses. The brain is the central hub for human information processing and storage, and synapses are the basic units responsible for processing and storing this information. Memristors can simulate many functions of synapses, such as short-term memory (STM), long-term memory (LTM), paired-pulse facilitation (PPF), spike-timing-dependent plasticity (STDP), etc. Therefore, using memristors to fabricate artificial synapses is expected to achieve a device that integrates storage and computing to solve the current problems in computer development. And in recent years, with the development of research on memristor artificial synapses, memristor artificial synapses that simulate visual nerves to form an "awareness-storage-computation" integration have also received people's attention. This development is expected to solve the hardware requirements of a new generation of intelligent robots.

[0004] Silicon carbide (SiC) has a bandgap of 2.4–3.3 eV and is one of the most promising materials for detecting ultraviolet radiation, with high sensitivity and strong stability, and has been widely studied in semiconductor optoelectronic devices. However, there are few reports on opto-stimulated memristor artificial synapse devices based on silicon carbide nanowires. Summary of the Invention

[0005] In order to solve the problems of the above-mentioned prior art, the present invention provides a memristor based on silicon carbide nanowires and a preparation method thereof. A two-terminal-structured silicon carbide nanowire memristor is prepared by a simple and rapid method, which can well simulate the basic functions of brain synapses and can also simulate the functions of more complex dendritic nerves.

[0006] The present invention is realized through the following technical solutions:

[0007] A memristor based on silicon carbide nanowires, which sequentially includes a bottom electrode, a silicon carbide nanowire thin film, a PMMA thin film, and a top electrode from bottom to top.

[0008] The preparation method of the memristor based on silicon carbide nanowires includes:

[0009] Step 1, covering a silicon carbide nanowire thin film on the conductive surface of the bottom electrode;

[0010] Step 2: Coating a PMMA solution on the silicon carbide nanowire thin film obtained in Step 1, pressing the top electrode with the conductive surface facing down onto the PMMA solution, and thermally pressing to solidify the PMMA to obtain a memristor.

[0011] Preferably, Step 1 specifically includes:

[0012] Step 1.1, electrochemically etching a silicon carbide single crystal wafer using an anodic oxidation method to obtain a silicon carbide nanowire vertical array thin film;

[0013] Step 1.2, transferring the silicon carbide nanowire vertical array thin film to the surface of the bottom electrode.

[0014] Further, in Step 1.1, the electrochemically etching parameters are: pulsed current, current amplitude 80 - 100 mA, pulse time 0.8 ms, and duty cycle 50%.

[0015] Further, in Step 1.1, the silicon carbide single crystal wafer is an N-doped 4-H silicon carbide nanocrystal wafer.

[0016] Further, in Step 1.1, the etching solution used for electrochemically etching includes HF, ethanol, and H2O2, and the volume ratio of HF, ethanol, and H2O2 is 3:6:1.

[0017] Preferably, Step 1 specifically includes:

[0018] Step 1.1, adding silicon carbide nanowires, sodium dodecylbenzenesulfonate, and aluminum nitrate into an isopropanol solution, and ultrasonically dispersing to obtain a silicon carbide nanowire electrochemical deposition solution;

[0019] Step 1.2, using the silicon carbide nanowire electrochemical deposition solution, and depositing silicon carbide nanowires onto the bottom electrode by an electrochemical deposition method to form a silicon carbide nanowire thin film.

[0020] Further, in Step 1.1, the silicon carbide nanowires are 3-C silicon carbide nanowires.

[0021] Further, the ratio of silicon carbide nanowires, sodium dodecylbenzenesulfonate, aluminum nitrate, and isopropanol is: (0.02 - 0.1) g : (0.05 - 0.15) g : (0.001 - 0.005) g : (50 - 200) mL.

[0022] Preferably, in step 2, the PMMA solution is an acetone solution of PMMA.

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] Based on the memristor of silicon carbide nanowires, the present invention utilizes the different optical memory effects generated by the shallow traps and deep traps of the prepared nanowire thin film under different illumination conditions to successfully realize the simulation of visual synapses and ordinary synapse functions. With the help of PMMA, the leakage current of the device can be well reduced, and due to the viscosity of PMMA, the outside air is isolated, providing a stable internal environment for the internal performance of the device. The prepared device can well simulate the basic behaviors of neural synapses under optical and electrical stimuli, and has versatility, such as short-term memory (STM), long-term memory (LTM), paired-pulse facilitation (PPF), spike-timing-dependent plasticity (STDP), etc. It can also simulate the logical behaviors between multiple neuron synapses, successfully simulating the logical "AND" and logical "OR" functions, and can also simulate the function of biological learning and training, successfully simulating the "Pavlovian" conditioned reflex.

[0025] The preparation process of the present invention is simple and has low power consumption, and can simply and conveniently prepare silicon carbide nanowire functional thin films and their memristors on a large scale.

[0026] Furthermore, the SiC nanowire vertical array prepared by the electrochemical etching method of the present invention has a large surface-to-volume ratio, which can well limit the flow of internal electrons and has advantages in the application of optoelectronic devices.

[0027] Furthermore, etching the N-doped 4-H silicon carbide single crystal wafer can obtain a silicon carbide nanowire array with better properties compared to other crystal forms of silicon carbide single crystal wafers.

[0028] Furthermore, the etching solution used in the electrochemical etching includes HF, ethanol, and H2O2, and the ratio of HF:ethanol:H2O2 is 3:6:1. Etching the silicon carbide single crystal wafer with this ratio has the best etching effect.

[0029] Furthermore, the electrochemical deposition solution obtained during the silicon carbide nanowire thin film process has the best deposition effect and strong controllability during deposition.

[0030] Furthermore, the cost of obtaining 3-C silicon carbide nanowires is simpler and lower than that of other crystal forms of nanowires, which helps to prepare a large amount of electrochemical deposition solution and mass-produce devices.

[0031] Further, the ratio of silicon carbide nanowires, sodium dodecylbenzenesulfonate, aluminum nitrate and isopropanol is: (0.02 - 0.1) g : (0.05 - 0.15) g : (0.001 - 0.005) g : (50 - 200) mL. The silicon carbide nanowire thin film deposited with this ratio is dense and has good uniformity. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 Schematic diagram of the memristor structure of the silicon carbide nanowire vertical array in Embodiments 1 - 3 of the present invention.

[0033] Figure 2 SEM photograph of the silicon carbide nanowire vertical array thin film prepared in Embodiment 2 of the present invention.

[0034] Figure 3 Schematic diagram of the connection of two silicon carbide nanowire vertical array memristor devices of the present invention.

[0035] Figure 4 Double - pulse alienation data diagram of the silicon carbide nanowire vertical array memristor in Embodiment 2 of the present invention.

[0036] Figure 5 Long - term memory data diagram of the silicon carbide nanowire vertical array memristor in Embodiment 2 of the present invention.

[0037] Figure 6 Logic operation data diagram of the silicon carbide nanowire vertical array memristor in Embodiment 2 of the present invention.

[0038] Figure 7 "Pavlov" conditional reflex data diagram of the silicon carbide nanowire vertical array memristor in Embodiment 2 of the present invention.

[0039] Figure 8 Schematic diagram of the memristor array structure based on silicon carbide nanowires in Embodiments 4 - 7 of the present invention.

[0040] Figure 9 Schematic diagram of the memristor structure based on silicon carbide nanowires in Embodiments 4 - 7 of the present invention.

[0041] Figure 10 SEM photograph of the silicon carbide nanowire thin film prepared in Embodiment 5 of the present invention.

[0042] Figure 11 Schematic diagram of the connection of two memristors based on silicon carbide nanowires of the present invention.

[0043] Figure 12 Double - pulse alienation data diagram of the silicon carbide nanowire memristor under light stimulation in Embodiment 5 of the present invention.

[0044] Figure 13This is the long-term memory data graph of the silicon carbide nanowire memristor under light stimulation in Embodiment 5 of the present invention.

[0045] Figure 14 This is the data graph of the memory retention time of the silicon carbide nanowire memristor array under light stimulation in Embodiment 5 of the present invention.

[0046] Figure 15 This is the logic operation data graph of the silicon carbide nanowire memristor under light stimulation in Embodiment 5 of the present invention.

[0047] Figure 16 This is the data graph of the "Pavlov" conditioned reflex of the silicon carbide nanowire memristor under light stimulation in Embodiment 5 of the present invention. Detailed implementation manners

[0048] To further understand the present invention, the present invention will be described below in conjunction with embodiments. These descriptions are only used to further explain the features and advantages of the present invention and are not used to limit the claims of the present invention.

[0049] The memristor based on silicon carbide nanowires according to the present invention sequentially includes a bottom electrode, a silicon carbide nanowire thin film, a PMMA thin film, and a top electrode from bottom to top.

[0050] The bottom electrode preferably uses an ITO electrode, and the top electrode preferably uses an ITO electrode.

[0051] The preparation method of the memristor based on silicon carbide nanowires includes:

[0052] Step 1, covering a silicon carbide nanowire thin film on the conductive surface of the bottom electrode;

[0053] Step 2: Coating a PMMA solution on the silicon carbide nanowire thin film, pressing the top electrode with the conductive surface facing down onto the PMMA solution, and thermally pressing to solidify the PMMA to obtain a memristor.

[0054] The above Step 1 can be implemented by the following two methods.

[0055] Method 1: Step 1 specifically includes:

[0056] Step 1.1, preparation of a silicon carbide nanowire vertical array thin film: Electrochemically etching a silicon carbide single crystal wafer using an anodic oxidation method, using the carbon surface of the silicon carbide single crystal wafer facing the platinum electrode as the etching surface, etching in a silicon carbide nanowire etching solution for 10 - 20 minutes (etching parameters: pulsed current, current amplitude 80 - 100 mA, pulse time 0.8 ms, duty cycle 50%), after etching, repeatedly cleaning with ethanol and deionized water to remove the etching solution, and then drying at 60 °C for 15 minutes to obtain a silicon carbide nanowire vertical array thin film;

[0057] Step 1.2: Transfer the vertical array thin film of silicon carbide nanowires to the surface of the bottom electrode.

[0058] In Step 1.1, the silicon carbide single crystal wafer is pre-treated as follows: The purchased commercial silicon carbide single crystal wafer is cut into small pieces. After cutting, ultrasonic treatment is carried out in acetone, absolute ethanol and deionized water for 15 - 30 min respectively. After cleaning, it is stored in acetone for future use. The silicon carbide single crystal wafer is an N-doped 4-H silicon carbide single crystal nanowire wafer. The length of the vertically arrayed silicon carbide nanowires obtained by etching is 35 um, and the diameter of the silicon carbide nanowires is 30 nm.

[0059] In Step 1.1, the preparation of the silicon carbide nanowire etching solution: HF (40% purity), ethanol C2H5OH (99% purity) and H2O2 (30% purity) are mixed in the ratio of HF:C2H5OH:H2O2 = 3:6:1 to obtain the silicon carbide nanowire etching solution.

[0060] Method 2: Step 1 specifically includes:

[0061] Step 1.1: Preparation of the silicon carbide nanowire electrochemical deposition solution: Silicon carbide nanowires, sodium dodecylbenzenesulfonate and aluminum nitrate are added to an isopropanol solution, and ultrasonic dispersion is carried out for 30 - 60 min with an ultrasonic power of 800 - 1000 W to obtain the silicon carbide nanowire electrochemical deposition solution; the ratio of silicon carbide nanowires, sodium dodecylbenzenesulfonate, aluminum nitrate and isopropanol is: (0.02 - 0.1) g : (0.05 - 0.15) g : (0.001 - 0.005) g : (50 - 200) mL;

[0062] Step 1.2: Preparation of the bottom electrode / silicon carbide nanowire thin film: Using the silicon carbide nanowire electrochemical deposition solution obtained in Step 1.1, the silicon carbide nanowires are deposited on the bottom electrode by electrochemical deposition. The bottom electrode is the cathode, and the anode electrode is a platinum electrode. The deposition voltage is 50 - 60 V, and the deposition time is 6 - 8 min. After deposition, it is placed in a vacuum drying oven for drying. After drying, the bottom electrode / silicon carbide nanowire thin film is obtained.

[0063] In Step 1.1, the silicon carbide nanowires are 3-C silicon carbide nanowires, the length of the silicon carbide nanowires is 80 um, and the diameter of the silicon carbide nanowires is 20 nm.

[0064] In Step 2, the preparation method of the PMMA solution is as follows: Take PMMA particles, add them to an acetone solution, and use water bath heating at a heating temperature of 70 - 90 °C. After the solution cools, the PMMA solution is obtained; the ratio of PMMA to the acetone solution is: (20 - 50) mg : (20 - 50) mL.

[0065] In step 2, the hot pressing temperature is 100-120 °C and the pressure is 5000-7500 Pa.

[0066] The following are specific examples.

[0067] Preparation of a memristor with a vertical array of silicon carbide nanowires.

[0068] The preparation process is as follows:

[0069] (1) Cutting and cleaning of a single crystal silicon carbide wafer: A purchased commercial single crystal silicon carbide wafer (with a thickness of 0.35 mm) is cut into small pieces with a typical area of 10×15 mm. After cutting, ultrasonic treatment is carried out in acetone, absolute ethanol, and deionized water for 15 minutes respectively. After cleaning, it is stored in acetone for later use;

[0070] (2) Preparation of a silicon carbide nanowire etching solution: HF (40% purity), ethanol C2H5OH (99% purity), and H2O2 (30% purity) are mixed in a ratio of HF:C2H5OH:H2O2 = 3:6:1 to obtain a silicon carbide nanowire etching solution;

[0071] (3) Preparation of a PMMA solution: Weigh 20 mg of PMMA particles, add them to 20 mL of acetone solution, and heat them in a water bath at a temperature of 70 °C. After the solution cools down, a PMMA solution is obtained;

[0072] (4) Preparation of a thin film of a vertical array of silicon carbide nanowires: The cleaned single crystal silicon carbide wafer in step (1) is electrochemically etched using anodic oxidation. With the carbon surface of the single crystal silicon carbide wafer facing the platinum electrode as the etching surface, it is etched in the silicon carbide nanowire etching solution in step (2) for 10 minutes (etching parameters: pulsed current, current amplitude 80 mA, pulse time 0.8 ms, duty cycle 50%). After etching, it is repeatedly washed with ethanol and deionized water to remove the etching solution, and then dried at 60 °C for 15 minutes to obtain a thin film of a vertical array of silicon carbide nanowires;

[0073] (5) Assembly of an ITO / silicon carbide nanowire / ITO memristor: The thin film of the vertical array of silicon carbide nanowires obtained in step (4) is transferred to the surface of a purchased strip-shaped ITO conductive glass (electrode width 1 mm), then 0.5 mL of the PMMA solution in step (3) is drop-coated. After that, another cleaned ITO conductive glass is pressed onto the top with the conductive surface facing down, and then hot pressed at 100 °C to solidify the PMMA. The pressure is 5000 Pa to obtain an ITO / SiC NWs / PMMA / ITO memristor.

[0074] Example 2 Preparation of a memristor based on a vertical array of silicon carbide nanowires

[0075] The manufacturing process is as follows

[0076] (1) Cutting and cleaning of single-crystalline silicon carbide wafers: The purchased commercial single-crystalline silicon carbide wafers (with a thickness of 0.35 mm) are cut into small pieces with a typical area of 10×15 mm. After cutting, ultrasonic treatment is carried out in acetone, absolute ethanol, and deionized water for 30 min respectively. After cleaning, they are stored in acetone for future use;

[0077] (2) Preparation of silicon carbide nanowire etching solution: HF (40% purity), ethanol C2H5OH (99% purity), and H2O2 (30% purity) are mixed in a ratio of HF:C2H5OH:H2O2 = 3:6:1 to obtain the silicon carbide nanowire etching solution;

[0078] (3) Preparation of PMMA solution: Weigh 50 mg of PMMA particles, add them to 50 mL of acetone solution, and heat them in a water bath at a temperature of 90 °C. After the solution cools down, the PMMA solution is obtained;

[0079] (4) Preparation of vertically aligned silicon carbide nanowire thin films: The cleaned single-crystalline silicon carbide wafers in step (1) are electrochemically etched using anodic oxidation. The carbon surface of the single-crystalline silicon carbide wafer is opposite to the platinum electrode as the etching surface and etched in step (2) for 20 minutes (etching parameters: pulsed current, current amplitude 100 mA, pulse time 0.8 ms, duty cycle 50%). After etching, the etching solution is repeatedly washed away with ethanol and deionized water respectively, and then dried at 60 °C for 15 minutes to obtain the vertically aligned silicon carbide nanowire thin films;

[0080] (5) Assembly of ITO / silicon carbide nanowire / ITO memristor: The vertically aligned silicon carbide nanowire thin films obtained in step (4) are transferred onto the surface of the purchased strip-shaped ITO conductive glass (electrode width 1 mm), then 1 mL of the PMMA solution in step (3) is drop-coated. After that, another cleaned ITO conductive glass is pressed on top with the conductive surface facing down, and then thermally pressed at 120 °C to solidify the PMMA with a pressure of 7500 Pa to obtain the ITO / SiC NWs / PMMA / ITO memristor.

[0081] Example 3 Preparation of a memristor based on vertically aligned silicon carbide nanowires

[0082] The manufacturing process is as follows

[0083] (1) Cutting and cleaning of single-crystalline silicon carbide wafers: The purchased commercial single-crystalline silicon carbide wafers (with a thickness of 0.35 mm) are cut into small pieces with a typical area of 10×15 mm. After cutting, ultrasonic treatment is carried out in acetone, absolute ethanol, and deionized water for 30 min respectively. After cleaning, they are stored in acetone for future use;

[0084] (2) Preparation of silicon carbide nanowire etching solution: Mix HF (40% purity), ethanol C2H5OH (99% purity), and H2O2 (30% purity) in a ratio of HF:C2H5OH:H2O2 = 3:6:1 to obtain the silicon carbide nanowire etching solution;

[0085] (3) Preparation of PMMA solution: Weigh 50 mg of PMMA particles, add them to 50 mL of acetone solution, and heat them in a water bath at a temperature of 90 °C. After the solution cools down, obtain the PMMA solution;

[0086] (4) Preparation of silicon carbide nanowire vertical array thin film: Electrochemically etch the well-cleaned silicon carbide single crystal wafer in step (1) using anodic oxidation. Use the carbon surface of the silicon carbide single crystal wafer facing the platinum electrode as the etching surface and etch in step (2) for 20 minutes (etching parameters: pulsed current, current amplitude 100 mA, pulse time 0.8 ms, duty cycle 50%). After etching, repeatedly wash with ethanol and deionized water to remove the etching solution, and then dry at 60 °C for 15 minutes to obtain the silicon carbide nanowire vertical array thin film;

[0087] (5) Assembly of flexible PETITO / silicon carbide nanowire / PETITO memristor: Transfer the silicon carbide vertical array nanowire thin film obtained in step (4) to the surface of the purchased flexible strip PETITO (electrode width 1 mm), then drop 1 mL of the PMMA solution in step (3), and then press another well-cleaned flexible PETITO with the conductive surface facing down on top. Then, solidify the PMMA by hot pressing at 120 °C with a pressure of 7500 Pa to obtain the flexible PETITO / silicon carbide nanowire / PMMA / PETITO memristor.

[0088] Figure 1 FIG. 13 is a schematic structural diagram of the memristor prepared in Examples 1 - 3, which sequentially includes a bottom electrode, a silicon carbide nanowire thin film, a PMMA thin film, and a top electrode from bottom to top. The silicon carbide nanowire thin film is a silicon carbide nanowire vertical array thin film.

[0089] Figure 2 FIG. 17 is an SEM photograph of the silicon carbide nanowire vertical array thin film prepared in Example 2. It can be clearly seen that the obtained nanowires are arranged neatly and regularly and have a certain flexibility.

[0090] Figure 3 FIG. 21 is a schematic connection diagram of two silicon carbide nanowire vertical array memristors of the present invention. Connecting the bottom electrodes of the two silicon carbide nanowire memristors forms a structure with two inputs at one end and one output at the other end, which is used to test whether it can simulate the function of dendritic nerves.

[0091] Figure 4This is the double-pulse dissimilation data graph of the silicon carbide nanowire vertical array memristor in Embodiment 2 of the present invention. The device shows an increase in conductance under the stimulation of two consecutive pulses, and the postsynaptic current generated by the second pulse stimulation is higher than that generated by the first pulse.

[0092] Figure 5 This is the long-term memory data graph of the silicon carbide nanowire vertical array memristor in Embodiment 2 of the present invention. The device shows a continuous increase in conductance under continuous pulse stimulation. After continuous pulse stimulation, the postsynaptic current of the device is significantly increased compared with the initial value, and the current slowly decreases, forming a long-term memory effect.

[0093] Figure 6 This is the logic operation data graph of the silicon carbide nanowire vertical array memristor in Embodiment 2 of the present invention. Using the dendritic structure with two memristors at both ends for input and one end for output, the operations of logic "AND" and logic "OR" are realized under different read biases.

[0094] Figure 7 This is the "Pavlovian" conditioned reflex data graph of the silicon carbide nanowire vertical array memristor in Embodiment 2 of the present invention. Using low-voltage stimulation as the bell condition and high-voltage stimulation as the food condition, through the combined training of high-voltage and low-voltage, the device can reach the current threshold that can be achieved by high-voltage under low-voltage stimulation.

[0095] Embodiment 4 Preparation of the memristor based on silicon carbide nanowires

[0096] The preparation process is as follows:

[0097] (1) Preparation of the electrochemical deposition solution of silicon carbide nanowires: Weigh 0.02 g of silicon carbide nanowires, 0.05 g of sodium dodecylbenzenesulfonate, and 0.001 g of aluminum nitrate, add them to 50 mL of isopropanol solution, and ultrasonically disperse for 30 min with an ultrasonic power of 800 W to obtain the electrochemical deposition solution of silicon carbide nanowires;

[0098] (2) Preparation of the PMMA solution: Weigh 20 mg of PMMA particles, add them to 20 mL of acetone solution, heat in a water bath at a heating temperature of 70 °C, and obtain the PMMA solution after the solution cools down;

[0099] (3) Preparation of the ITO / silicon carbide nanowire thin film: Use the solution obtained in step (1), and deposit silicon carbide nanowires onto a strip-shaped ITO conductive glass with a width of 1 mm by electrochemical deposition. The deposition electrode is the cathode, the anode electrode is a platinum electrode, the deposition voltage is 50 V, the deposition time is 8 min. After deposition, place it in a vacuum drying oven and dry for 3 hours to obtain the ITO / silicon carbide nanowire thin film;

[0100] (4) Fabrication of ITO / SiC NWs / PMMA / ITO memristor: 0.5 mL of the PMMA solution obtained in step (2) was drop-coated onto the surface of the ITO / silicon carbide nanowire thin film obtained in step (3). Then, an ITO conductive glass with a width of 1 mm was pressed onto it with the conductive surface facing downwards. After that, hot pressing at 100 °C was carried out to solidify the PMMA, with a pressure of 5000 Pa, to obtain the ITO / SiC NWs / PMMA / ITO memristor.

[0101] Example 5 Preparation of a Memristor Based on Silicon Carbide Nanowires

[0102] The manufacturing process is as follows:

[0103] (1) Preparation of the silicon carbide nanowire electrochemical deposition solution: 0.1 g of silicon carbide nanowires, 0.15 g of sodium dodecylbenzenesulfonate, and 0.005 g of aluminum nitrate were weighed and added to 200 mL of isopropanol solution. Ultrasonic dispersion was carried out for 60 min with an ultrasonic power of 1000 W to obtain the silicon carbide nanowire electrochemical deposition solution;

[0104] (2) Preparation of the PMMA solution: 50 mg of PMMA particles were weighed and added to 50 mL of acetone solution. Water bath heating was used, with a heating temperature of 90 °C. After the solution cooled, the PMMA solution was obtained;

[0105] (3) Preparation of the ITO / silicon carbide nanowire thin film: Using the solution obtained in step (1), the silicon carbide nanowires were deposited onto a strip-shaped ITO conductive glass with a width of 1 mm by electrochemical deposition. The deposition electrode was the cathode, and the anode electrode was a platinum electrode. The deposition voltage was 60 V, and the deposition time was 6 min. After deposition, it was placed in a vacuum drying oven and dried for 3 hours. After drying, the ITO / silicon carbide nanowire thin film was obtained;

[0106] (4) Fabrication of ITO / SiC NWs / PMMA / ITO memristor: 1 mL of the PMMA solution obtained in step (2) was drop-coated onto the surface of the ITO / silicon carbide nanowire thin film obtained in step (3). Then, an ITO conductive glass with a width of 1 mm was pressed onto it with the conductive surface facing downwards. After that, hot pressing at 120 °C was carried out to solidify the PMMA, with a pressure of 7000 Pa, to obtain the ITO / SiC NWs / PMMA / ITO memristor.

[0107] Example 6 Preparation of a Memristor with Dendritic Function Based on Silicon Carbide Nanowires

[0108] The manufacturing process is as follows:

[0109] (1) Preparation of the electrochemical deposition solution of silicon carbide nanowires: Weigh 0.1 g of silicon carbide nanowires, 0.15 g of sodium dodecylbenzenesulfonate, and 0.005 g of aluminum nitrate, add them to 200 mL of isopropanol solution, and ultrasonically disperse for 60 min with an ultrasonic power of 1000 W to obtain the electrochemical deposition solution of silicon carbide nanowires;

[0110] (2) Preparation of PMMA solution: Weigh 50 mg of PMMA particles, add them to 50 mL of acetone solution, heat them in a water bath at a heating temperature of 90 °C, and obtain the PMMA solution after the solution cools down;

[0111] (3) Preparation of ITO / silicon carbide nanowire film: Using the solution obtained in step (1), deposit silicon carbide nanowires onto a strip-shaped ITO conductive glass with a width of 1 mm by electrochemical deposition. The deposition electrode is the cathode, the anode electrode is a platinum electrode, the deposition voltage is 60 V, the deposition time is 6 min, and after deposition, place it in a vacuum drying oven for drying for 3 hours to obtain the ITO / silicon carbide nanowire film;

[0112] (4) Assembly of ITO / SiC NWs / PMMA / ITO memristor: Drop 1 mL of the PMMA solution in step (2) onto the surface of the ITO / silicon carbide nanowire film obtained in step (3), then press the ITO conductive glass with a width of 1 mm onto it with the conductive surface facing down, and then heat-press at 120 °C to solidify the PMMA with a pressure of 7000 Pa to obtain the ITO / SiC NWs / PMMA / ITO memristor.

[0113] (5) Assembly of ITO / SiC NWs / PMMA / ITO memristor that can simulate dendritic function: Connect the bottom ITO electrodes of the two ITO / SiC NWs / PMMA / ITO memristors prepared in step (4) together to form a device with a two-end input and one-end output structure, and obtain the ITO / SiC NWs / PMMA / ITO memristor that can simulate dendritic function.

[0114] Example 7 Preparation of a flexible memristor based on silicon carbide nanowires

[0115] The production process is as follows:

[0116] (1) Preparation of the electrochemical deposition solution of silicon carbide nanowires: Weigh 0.1 g of silicon carbide nanowires, 0.15 g of sodium dodecylbenzenesulfonate, and 0.005 g of aluminum nitrate, add them to 200 mL of isopropanol solution, and ultrasonically disperse for 60 min with an ultrasonic power of 1000 W to obtain the electrochemical deposition solution of silicon carbide nanowires;

[0117] (2) Preparation of PMMA solution: Weigh 50 mg of PMMA particles and add them to 50 mL of acetone solution. Heat the solution in a water bath at 90°C. After the solution is cooled, a PMMA solution is obtained.

[0118] (3) Preparation of PETITO / silicon carbide nanowire film: Using the solution obtained in step (1), silicon carbide nanowires were deposited onto a flexible strip of PETITO conductive glass with a width of 1 mm by electrochemical deposition. The deposition electrode was a cathode, the anode electrode was a platinum electrode, the deposition voltage was 60 V, the deposition time was 6 min, and after the deposition was completed, it was placed in a vacuum drying oven for 3 hours to obtain a flexible PETITO / silicon carbide nanowire film after drying;

[0119] (4) Flexible PETITO / SiC NWs / PMMA / PETITO memristor assembly: 1 mL of the PMMA solution of step (2) was drop-coated on the surface of the flexible PETITO / silicon carbide nanowire film obtained in step (3), and then a flexible PETITO with a width of 1 mm was pressed onto it with the conductive surface facing downward, and then the PMMA was solidified by hot pressing at 120°C and a pressure of 7000 Pa to obtain a flexible PETITO / SiC NWs / PMMA / PETITO memristor.

[0120] Figure 8 This is a schematic diagram of the structure of a memristor array based on silicon carbide nanowires according to Embodiment 4-7 of the present invention. Figure 9 This is a schematic diagram of the structure of a memristor based on silicon carbide nanowires according to Embodiment 4-7 of the present invention. Figure 8 The fabricated 5×5 memristor array is shown in Figure 9 The structure of a single memristor is shown, which includes, from top to bottom, an ITO top electrode, a PMMA layer, a silicon carbide nanowire film, and an ITO bottom electrode.

[0121] Figure 10 This is a SEM photograph of the silicon carbide nanowire film prepared in Example 5 of the present invention. It can be seen that the nanowires are arranged uniformly and densely, indicating that the obtained nanowire film is of high quality.

[0122] Figure 11 This is a schematic diagram of the connection between the bottom electrodes of two silicon carbide nanowire memristors of the present invention, forming a structure with two input ends and one output end, which is used to test its ability to simulate dendrite functions.

[0123] Figure 12 This is a double-pulse alienation data diagram of the silicon carbide nanowire memristor under light stimulation in Example 5 of the present invention. The postsynaptic current generated by the device under two consecutive light pulse stimulations gradually increases, and the postsynaptic current generated by the second light pulse is significantly higher than the postsynaptic current generated by the first light pulse.

[0124] Figure 13 This is the long-term memory data graph of the silicon carbide nanowire memristor under optical stimulation in Example 5 of the present invention. When the device is under continuous optical pulse stimulation, the postsynaptic current increases significantly. After the optical pulse stops, the postsynaptic current takes a long time to drop to the initial level, forming a memory effect.

[0125] Figure 14 This is the memory retention time data graph of the silicon carbide nanowire memristor array under optical stimulation in Example 5 of the present invention. The fabricated memristor array is pattern-irradiated, and the irradiated area forms a patterned shape. After different irradiation times, the obtained pattern retention times are different.

[0126] Figure 15 This is the logic operation data graph of the silicon carbide nanowire memristor under optical stimulation in Example 5 of the present invention. By utilizing the different responses of the memristor to different optical bands, logical "AND" and logical "OR" operations can be achieved under different read biases with illumination of different bands.

[0127] Figure 16 This is the "Pavlovian" conditioned reflex data graph of the silicon carbide nanowire memristor under optical stimulation in Example 5 of the present invention. By utilizing the different responses of the device to light of different bands, with 405 nm light as the bell condition and 365 nm light as the food condition, through training with 405 nm and 365 nm light, the response of the device at 405 nm exceeds the specified threshold, realizing the Pavlovian behavior of optical debugging.

[0128] As can be seen from the above embodiments, the multifunctional silicon carbide nanowire memristor prepared by the present invention has a simple structure, is easy to fabricate, has a low cost, and a simple process. Most importantly, it can well simulate the basic functions of biological visual synapses and the information logic processing ability between multiple neurons. Therefore, it can be applied to the field of artificial intelligence, and this method can be used in fields such as artificial neural networks, having broad application prospects.

Claims

1. A preparation method of a memristor based on silicon carbide nanowires, characterized in that, Including: Step 1: Cover the conductive surface of the bottom electrode with a silicon carbide nanowire thin film; Step 2: Coat a PMMA solution on the silicon carbide nanowire thin film obtained in Step 1. Press the top electrode with its conductive surface facing down onto the PMMA solution, and perform hot pressing to solidify the PMMA to obtain a memristor; Step 1 specifically includes: Step 1.1: Electrochemically etch a silicon carbide single crystal wafer using an anodic oxidation method to obtain a silicon carbide nanowire vertical array thin film; Step 1.2: Transfer the silicon carbide nanowire vertical array thin film to the surface of the bottom electrode; Alternatively, Step 1 specifically includes: Step 1.01: Add silicon carbide nanowires, sodium dodecylbenzenesulfonate, and aluminum nitrate to an isopropanol solution, and perform ultrasonic dispersion to obtain a silicon carbide nanowire electrochemical deposition solution; Step 1.02: Use the silicon carbide nanowire electrochemical deposition solution and adopt an electrochemical deposition method to deposit silicon carbide nanowires onto the bottom electrode to form a silicon carbide nanowire thin film.

2. The preparation method of the memristor based on silicon carbide nanowires according to claim 1, characterized in that, In Step 1.1, the electrochemically etching parameters are: pulsed current, current amplitude 80 - 100 mA, pulse time 0.8 ms, duty cycle 50%.

3. The preparation method of the memristor based on silicon carbide nanowires according to claim 1, wherein In Step 1.1, the silicon carbide single crystal wafer is an N-doped 4-H silicon carbide nanocrystal wafer.

4. The preparation method of the memristor based on silicon carbide nanowires according to claim 1, wherein In Step 1.1, the etching solution used for electrochemical etching includes HF, ethanol, and H2O2, and the volume ratio of HF, ethanol, and H2O2 is 3:6:

1.

5. The preparation method of the memristor based on silicon carbide nanowires according to claim 1, wherein, In Step 1.01, the silicon carbide nanowires are 3-C silicon carbide nanowires.

6. The preparation method of the memristor based on silicon carbide nanowires according to claim 1, wherein, The ratio of silicon carbide nanowires, sodium dodecylbenzenesulfonate, aluminum nitrate, and isopropanol is: (0.02 - 0.1) g : (0.05 - 0.15) g : (0.001 - 0.005) g : (50 - 200) mL.

7. The preparation method of the memristor based on silicon carbide nanowires according to claim 1, wherein In the said Step 2, the PMMA solution is an acetone solution of PMMA.

8. The memristor based on silicon carbide nanowires obtained by using the preparation method according to any one of claims 1 to 7, characterized in that, It sequentially includes a bottom electrode, a silicon carbide nanowire thin film, a PMMA thin film, and a top electrode from bottom to top.

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