A test circuit, test structure, and test method

Abstract

This disclosure provides a test circuit, test structure, and test method. The test circuit is applied to a chip stack structure, which includes multiple chips connected by through-silicon via (TSV) modules. The test circuit includes a first test module and a second test module. The two ends of the TSV modules are connected to the first and second test modules, respectively. The first test module is located within the bottom-layer chip, and the second test module is located within the top-layer chip. The test circuit is used to test the TSV modules between the bottom and top-layer chips using the combined methods of the first and second test modules, and to determine the test results. The test results indicate whether the TSV modules are abnormal. This disclosure enables accurate measurement of TSV modules, thereby quickly detecting abnormal TSVs in the chip stack structure.

Description

Technical Field

[0001] This disclosure relates to the field of memory technology, and in particular to a test circuit, test structure, and test method. Background Technology

[0002] For memory, such as Dynamic Random Access Memory (DRAM), three-dimensional designs offer superior performance compared to planar designs. In three-dimensional integrated structures, through-silicon vias (TSVs) are commonly used to achieve vertical interconnects between different chips. TSV technology involves etching through-holes into a silicon substrate and filling these holes with conductive materials such as copper or tungsten to form vertical interconnects between the chips. For memory chips employing three-dimensional integrated structures, TSVs are crucial for ensuring proper chip operation; therefore, testing TSVs is an important task. Summary of the Invention

[0003] This disclosure provides a test circuit, test structure, and test method.

[0004] In a first aspect, embodiments of this disclosure provide a test circuit applied to a chip stack structure, the chip stack structure including multiple chips, and the multiple chips being connected through a through-silicon via (TSV) module; the test circuit includes a first test module and a second test module, the two ends of the TSV module being respectively connected to the first test module and the second test module, and the first test module being disposed within the bottom chip of the multiple chips, and the second test module being disposed within the top chip of the multiple chips, wherein:

[0005] The test circuit is used to test the through-silicon via (TSV) module between the bottom chip and the top chip using the first test module and the second test module, and to determine the test result; wherein the test result is used to indicate whether there is an abnormality in the TSV module.

[0006] In some embodiments, the first test module is configured to determine a first test result based on the voltage change at one end of the through-silicon via module connected to the first test module;

[0007] The second test module is used to determine a second test result based on the voltage change at the other end of the through-silicon via module connected to the second test module;

[0008] The voltage change across the through-silicon via module is provided by the first test module and the second test module, and the first test result and the second test result constitute the test result.

[0009] In some embodiments, the plurality of chips further includes N intermediate chips, and the test circuit further includes N third test modules, wherein the N third test modules correspond to the N intermediate chips; the through-silicon via (TSV) module includes N+1 sub-TSVs, where N is an integer greater than 0; wherein:

[0010] The bottom chip and the first intermediate chip are connected through the first sub-through silicon via; the first end of the first sub-through silicon via is connected to the first test module, and the second end of the first sub-through silicon via is connected to the third test module corresponding to the first intermediate chip;

[0011] The i-th intermediate chip and the (i+1)-th intermediate chip are connected through the (i+1)-th sub-through silicon via, where i is an integer greater than 0 and less than N; the first end of the (i+1)-th sub-through silicon via is connected to the third test module corresponding to the i-th intermediate chip, and the second end of the (i+1)-th sub-through silicon via is connected to the third test module corresponding to the (i+1)-th intermediate chip.

[0012] The Nth intermediate chip is connected to the top-level chip through the (N+1)th sub-through silicon via; the first end of the (N+1)th sub-through silicon via is connected to the third test module corresponding to the Nth intermediate chip, and the second end of the (N+1)th sub-through silicon via is connected to the second test module.

[0013] In some embodiments, the second test module has the same structure as the third test module.

[0014] In some embodiments, the test circuit is further configured to determine whether there are any abnormalities in the N+1 sub-through silicon vias based on the first test result output by the first test module, the N third test results output by the N third test modules, and the second test result output by the second test module.

[0015] In some embodiments, the test circuit is further configured to, when the test result indicates that the through-silicon via module has an abnormality, determine the Nth intermediate chip as the top-level chip, test the remaining sub-through-silicon vias except for the N+1th sub-through-silicon via according to the first test module and the Nth intermediate chip, determine the test result, and if the test result indicates that the through-silicon via module has an abnormality, determine the N-1th intermediate chip as the top-level chip, until the test result is a pass.

[0016] In some embodiments, the first test module includes a charging module and a first trigger module, and the second test module includes a discharging module and a second trigger module; wherein:

[0017] The charging module is used to charge the through-silicon via module to a first level after the first trigger module and the second trigger module receive a power-on signal;

[0018] The discharge module is used to discharge the through-silicon via module to a second level after the charging module charges the through-silicon via module.

[0019] The first trigger module is used to perform triggering processing based on the first level and the second level to obtain a first test result;

[0020] The second trigger module is used to perform triggering processing based on the first level and the second level to obtain a second test result.

[0021] In some embodiments, the first triggering module includes a first trigger and a first inverter. The clock input of the first trigger is connected to the output of the first inverter. The input of the first inverter is connected to the through-silicon via module and the charging module. The input of the first trigger is connected to the first power supply module. The output of the first trigger is used to output the first test result.

[0022] The second trigger module includes a second trigger and a second inverter. The clock input of the second trigger is connected to the output of the second inverter. The input of the second inverter is connected to the through-silicon via module and the discharge module. The input of the second trigger is connected to the second power supply module. The output of the second trigger is used to output the second test result.

[0023] In some embodiments, the first test module further includes a first transistor, the input terminal of the first inverter is connected to the first terminal of the first transistor, the second terminal of the first transistor is connected to the first ground module, and the gate of the first transistor is connected to the inverted signal of the power-on signal.

[0024] The second test module also includes a second transistor, the input terminal of the second inverter is connected to the first terminal of the second transistor, the second terminal of the second transistor is connected to the second ground module, and the gate of the second transistor is connected to the inverted signal of the power-on signal.

[0025] In some embodiments, the control terminal of the charging module is connected to the first drive signal, the control terminal of the discharge module in the second test module is connected to the second drive signal, and the control terminal of the discharge module in the third test module is connected to the inverted signal of the second drive signal.

[0026] In some embodiments, the first triggering module further includes a third inverter, and the second triggering module further includes a fourth inverter, wherein:

[0027] The input terminal of the third inverter is connected to the output terminal of the first inverter, and the output terminal of the third inverter is connected to the input terminal of the first inverter.

[0028] The input terminal of the fourth inverter is connected to the output terminal of the second inverter, and the output terminal of the fourth inverter is connected to the input terminal of the second inverter.

[0029] In some embodiments, the test circuit further includes N+2 register modules, wherein:

[0030] In the underlying chip, the register module is connected to the output of the first trigger and is used to save the first test result;

[0031] In the intermediate chip, the register module is connected to the output of the second flip-flop and is used to save the third test result;

[0032] In the top-level chip, the register module is connected to the output of the second flip-flop and is used to save the second test result.

[0033] In some embodiments, the test circuit is further configured to determine that the test result indicates that the through-silicon via module is not abnormal when both the first test result and the second test result are first values; and the test circuit is further configured to determine that the test result indicates that the through-silicon via module is abnormal when at most one of the first test result and the second test result is a first value.

[0034] In some embodiments, the test circuit is further configured to determine that the (j+1)th sub-silicon via is abnormal if the first test result output by the first test module is a second value, and the third test result output by the third test module corresponding to the 1st to jth intermediate chips is a second value, the third test result output by the third test module corresponding to the (j+1)th to Nth intermediate chips is a first value, and the second test result output by the second test module is a first value;

[0035] The test circuit is further configured to determine that the (j+1)th sub-silicon via is abnormal if the first test result output by the first test module is a first value, and the third test result output by the third test module corresponding to the 1st to jth intermediate chips is a first value, the third test result output by the third test module in the (j+1)th to Nth intermediate chips is a second value, and the second test result output by the second test module is a second value.

[0036] In some embodiments, the underlying chip among the plurality of chips is a logic chip, and the chips other than the underlying chip among the plurality of chips are memory chips.

[0037] Secondly, embodiments of this disclosure provide a test structure applied to a chip stacking structure, the chip stacking structure comprising multiple chips, the multiple chips being connected through silicon via modules and at least one redundant silicon via module, and the test structure comprising the test circuit as described in the first aspect, wherein:

[0038] The test structure is used to select a redundant through-silicon via module to replace the through-silicon via module if the test circuit detects an abnormality in the through-silicon via module.

[0039] In some embodiments, the test structure further includes at least one redundant test circuit, and the redundant test circuit has the same structure and function as the test circuit; wherein, the redundant test circuit is used to test whether the corresponding redundant through-silicon via module is abnormal.

[0040] Thirdly, embodiments of this disclosure provide a test method applied to the test circuit described in the first aspect, the method comprising:

[0041] The test results are determined by jointly testing the through-silicon via (TSV) module between the bottom-layer chip and the top-layer chip using the first test module and the second test module; wherein the test results are used to indicate whether there is an abnormality in the TSV module.

[0042] This disclosure provides a test circuit, test structure, and test method. The test circuit is applied to a chip stack structure, which includes multiple chips connected by through-silicon via (TSV) modules. The test circuit includes a first test module and a second test module. The two ends of the TSV modules are respectively connected to the first test module and the second test module. The first test module is disposed within the bottom chip of the multiple chips, and the second test module is disposed within the top chip of the multiple chips. The test circuit is used to test the TSV modules between the bottom chip and the top chip using the first test module and the second test module, and to determine the test result. The test result is used to indicate whether there is an abnormality in the TSV modules. Thus, by setting a first test module in the bottom chip of the chip stack structure and a second test module in the top chip of the chip stack structure, and connecting the first and second test modules to the two ends of the through-silicon via (TSV) module that runs through the chip stack structure, the entire TSV module can be tested using only the first test module in the bottom chip and the second test module in the top chip to determine whether there are any abnormalities in the TSV module. This simplifies the testing method, achieves accurate measurement of the TSV module, and enables rapid detection of abnormal TSVs in the chip stack structure. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of the composition structure of a TSV test circuit;

[0044] Figure 2 This is a schematic diagram of the composition of a chip stacking structure provided in an embodiment of the present disclosure;

[0045] Figure 3 A schematic diagram of the circuit structure of a test circuit provided in an embodiment of this disclosure;

[0046] Figure 4 A signal timing diagram provided for an embodiment of this disclosure;

[0047] Figure 5 This is a schematic diagram of the composition of another chip stacking structure provided in an embodiment of the present disclosure;

[0048] Figure 6 A schematic diagram of the circuit structure of another test circuit provided in an embodiment of this disclosure;

[0049] Figure 7 This is a schematic diagram of the composition structure of another chip stacking structure provided in the embodiments of this disclosure;

[0050] Figure 8 This is a schematic diagram of the composition of a test structure provided in an embodiment of the present disclosure;

[0051] Figure 9 This is a schematic diagram of a circuit structure for a test structure provided in an embodiment of the present disclosure;

[0052] Figure 10 This is a flowchart illustrating a testing method provided in an embodiment of the present disclosure. Detailed Implementation

[0053] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the disclosure are shown in the accompanying drawings.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0055] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0056] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0057] Figure 1 A schematic diagram of the structure of a TSV test circuit is shown. (For example...) Figure 1 As shown, the multi-layer chips are connected together via TSVs, and the TSV connection method is multidrop connection. Figure 1 In this system, nine TSVs form a TSV group, and this TSV group spans multiple chips. Figure 1 The diagram shows four TSV groups. Taking one TSV group as an example, when testing this TSV group, the top die and the base die are first located. Then, test points are connected to the TSVs on the top die and the base die respectively to test the DC performance of the TSVs and obtain the test results. The test points are as follows: Figure 1The test involves bottom-level and top-level test points. Test results include a pass flag (indicating a successful test) and a fail flag (indicating a failed test). Additionally, a robust TSV (telematics unit) is needed to transmit the pass / fail flags to each chip layer. This testing method has the following drawbacks: the robust TSV is generally shared; if the robust TSV fails, the entire chip's multidrop TSV repair function will fail; and additional circuitry is required to transmit and receive the pass / fail flags.

[0058] Based on this, this disclosure provides a test circuit applied to a chip stack structure, the chip stack structure including multiple chips, and the multiple chips are connected by through-silicon via (TSV) modules; the test circuit includes a first test module and a second test module, the two ends of the TSV modules are respectively connected to the first test module and the second test module, and the first test module is disposed in the bottom chip of the multiple chips, and the second test module is disposed in the top chip of the multiple chips, wherein: the test circuit is used to test the TSV modules between the bottom chip and the top chip according to the joint testing of the first test module and the second test module, and determine the test result; wherein, the test result is used to indicate whether there is an abnormality in the TSV modules. Thus, by setting a first test module in the bottom chip of the chip stack structure and a second test module in the top chip of the chip stack structure, and connecting the first and second test modules to the two ends of the through-silicon via (TSV) module that runs through the chip stack structure, the entire TSV module can be tested using only the first test module in the bottom chip and the second test module in the top chip to determine whether there are any abnormalities in the TSV module. This simplifies the testing method, achieves accurate measurement of the TSV module, and enables rapid detection of abnormal TSVs in the chip stack structure.

[0059] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0060] In one embodiment of this disclosure, see [link to embodiment]. Figure 2 This illustration shows a schematic diagram of the composition of a chip stacking structure 10 provided in an embodiment of this disclosure, with a test circuit applied to the chip stacking structure 10. For example... Figure 2 As shown, the chip stack structure 10 includes multiple chips, and the multiple chips are connected through silicon via modules 13; the test circuit includes a first test module 14 and a second test module 15, with the two ends of the silicon via module 13 connected to the first test module 14 and the second test module 15 respectively, and the first test module 14 is disposed in the bottom chip 11 of the multiple chips, and the second test module is disposed in the top chip 12 of the multiple chips, wherein:

[0061] The test circuit is used to test the through-silicon via module 13 between the bottom chip 11 and the top chip 12 together with the first test module 14 and the second test module 15, and determine the test results; wherein the test results are used to indicate whether there is an abnormality in the through-silicon via module 13.

[0062] It should be noted that in memory (such as DRAM), a stacked structure can be used to increase storage capacity. For example... Figure 2 As shown, in the chip stack structure 10, multiple chips are stacked, and through-silicon via (TSV) modules 13 penetrate multiple chips in the chip stack structure 10. The TSV modules 13 are used to achieve vertical interconnection between multiple chips. If the TSV modules 13 malfunction, it will cause problems such as signal transmission failure or signal transmission errors between chips. In order to detect whether the TSV modules 13 are malfunctioning in a timely manner, this embodiment of the disclosure sets up a test circuit in the chip stack structure 10 to test the TSV modules 13.

[0063] In other words, the test circuit provided in this disclosure embodiment can be applied to, for example... Figure 2 The chip stack structure 10 shown is as follows. The chip stack structure 10 includes at least a bottom chip 11 and a top chip 12, which are connected via through-silicon via (TSV) modules 13. The test circuit includes a first test module 14 disposed in the bottom chip 11 and a second test module 15 disposed in the top chip 12. The first test module 14 is connected to one end of the TSV module 13 located in the bottom chip 14, and the second test module 15 is connected to one end of the TSV module 13 located in the top chip 15. Testing of the TSV module 13 is performed jointly by the first test module 14 and the second test module 15. Alternatively, the bottom chip 11 and the top chip 12 can be two adjacent chips, in which case there is no intermediate chip between them, or, as... Figure 1 As shown, several intermediate chips may also be included between the bottom chip 11 and the top chip 12. In any case, the through-silicon via module 13 between the top chip 12 and the bottom chip 11 can be tested using only the first test module 14 and the second test module 15.

[0064] In this way, since the first test module 14 and the second test module 15 are respectively connected to the two ends of the through-silicon via (TSV) module 13, the TSV module 13 will be unable to transmit signals normally if there is an abnormality at any position of the TSV module 13. Therefore, the test circuit can detect whether there is an abnormality in the TSV module 13. Based on this method, the detection of the TSV module 13 can be achieved simply by setting the first test module 14 and the second test module 15 in the bottom chip 11 and the top chip 12, respectively.

[0065] Furthermore, in some embodiments, the first test module 14 is used to determine a first test result based on the voltage change at one end of the through-silicon via module 13 connected to the first test module 14;

[0066] The second test module 15 is used to determine the second test result based on the voltage change at the other end of the through-silicon via module 13 connected to the second test module 15;

[0067] The voltage change across the through-silicon via module 13 is provided by the first test module 14 and the second test module 15, and the first test result and the second test result constitute the test result.

[0068] It should be noted that the test results include the first test result output by the first test module 14 and the second test result output by the second test module 15. The first test module 14 and the second test module 15 can charge or discharge the through-silicon via (TSV) module 13, thereby causing a voltage change across the TSV module 13 through the charging and discharging process. The end of the TSV module 13 connected to the first test module 14 is designated as the first end, and the end connected to the second test module 15 is designated as the second end. In the bottom-layer chip 11, the first test module 14 outputs the first test result based on the voltage change at the first end of the TSV module 13; in the top-layer chip 12, the second test module 15 outputs the second test result based on the voltage change at the second end of the TSV module 13. The voltage levels provided by the first test module 14 and the second test module 15 to the TSV 13 are different, thus generating the voltage change.

[0069] It should also be noted that if the through-silicon via (TSV) module 13 is functioning correctly, voltage changes will occur normally at both ends of the TSV module 13 during the test. In this case, both the first and second test results will be normal. However, if the TSV module is faulty, the TSV module 13 will be unable to transmit voltage changes normally. For example, if there are abnormalities in both bidirectional transmission of the TSV module 13, the voltage provided by the first test module 14 cannot be transmitted from the first end to the second end, and the voltage provided by the second test module 15 cannot be transmitted from the second end to the first end. In this case, no voltage change will occur at either end of the TSV module 13 during the test, and both the first and second test results will be abnormal.

[0070] If there is an anomaly in the voltage transmission from the first end to the second end of the through-silicon via (TSV) module 13, the voltage provided by the first test module 14 cannot be transmitted from the first end to the second end, while the voltage provided by the second test module 15 can be transmitted from the second end to the first end. During the test, the voltage at the first end of the TSV module 13 will change, but the voltage at the second end will not change. In this case, the first test result is normal, and the second test result is abnormal.

[0071] If there is an anomaly in the voltage transmission from the second end to the first end of the through-silicon via (TSV) module 13, then although the voltage provided by the first test module 14 can be transmitted from the first end to the second end, the voltage provided by the second test module 15 cannot be transmitted from the second end to the first end. Therefore, during the test, the voltage at the second end of the TSV module 13 will change, while the voltage at the first end will not change. In this case, the first test result is abnormal, and the second test result is normal.

[0072] As can be seen, when the through-silicon via module 13 is abnormal, at least one of the first test module 14 and the second test module 15 will output an abnormal test result, thereby enabling the detection of the through-silicon via module 13. At the same time, it is also possible to determine which direction the through-silicon via module 13 has a transmission abnormality based on the first test result and the second test result.

[0073] Furthermore, for the test circuit, see [link / reference]. Figure 3 This illustrates a schematic diagram of the circuit structure of a test circuit 101 provided in an embodiment of this disclosure. Figure 3 As shown, in some embodiments, the first test module 14 includes a charging module 141 and a first trigger module 142, and the second test module 15 includes a discharging module 151 and a second trigger module 152; wherein:

[0074] The charging module 141 is used to charge the through-silicon via module 13 to a first level after the first trigger module 142 and the second trigger module 152 receive the power-on signal;

[0075] The discharge module 151 is used to discharge the through-silicon via module 13 to a second level after the charging module 141 charges the through-silicon via module 13.

[0076] The first trigger module 142 is used to perform triggering processing based on the first level and the second level to obtain the first test result;

[0077] The second trigger module 152 is used to perform triggering processing based on the first level and the second level to obtain the second test result.

[0078] It should be noted that, as Figure 3As shown, the charging module 141 is connected to the first end of the through-silicon via (TSV) module 13, and is also connected to the first trigger module 142; the discharging module 151 is connected to the second end of the TSV module 13, and is also connected to the second trigger module 152. P_on represents the power-on signal. When the TSV module 13 needs to be tested, the power-on signal is in a valid state; otherwise, it is in an invalid state. In this embodiment, the example is described as a logic 1 with a high level for the valid state and a logic 0 with a low level for the invalid state. However, the valid state can also be a logic 0 with a low level, and the invalid state can also be a logic 0 with a high level; no specific limitation is made here.

[0079] It should also be noted that after both the first trigger module 142 and the second trigger module 152 receive the power-on signal, both the first trigger module 142 and the second trigger module 152 enter the test state. After entering the test state, the charging module 141 first charges the through-silicon via module 13. If there is no abnormality in the through-silicon via module 13, then the first and second terminals of the through-silicon via module 13 are both charged to the first level. Here, the first level can indicate a high logic 1. After the through-silicon via module 13 is charged to the first level, the discharging module 151 discharges the through-silicon via module 13. If there is no abnormality in the through-silicon via module 13, then the first and second terminals of the through-silicon via module 13 are both discharged to the second level. Here, the second level can indicate a low logic 0.

[0080] In this way, since the through-silicon via module 13 is first charged to the first level and then discharged to the second level, a voltage change will occur at both ends of the through-silicon via module 13 during this process. Based on this voltage change, the first trigger module 142 and the second trigger module 152 are triggered, thereby outputting the first test result and the second test result respectively.

[0081] As mentioned above, if there is no abnormality in the through-silicon via (TSV) module 13, voltage changes will occur at both ends of the TSV module 13, and both the first and second test results will be normal. If there is an abnormality in both bidirectional transmission of the TSV module 13, then when charging the TSV module 13, the second end cannot be charged to the first level, and when discharging, the first end cannot be discharged to the second level. No voltage change will occur at either end of the TSV module 13, and both the first and second test results will be abnormal.

[0082] If the through-silicon via module 13 has an abnormality in the transmission from the first end to the second end, or if the through-silicon via module 13 has an abnormality in transmitting a high level, then during charging, only the first end can be charged to the first level, while the second end cannot be charged to the first level. During discharging, the first end can be discharged to the second level. At this time, the first end will undergo a normal voltage change, triggering the first trigger module 142, so the first trigger module 142 can output a normal first test result. However, the second end is not charged to the first level, and no voltage change will occur, so the second trigger module 152 cannot be triggered. Therefore, the second test result is abnormal.

[0083] If there is an anomaly in the transmission from the second end to the first end of the through-silicon via module 13, or if there is an anomaly in the transmission of a low level of the through-silicon via module 13, then during charging, although both the first end and the second end can be charged to the first level, during discharging, only the second end can be discharged to the second level. At this time, the second end will undergo a normal voltage change, triggering the second trigger module 152, so the second trigger module 152 can output a normal second test result. However, since the first end is not discharged to the second level, no voltage change will occur, and the first trigger module 142 cannot be triggered, so the first test result is abnormal.

[0084] Thus, in this embodiment of the present disclosure, the through-silicon via (TSV) module 13 is charged and discharged by the charging module 141 and the discharging module 151, respectively. During the charging and discharging process, the voltage across the two ends of the TSV module 13 changes, triggering the first trigger module 142 and the second trigger module 152. Only when the TSV module 13 is not abnormal will the first trigger module 142 and the second trigger module 152 be triggered, outputting normal first and second test results. Otherwise, abnormal test results will be output, thereby realizing the testing of the TSV module 13.

[0085] Furthermore, regarding the specific composition of the test circuit 101, such as... Figure 3 As shown, in some embodiments, the first trigger module 142 includes a first trigger 1421 and a first inverter 1422. The clock input terminal CLK of the first trigger 1421 is connected to the output terminal of the first inverter 1422. The input terminal of the first inverter 1422 is connected to the through-silicon via module 13 and the charging module 141. The input terminal D of the first trigger 1421 is connected to the first power supply module VDD1. The output terminal Q of the first trigger 1421 is used to output the first test result.

[0086] The second trigger module 152 includes a second trigger 1521 and a second inverter 1522. The clock input terminal CLK of the second trigger 1521 is connected to the output terminal of the second inverter 1522. The input terminal of the second inverter 1522 is connected to the through-silicon via module 13 and the discharge module 151. The input terminal D of the second trigger 1521 is connected to the second power supply module VDD2. The output terminal Q of the second trigger 1521 is used to output the second test result.

[0087] The first test module 14 also includes a first transistor T1, the input terminal of the first inverter 1422 is connected to the first terminal of the first transistor T1, the second terminal of the first transistor T1 is connected to the first ground module VSS1, and the gate of the first transistor T1 is connected to the inverted signal of the power-on signal.

[0088] The second test module 15 also includes a second transistor T2. The input terminal of the second inverter 1522 is connected to the first terminal of the second transistor T2, the second terminal of the second transistor T2 is connected to the second ground module VSS2, and the gate of the second transistor T2 is connected to the inverted signal of the power-on signal.

[0089] The charging module 141 may include a third transistor T3, the gate of the third transistor T3 receives a first drive signal, the first terminal of the third transistor T3 is connected to the input terminal of the first inverter 1422 and the first terminal of the through-silicon via module 13, and the second terminal of the third transistor T3 is connected to the third power module VDD3.

[0090] The discharge module 151 may include a fourth transistor T4, the gate of which receives a second drive signal, the first terminal of which is connected to the input terminal of the second inverter 1522 and the second terminal of the through-silicon via module 13, and the second terminal of which is connected to the third grounding module VDD3.

[0091] It should be noted that, in Figure 3 In this diagram, the first power module VDD1, the second power module VDD2, and the third power module VDD3 can be different modules or the same power supply; no specific limitation is made here. Similarly, the first ground module VSS1, the second ground module VSS2, and the third ground module VSS3 can be different modules or the same ground terminal; no specific limitation is made here. The voltage levels provided by VDD1 / VDD2 / VDD3 are first values, and the voltage levels provided by VSS1 / VSS2 / VSS3 are second values. The first value represents a high logic level (logo 1), and the second value represents a low logic level (logo 0).

[0092] like Figure 3As shown, the first transistor T1, the second transistor T2 and the fourth transistor T4 are all N-type metal-oxide-semiconductor field-effect transistors (NMOS transistors), and the third transistor T3 is a P-type metal-oxide-semiconductor field-effect transistor (PMOS transistor).

[0093] The gates of both the first transistor T1 and the second transistor T2 receive the inverted signal of the power-on signal (in the diagram). (This is indicated by the diagram). Thus, when no test is performed, the power-on signal is in an invalid state (i.e., a low logic 0), and the inverted power-on signal is in a valid state (a high logic 1). At this time, in... Under the control of [the transistor], the first transistor T1 and the second transistor T2 are in the on state. For example... Figure 3 As shown, since the first terminal of the first transistor T1 is connected to the input terminal of the first inverter 1422 and the first terminal of the through-silicon via module 13, and the first terminal of the second transistor T2 is connected to the input terminal of the second inverter 1522 and the second terminal of the through-silicon via module 13, the input terminal of the first inverter 1422 receives the second value, inverts it, and outputs the first value to the clock input terminal CLK of the first flip-flop 1421. The input terminal of the second inverter 1522 also receives the second value, inverts it, and outputs the first value to the clock input terminal CLK of the second flip-flop 1521. During this period, the control terminals RN of the first flip-flop 1421 and the second flip-flop 1422 do not receive a power-on signal, or in other words, they receive a power-on signal that is in an invalid state.

[0094] After the test begins, the power-on signal is active. The first flip-flop 1421 and the second flip-flop 1521 receive the power-on signal and turn on, entering the test state. Since the inverted signal of the power-on signal is inactive, the first transistor T1 and the second transistor T2 are not conducting. Upon entering the test state, a first drive signal (denoted by PDRV in the diagram) is provided to the third transistor T3, causing it to conduct. Since the third transistor T3 is a PMOS transistor, the level of the first drive signal is the second value (logic 0 for low level). After the third transistor T3 is turned on, the high level provided by VDD3 is transmitted, charging both ends of the through-silicon via module 13 to the first level, where the level is the first value (logic 1 for high level). Simultaneously, the inputs of the first inverter 1422 and the second inverter 1522 also receive the first value, invert it, and output the second value to the clock receiver CLK of the first flip-flop 1421 and the second flip-flop 1521.

[0095] Next, instead of providing the first drive signal to the third transistor T3, a second drive signal (denoted as NDRV in the diagram) is provided to the fourth transistor T4, causing the fourth transistor T4 to conduct. Since the fourth transistor T4 is an NMOS transistor, the level of the second drive signal is the first value. After the fourth transistor T4 conducts, it transmits the low level provided by VSS3, thereby discharging the two ends of the through-silicon via module 13 to the second level, where the level is the second value. Simultaneously, the input terminals of the first inverter 1422 and the second inverter 1522 also receive the second value, invert it, and output the first value to the clock receiving terminals CLK of the first flip-flop 1421 and the second flip-flop 1521. Thus, for the first flip-flop 1421 and the second flip-flop 1521, the signal received by the clock receiver CLK changes from the second value to the first value, forming a rising edge, thereby triggering the first flip-flop 1421 and the second flip-flop 1521. The first flip-flop 1421 and the second flip-flop 1521 sample the signal received at their input terminals D according to the signal received at the clock input terminal CLK, and output the test result at their output terminal Q. Since the input terminal D of the first flip-flop 1421 is connected to VDD1 and the input terminal D of the second flip-flop 1521 is connected to VDD2, and VDD1 / VDD2 provides a high-level first value, then when the through-silicon via module 13 is functioning normally, the first test result output by the output terminal Q of the first flip-flop 1421 and the second test result output by the output terminal Q of the second flip-flop 1521 are both the first value.

[0096] If there is an anomaly in both bidirectional transmission of the through-silicon via module 13, then since there will be no voltage change at either end of the through-silicon via module 13, a rising edge cannot be formed at the clock input terminal CLK of the first flip-flop 1421 and the second flip-flop 1521. As a result, the first flip-flop 1421 and the second flip-flop 1521 will not be triggered, and both the first test result and the second test result will be the second value.

[0097] If there is an anomaly in the transmission from the first terminal to the second terminal of the through-silicon via (TSV) module 13, or if there is an anomaly in the transmission of a high-level signal in the TSV module 13, then only a voltage change occurs at the first terminal of the TSV module 13. This causes a rising edge to form at the clock input CLK of the first flip-flop 1421, triggering the first flip-flop 1421. Therefore, the first flip-flop 1421 can sample the signal provided by VDD1 and output a first value. However, no rising edge forms at the clock input CLK of the second flip-flop 1521, so the second flip-flop 1521 cannot sample the signal provided by VDD2. Therefore, the second test result output by the second flip-flop 1521 is the second value.

[0098] If there is an anomaly in the transmission from the second terminal to the first terminal of the through-silicon via (TSV) module 13, or if there is an anomaly in the transmission of a low level in the TSV module 13, then only a voltage change occurs at the second terminal of the TSV module 13. This causes a rising edge to form at the clock input CLK of the second flip-flop 1521, triggering the second flip-flop 1521. Therefore, the second flip-flop 1521 can sample the signal provided by VDD2 and output the first value. However, if the clock input CLK of the first flip-flop 1421 does not form a rising edge, the first flip-flop 1421 cannot sample the signal provided by VDD1, and therefore the first test result output by the first flip-flop 1421 is the second value.

[0099] In other words, the test circuit 101 is used to determine that the test result is that the through-silicon via module 13 is not abnormal when both the first test result and the second test result are the first value, and the test circuit 101 is also used to determine that the test result is that the through-silicon via module 13 is abnormal when at most one of the first test result and the second test result is the first value.

[0100] Furthermore, this embodiment is illustrated using the example of a rising edge triggered flip-flop, where both the first flip-flop 1421 and the second flip-flop 1521 are triggered. For other types of flip-flops, only adaptive adjustments to the circuit are needed to still achieve the testing of the through-silicon via module 13. The design concept is the same, and will not be elaborated here.

[0101] It should also be noted that, for the first flip-flop 1421 and the second flip-flop 1521, the first flip-flop 1421 is also used to reset its output when no power-on signal is received; similarly, the second flip-flop 1521 is also used to reset its output when no power-on signal is received. This method of resetting the flip-flop outputs when no test is being performed avoids signal interference that could lead to inaccurate test results.

[0102] Furthermore, such as Figure 3 As shown, in some embodiments, the first trigger module 142 further includes a third inverter 1423, and the second trigger module 152 further includes a fourth inverter 1523, wherein:

[0103] The input terminal of the third inverter 1423 is connected to the output terminal of the first inverter 1422, and the output terminal of the third inverter 1423 is connected to the input terminal of the first inverter 1422.

[0104] The input terminal of the fourth inverter 1523 is connected to the output terminal of the second inverter 1522, and the output terminal of the fourth inverter 1523 is connected to the input terminal of the second inverter 1522.

[0105] It should be noted that, as Figure 3 As shown, the first trigger module 142 also includes a third inverter 1423, which is connected end-to-end with the first inverter 1422 to form a latch structure, ensuring the reliability of the signal input to the clock input terminal CLK of the first flip-flop 1421. The second trigger module 152 also includes a fourth inverter 1523, which is connected end-to-end with the second inverter 1522 to form a latch structure, ensuring the reliability of the signal input to the clock input terminal CLK of the second flip-flop 1521.

[0106] Furthermore, Figure 4 A signal timing diagram provided by a disclosed embodiment is shown below, in conjunction with... Figure 4 Briefly describe the test results output by the test circuit. Among them, The signal is the inverted power-on signal. P_on represents the power-on signal, PDRV represents the first drive signal, NDRV represents the second drive signal, TSV (abnormal) represents the voltage change of the through-silicon via module (first terminal) with bidirectional transmission abnormality, P (abnormal) represents the first test result when the through-silicon via module has bidirectional transmission abnormality, TSV (normal) represents the voltage change of the through-silicon via module (first terminal) with normal operation, and P (normal) represents the first test result when the through-silicon via module is normal.

[0107] Combination Figure 3 and Figure 4 As shown, before point A, i.e. before power-on, the power-on signal is low and the inverse signal of the power-on signal is high. At this time, the control terminal RN of the first flip-flop 1421 is low, the gate of the first transistor T1 is high, the first transistor T1 is turned on, which grounds the input terminal of the first inverter 1422 and outputs a high level, i.e., sets the clock input terminal CLK of the first flip-flop 1421 to "1".

[0108] At point B, the first drive signal PDRV is low, causing the third transistor T3 to conduct and charge the through-silicon via module 13, as shown in TSV (normally). The input of the first inverter 1422 is high, so the output of the first inverter 1422 outputs a low level to the clock input CLK of the first flip-flop 1421, that is, sets the clock input CLK of the first flip-flop 1421 to "0".

[0109] At point C, the first drive signal PDRV changes from low to high, causing the third transistor T3 to turn off.

[0110] At point D, the second drive signal NDRV is high, causing the fourth transistor T4 to conduct and the through-silicon via module 13 to discharge, as shown in TSV (normal). The input of the first inverter 1422 becomes low, and the output of the first inverter 1422 outputs a high level to the clock input CLK of the first flip-flop 1421, thereby generating a rising edge at the clock input CLK of the first flip-flop 1421. The output Q of the first flip-flop 1421 outputs a high level, as shown in P (normal).

[0111] For through-silicon via (TSV) modules with bidirectional transmission anomalies, as shown in TSV (anomaly), the voltage of the TSV module does not change during charging and discharging. Correspondingly, the clock input CLK of the first flip-flop 1421 cannot detect the rising edge, the first flip-flop 1421 is not triggered, and its output Q outputs a low level, as shown in P (anomaly).

[0112] The testing process for unidirectional transmission anomalies and the second detection circuit 15 is similar, and will not be repeated here.

[0113] Furthermore, such as Figure 3 As shown, the test circuit 101 may further include a first register module 143 and a second register module 153, wherein:

[0114] The first register module 143 is connected to the output of the first trigger 1421 and is used to save the first test result;

[0115] The second register module 153 is connected to the output of the second trigger 1521 and is used to save the second test result.

[0116] It should be noted that, in this embodiment, a register module can also be configured to save the corresponding test results. The first register module 143 and the second register module 153 can both be registers. These registers can be existing registers within the memory, but for ease of description, they are categorized under the test circuit; alternatively, they can be newly added registers to save the test results. Regardless of the method, no additional external components are needed to resend the test results to the chip, which simplifies the circuit structure.

[0117] Furthermore, such as Figure 2 As shown, one or more intermediate chips may be included between the bottom chip 11 and the top chip 12. For details, see [link to documentation]. Figure 5 It shows a schematic diagram of the composition structure of another chip stacking structure 10 provided in an embodiment of this disclosure, such as... Figure 5As shown, in some embodiments, the multiple chips further include N intermediate chips 16, and the test circuit further includes N third test modules 17, with a correspondence between the N third test modules 16 and the N intermediate chips 17; the through-silicon via module 13 includes N+1 sub-through-silicon vias, where N is an integer greater than 0; wherein:

[0118] The bottom chip 11 is connected to the first intermediate chip 16 through the first sub-through silicon via (TSV1); the first end of the first TSV1 is connected to the first test module 14, and the second end of the first TSV1 is connected to the third test module 17 corresponding to the first intermediate chip 16.

[0119] The i-th intermediate chip 17 and the (i+1)-th intermediate chip 17 are connected through the (i+1)-th sub-through silicon via, where i is an integer greater than 0 and less than N; the first end of the (i+1)-th sub-through silicon via is connected to the third test module 17 corresponding to the i-th intermediate chip 16, and the second end of the (i+1)-th sub-through silicon via is connected to the third test module 17 corresponding to the (i+1)-th intermediate chip 16.

[0120] The Nth intermediate chip 16 is connected to the top chip 12 through the (N+1)th sub-through silicon via; the first end of the (N+1)th sub-through silicon via is connected to the third test module 17 corresponding to the Nth intermediate chip 16, and the second end of the (N+1)th sub-through silicon via is connected to the second test module 15.

[0121] It should be noted that, Figure 5 The left image is a schematic diagram of the chip stack structure 10, and the right image is a schematic diagram of the through-silicon via (TSV) module 13 and the test circuit 101 in the chip stack structure 10. Figure 5 In the example, N equals 7, so the chip stack structure 10 from bottom to top includes: bottom chip 11 (also called Base Die), 7 intermediate chips 16 (referred to as Die0, Die1, Die2, Die3, Die4, Die5 and Die6 respectively) and top chip 12 (also called Die7 or Top Die); the through silicon via module 13 includes 8 sub-through silicon vias (referred to as TSV1, TSV2, TSV3, TSV4, TSV5, TSV6, TSV7 and TSV8 respectively).

[0122] It should also be noted that in DRAM, multiple chips are typically divided into logic chips and memory chips, such as... Figure 5 As shown, the bottom-level chip 11 among the multiple chips is a logic chip, and the chips other than the bottom-level chip 11 are memory chips. Therefore, in Figure 5 In the middle, the top-level chip 12 is also referred to as Die7.

[0123] It should also be noted that the second test module 15 and the third test module 17 have the same structure. They are referred to here as the second test module 15 and the third test module 17 only for ease of description.

[0124] Furthermore, when testing the through-silicon via (TSV) module 13, it is necessary to first determine the top-level chip from multiple memory chips. One method for determining the top-level chip is to store a preset number in the Base Die, which corresponds to the number of the Top Die. Then, read the number of each memory chip individually. If the number of a memory chip matches the preset number stored in the Base Die, it is determined to be the Top Die. In this case, the memory chips are typically numbered with the chip adjacent to the Base Die starting at 0000 and increasing sequentially. Alternatively, when numbering the memory chips, the chip adjacent to the Base Die can be assigned the largest number, and the Top Die the smallest number at 0000. Therefore, when a memory chip with the number 0000 is detected, it is determined to be the Top Die.

[0125] It is understandable that regardless of whether there is an intermediate chip 16 between the top-level chip 12 and the bottom-level chip 11, the through-silicon via (TSV) module 13 can be tested using only the first test module 14 and the second test module 15. Since the TSV module 13 can be composed of several sub-TSVs, when any one of the sub-TSVs is abnormal, it will cause a voltage change at one end of the sub-TSV connected to the first test module 14, and / or a voltage change at one end of the sub-TSV connected to the second test module 15, thereby outputting an abnormal first test result and / or second test result.

[0126] When the chip stack structure 10 includes at least one intermediate chip 16, the presence of abnormal sub-through silicon vias in the through silicon via module 13 can also be determined based on the test results. Therefore, in some embodiments, the test circuit is further configured to determine whether N+1 sub-through silicon vias are abnormal based on the first test result output by the first test module 14, the N third test results output by the N third test modules 17, and the second test result output by the second test module 15.

[0127] It should be noted that, see Figure 6 This illustrates a schematic diagram of the circuit structure of another test circuit 101 provided in an embodiment of this disclosure. Figure 6 As shown, N third test modules 17 and N sub-through silicon vias (TSVs) are connected between the first test module 14 and the second test module 15. The structure of the third test module 17 is the same as that of the second test module 15, and its circuit composition will not be described further here. Additionally, in Figure 6 In this diagram, the first power module, the second power module, and the third power module are all represented by VDD, and the first grounding module, the second grounding module, and the third grounding module are all represented by VSS.

[0128] It should be noted that when testing the through-silicon via (TSV) module, in the second test module 15, the discharge module 151 needs to receive the second drive signal NDRV, while the discharge modules 151 in the N third test modules 17 do not need to receive the second drive signal. That is to say, as... Figure 6 As shown, the control terminal of the charging module 141 is connected to the first drive signal PDRV, and the control terminal of the discharge module 151 in the second test module 15 and the third test module 17 is connected to the second drive signal NDRV. However, only one of the multiple discharge modules 151 corresponding to the second test module 15 and the third test module 17 can receive the valid second drive signal NDRV, and the test module that can receive the valid second drive signal is the Topdie in the current scenario. Specifically, under mass production test conditions, the topmost memory chip is generally defined as the Topdie. Under analysis test conditions, the topmost memory chip is generally defined as the Topdie first. If the silicon vias corresponding to the topmost memory chip are unqualified, a slicing test is required. At this time, the topmost memory chip in the stacked structure containing the bottom logic chips obtained after slicing is defined as the Topdie. The Topdie is the aforementioned intermediate chip. The control terminal of the charging module 141 is the gate of the third transistor T3, and the control terminal of the discharge module 151 is the gate of the fourth transistor T4.

[0129] It should also be noted that, such as Figure 6 As shown, when the power-on signal P_on is in an invalid state, the inverted signal of the power-on signal... This causes the first transistor T1 and all the second transistors T2 to conduct. In the first test module 14, the first inverter 1422 inverts the second value to the first value and provides it to the clock input terminal CLK of the first flip-flop 1421. In the second test module 15 and the third test module 17, the second inverter 1522 inverts the second value to the first value and provides it to the clock input terminal CLK of the second flip-flop 1521. After the test starts, the power-on signal P_on is in an active state, and the first transistor T1 and all the second transistors T2 are not conducting. At this time, the first drive signal PDRV is first provided to the third transistor T3, causing the third transistor T3 to conduct and charge the through-silicon via module 13. At this time, each sub-through-silicon via is charged to the first level. At the same time, the signal received by the clock receiver terminal CLK of the first flip-flop 1421 and all the second flip-flops 1521 becomes the second value. Then, instead of providing the first drive signal PDRV to the third transistor T3, a second drive signal NDRV is provided to the fourth transistor T4 in the second test module 15, causing the fourth transistor T4 to conduct and discharge the through-silicon via module 13. At this time, each sub-through-silicon via is discharged to the second level. Simultaneously, the signal received by the clock receiver CLK of the first flip-flop 1421 and each second flip-flop 1521 changes from the second value to the first value, forming a rising edge. Under the triggering of the rising edge, the first flip-flop 1421 and each second flip-flop 1521 sample the high-level signal (logic 1) received at the input terminal D, thereby outputting a test result of the first value (logic 1) at the output terminal Q. At the same time, the second flip-flop 152 in the third test module 17 is also triggered and outputs a third test result of the first value.

[0130] During the test, if any of the sub-through silicon vias has a bidirectional transmission problem, then the sub-through silicon via (TSV1) connected to the first test module 14 and the sub-through silicon via (TSV N+1) connected to the second test module 15 will not experience voltage changes, and the first trigger 1421 and each of the second triggers 1521 will not be triggered, resulting in the first test result, the second result result and N third test results all being the second value.

[0131] If the i-th sub-via exhibits an anomaly in the transmission from the first end to the second end (the first end being the end closer to the bottom chip, and the second end being the end closer to the top chip), or an anomaly in the transmission of a high level, then only the 1st to (i-1th)-th sub-vias will experience voltage changes, triggering their corresponding flip-flops. This causes the first test module 14 and the 1st to (i-1th)th third test modules 17 to output the first value. However, the flip-flops corresponding to the i-th to (N+1th)-th sub-vias cannot be triggered, and the i-th to (N+1th)-th third test modules 17 and the second test module 15 will output the second value. Assuming N=7, the first test result, the 7 third test results, and the second test result are respectively: 1-1111000-0. In this case, the 4th third test result is normal, but the results from the 5th third test result onwards are abnormal, indicating that the 5th sub-via cannot transmit the first level to the subsequent sub-vias, indicating an anomaly in the transmission from the first end to the second end (or the transmission of a high level).

[0132] If the i-th sub-via exhibits an anomaly in the transmission from the second end to the first end, or an anomaly in the transmission of a low level, then only the i-th to N+1-th sub-vias will experience voltage changes, triggering their corresponding flip-flops. This causes the i-th to N-th third test modules 17 and the second test module 15 to output the first value. However, the flip-flops corresponding to the first to i-1-th sub-vias cannot be triggered, so the first test module 14 and the first to i-1-th third test modules 17 output the second value. Assuming N=7, the first test result, the 7 third test results, and the second test result are 0-0001111-1 respectively. In this case, the 4th to 7th third test results and the second test result are normal, but the first test result and the 1st to 3rd third test results are abnormal. This indicates that the 4th sub-via cannot transmit the second level to the sub-vias preceding it, indicating an anomaly in the transmission from the second end to the first end (or transmission of a low level).

[0133] In other words, the test circuit is also used to determine that the (j+1)th sub-through-silicon via is abnormal if the first test result output by the first test module 14 is the second value, and the third test result output by the third test module 17 corresponding to the 1st to jth intermediate chips is the second value, the third test result output by the third test module 17 corresponding to the (j+1)th to Nth intermediate chips is the first value, and the second test result output by the second test module 15 is the first value;

[0134] The test circuit is further configured to determine that the (j+1)th sub-through-silicon via is abnormal if the first test result output by the first test module 14 is a first value, and the third test result output by the third test module 17 corresponding to the 1st to jth intermediate chips is a first value, the third test result output by the third test module 17 in the (j+1)th to Nth intermediate chips is a second value, and the second test result output by the second test module 15 is a second value; where j is an integer greater than 0 and less than or equal to N.

[0135] Thus, this embodiment of the present disclosure can not only test whether there is any abnormality in the overall through-silicon via module, but also determine the abnormal sub-through-silicon vias by combining the first test result, the second test result and the third test result, thereby further improving the accuracy and reliability of the test results.

[0136] It should also be noted that when an abnormality is found in the through-silicon via (TSV) module, it may be that one or more TSVs are abnormal. In order to identify the specific one or more TSVs that are abnormal, in some embodiments, the test circuit is also used to determine the Nth intermediate chip as the top chip when the test result indicates that the TSV module is abnormal. The remaining TSVs except the N+1th TSV are tested according to the first test module and the Nth intermediate chip to determine the test result. If the test result indicates that the TSV module is abnormal, the N-1th intermediate chip is determined as the top chip, until the test result is a pass.

[0137] It should be noted that if the test results indicate an anomaly in the through-silicon via (TSV) module, especially when both the first and second test results are the second value, and it is still impossible to determine which sub-TSV is abnormal, then the intermediate chip adjacent to the original top-layer chip (the Nth intermediate chip) is identified as the top-layer chip, and the test is performed in the aforementioned manner. If the test results show that the TSV module is not abnormal, then the abnormality is in the (N+1)th sub-TSV module. If the test results indicate that the TSV module is still abnormal, the (N-1)th intermediate chip is identified as the top-layer chip and the test is performed until the abnormal sub-TSV is identified.

[0138] Based on this approach, the embodiments of this disclosure can not only test whether there are any anomalies in the through-silicon via (TSV) modules between the top-layer chip and the bottom-layer chip, but also determine whether there are any anomalies in the TSV modules between any intermediate chip and the bottom-layer chip. In other words, when testing the TSV modules as a whole, only the NDRV of the Top Die is enabled, but slicing tests can also be performed, in which case the NDRV of the top-layer chip in the sliced ​​structure is enabled.

[0139] Furthermore, embodiments of this disclosure can also save the test results corresponding to each test module. Therefore, in some embodiments, the test circuit further includes N+2 register modules, wherein:

[0140] In the underlying chip, the register module is connected to the output of the first flip-flop to save the first test result;

[0141] In the intermediate chip, the register module is connected to the output of the second flip-flop to store the third test result;

[0142] In the top-level chip, the register module is connected to the output of the second flip-flop to store the second test result.

[0143] It should be noted that, as Figure 6 As shown, the register module connected to the first flip-flop 1421 is denoted as the first register module 143, the register module connected to the second flip-flop 1521 in the second test module 15 is denoted as the second register module 153, and the register module connected to the second flip-flop 1521 in the third test module 17 is denoted as the third register module 171. In this way, each register module can store the test results output by the flip-flop connected to it; specifically, the register module can be a register.

[0144] In this way, there is no need for an additional TSV to resend the test results to the corresponding chip. Instead, the test results are directly stored in the corresponding chip. There is no need to set up additional transmission circuits, which reduces circuit complexity. At the same time, each test module includes an independent register module, so they will not interfere with each other. They also do not need to share additional TSVs, so there will be no problem of the shared TSV failing and the entire test circuit failing to operate normally.

[0145] Furthermore, in this embodiment, since the through-silicon via (TSV) module is charged using a PMOS transistor in the first test module and discharged using an NMOS transistor in the second and third test modules, the charging module in the first test module can also be called a P-pulse generation module, and the remaining parts of the first test module are called a pass / fail recorder module. Similarly, the discharging module in the second and third test modules can also be called an N-pulse generation module, and the remaining parts are called a pass / fail recorder module. In mass production, each memory chip has the same chip structure. In this embodiment, except for the Base Die which uses the first test module containing P-pulse generation, all memory chips (also called Core Dies) use the second test module containing N-pulse generation. During testing, only the discharge module of the Top Die receives the second drive signal NDRV and is enabled. If the TSV module is turned on, all flip-flops on the corresponding lines will output the first value (Pass Flag). Simultaneously, this embodiment can utilize additional tests to verify whether the first / second / third test results are recorded.

[0146] Furthermore, in the embodiments of this disclosure, the circuit structures of the first test module 14 and the second test module 15 (third test module 17) can also be interchanged, and the detection of the through silicon via module 13 can still be achieved. The principle is as described above and will not be repeated here.

[0147] In short, during testing, the embodiments of this disclosure first locate the Top Die and Base Die, and connect test points to both sides of the Top Die and Base Die respectively to test the DC performance of the through-silicon via (TSV) module. Only the N pulse generator and P pulse generator at the test points will generate pulses. The Pass / Fail Flags of the test results (where Pass Flag indicates the first value of a normal test result, and Fail Flag indicates the second value of an abnormal test result) are automatically recorded to each chip by the Pass / Fail Recorder. Simultaneously, the Pass / Fail Recorder for each layer of chips is activated during the testing process.

[0148] This disclosure provides a test circuit applied to a chip stack structure, which includes multiple chips connected by through-silicon via (TSV) modules. The test circuit includes a first test module and a second test module, with the two ends of the TSV modules connected to the first and second test modules respectively. The first test module is located within the bottom chip of the chip stack, and the second test module is located within the top chip of the chip stack. The test circuit is used to test the TSV modules between the bottom and top chips using the first and second test modules, and to determine the test results. The test results indicate whether the TSV modules are abnormal. Thus, by placing the first test module in the bottom chip of the chip stack structure and the second test module in the top chip of the chip stack structure, and connecting the first and second test modules to the two ends of the TSV modules penetrating the chip stack structure, this disclosure allows testing of the entire TSV module using only the first test module in the bottom chip and the second test module in the top chip, thus determining whether the TSV modules are abnormal. This simplifies the testing method while achieving accurate measurement of the TSV modules, enabling rapid detection of abnormal TSVs in the chip stack structure. In addition, there is no need to use an additional Robust TSV to transmit the Pass / Fail Flag, which avoids the problem that the entire test circuit cannot function properly when the additional TSV fails, and also saves test repair circuitry.

[0149] Furthermore, when the through-silicon via (TSV) module malfunctions, repair is required to ensure the normal operation of the memory. Based on this, another embodiment of this disclosure also provides a test structure applied to the chip stack structure 10, see [link to relevant documentation]. Figure 7 It shows a schematic diagram of the composition structure of another chip stacking structure 10 provided in the embodiments of this disclosure, such as Figure 7 As shown, the chip stack structure 10 includes multiple chips, which are connected through a through-silicon via (TSV) module 13 and at least one redundant TSV module 13'. The test structure includes the test circuit 101 described in any of the preceding embodiments, wherein:

[0150] The test structure is used to select a redundant through-silicon via module 13' to replace the through-silicon via module 13 if the test circuit 101 detects an abnormality in the through-silicon via module 13.

[0151] It should be noted that, as Figure 7 As shown, in the chip stacking structure 10, in addition to the through-silicon via (TSV) modules 13 connecting multiple chips, at least one redundant TSV module 13' is also included. Figure 6The diagram shows one (the specific number is not limited) connecting multiple chips through each other. In this case, if there is a problem with the through-silicon via module 13, then a redundant through-silicon via module 13' is selected as the new through-silicon via module to operate.

[0152] In some embodiments, the test structure further includes at least one redundant test circuit 101', and the redundant test circuit 101' has the same structure and function as the test circuit 101; wherein, the redundant test circuit 101' is used to test whether there is an abnormality in the corresponding redundant through-silicon via module 13'.

[0153] It should be noted that, as Figure 7 As shown, the redundant silicon via module 13' is connected to the redundant test circuit 101'. The composition and structure of the redundant test circuit 101' are exactly the same as those of the aforementioned test circuit 101, and the working method is also exactly the same, so it will not be described again here.

[0154] See Figure 8 and Figure 9 , Figure 8 This diagram illustrates the structural composition of a test structure provided in an embodiment of the present disclosure. Figure 9 A schematic diagram of the circuit structure of a test structure provided in an embodiment of this disclosure is shown. Figure 9 In this diagram, the first power module, the second power module, and the third power module are all represented by VDD, and the first grounding module, the second grounding module, and the third grounding module are all represented by VSS. Figure 8 and Figure 9 The diagram illustrates a test circuit and a redundant test circuit. Correspondingly, sub-vias TSV1, TSV2, ..., TSV N+1 form a via module 13, and redundant sub-vias TSV1', TSV2', ..., TSV N+1' form a redundant via module 13'. A first test module 14, a second test module 15, and a third test module 17, connected to each redundant sub-via, form a redundant test module. For... Figure 8 and Figure 9 The working principle of each test module can be referred to the above. Figure 3 and Figure 6 The description is for reference only, and will not be elaborated further here.

[0155] In addition, such as Figure 9As shown in the diagram, several switch modules 18 and data terminals 19 are also illustrated. Taking the test circuit as an example, in the first test module 14, switch module 18 is connected to the output terminal of the first flip-flop 1421, and switch module 18 is also connected to the through-silicon via (TSV) module and data terminal 19. In the second test module 15 and the third test module 17, switch module 18 is connected to the output terminal of the second flip-flop 1521, and switch module 18 is also connected to the TSV module and data terminal 19. Thus, when both the first flip-flop 1421 and the second flip-flop 1521 output a first value, their respective connected switch modules 18 can be activated, thereby enabling data transmission from one data terminal to another. Specifically, switch module 18 can be a transmission gate, which can be composed of an NMOS transistor and a PMOS transistor. Regarding the aforementioned... Figure 3 and Figure 5 The test circuit shown can also be augmented with a switch module 18 and a data terminal 19 to achieve data transmission functionality. Meanwhile, Figure 8 The circuit structure shown can also include a register module for storing test results, only in... Figure 8 Not shown in the image.

[0156] It should also be noted that, Figures 7 to 9 Only the 1:1 repair scenario is shown. Other repair schemes (1:3, 2:2, 8:2, etc.) can also be implemented in the same way. Here, 1:1 means that in the DRAM, one through-silicon via (TSV) module is used for bidirectional data transmission, with one redundant TSV module (dummy) as a backup. 1:3 means that three redundant TSV modules are used as backups. 2:2 means that two TSV modules are used for unidirectional data transmission, i.e., there are two data paths. In this case, two TSV modules are needed as a group for normal use. Similarly, during repair, two redundant TSV modules are needed as a group for replacement. 2:2 means that one set of redundant redundant TSV modules is used as a replacement. 8:2 means that for every four groups of TSV modules, there is one set of redundant redundant TSV modules as a replacement. Furthermore, in practice, the methods listed here are not limited to those shown here, and will not be elaborated further.

[0157] In summary, the test structure provided in this disclosure can be applied to the self-testing and repair of multi-point connected TSVs in multi-stacked DRAMs. In this case, it is not necessary to use an additional Robust TSV to transmit the Pass / Fail Flag, and the test and repair circuit is saved.

[0158] In another embodiment of this disclosure, see Figure 10 This illustrates a flowchart of a testing method provided in an embodiment of this disclosure. Figure 10 As shown, the method may include:

[0159] S1001: The through-silicon via (TSV) module between the bottom-layer chip and the top-layer chip is tested by the first test module and the second test module, and the test results are determined; wherein, the test results are used to indicate whether there is any abnormality in the TSV module.

[0160] In some embodiments, determining the test result may include:

[0161] The first test result is determined by the first test module based on the voltage change at one end of the through-silicon via module connected to the first test module.

[0162] The second test result is determined by the voltage change at the other end of the through-silicon via module connected to the second test module.

[0163] The voltage change across the through-silicon via module is provided by the first test module and the second test module, and the first test result and the second test result constitute the test result.

[0164] In some embodiments, the method may further include: determining whether there are any abnormalities in the N+1 sub-through silicon vias based on the first test result output by the first test module, the N third test results output by the N third test modules, and the second test result output by the second test module.

[0165] In some embodiments, the method may further include: when the test result indicates that the through-silicon via module is abnormal, determining the Nth intermediate chip as the top chip, testing the remaining sub-through-silicon vias except for the N+1th sub-through-silicon via according to the first test module and the Nth intermediate chip, determining the test result, and if the test result indicates that the through-silicon via module is abnormal, determining the N-1th intermediate chip as the top chip, until the test result is a pass.

[0166] In some embodiments, determining the test result may include: if both the first test result and the second test result are first values, determining that the test result is that the through-silicon via module has no abnormality; and if at most one of the first test result and the second test result is a first value, determining that the test result is that the through-silicon via module has an abnormality.

[0167] In some embodiments, determining whether there are any abnormalities in the N+1 sub-through-silicon vias based on the first test result output by the first test module, the N third test results output by the N third test modules, and the second test result output by the second test module may include:

[0168] If the first test result output by the first test module is the second value, and the third test result output by the third test module corresponding to the 1st to jth intermediate chips is the second value, the third test result output by the third test module corresponding to the (j+1)th to Nth intermediate chips is the first value, and the second test result output by the second test module is the first value, then it is determined that the (j+1)th sub-through-silicon via is abnormal, or;

[0169] If the first test result output by the first test module is the first value, and the third test result output by the third test module corresponding to the 1st to jth intermediate chips is the first value, the third test result output by the third test module in the (j+1)th to Nth intermediate chips is the second value, and the second test result output by the second test module is the second value, then it is determined that the (j+1)th sub-through-silicon via is abnormal.

[0170] In some embodiments, the method may further include: if the test circuit detects an abnormality in the through-silicon via (TSV) module, selecting a redundant TSV module to replace the TSV module.

[0171] In some embodiments, the method may further include: testing whether the corresponding redundant through-silicon via (TSV) module is abnormal using a redundant test circuit.

[0172] It should be noted that the test method provided in this disclosure can be applied to the test circuit or test structure provided in the foregoing embodiments. For details not disclosed in this disclosure, please refer to the description of the foregoing embodiments for understanding.

[0173] The above description is merely an example embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure.

[0174] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0175] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0176] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0177] The features disclosed in the several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

[0178] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0179] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A test circuit, characterized in that, This is applied to a chip stacking structure, wherein the chip stacking structure includes multiple chips connected by through-silicon via (TSV) modules; the test circuit includes a first test module and a second test module, with the two ends of the TSV modules respectively connected to the first test module and the second test module, wherein the first test module is disposed within the bottom chip of the multiple chips, and the second test module is disposed within the top chip of the multiple chips, wherein: The test circuit is used to test the through-silicon via (TSV) module between the bottom chip and the top chip using the first test module and the second test module, and to determine the test result; wherein the test result is used to indicate whether there is an abnormality in the TSV module; The first test module is used to determine a first test result based on the voltage change at one end of the through-silicon via module connected to the first test module; The second test module is used to determine a second test result based on the voltage change at the other end of the through-silicon via module connected to the second test module; The voltage change across the through-silicon via module is provided by the first test module and the second test module, and the test results are composed of the first test results and the second test results. The first test module includes a charging module and a first trigger module, and the second test module includes a discharging module and a second trigger module; wherein: The charging module is used to charge the through-silicon via module to a first level after the first trigger module and the second trigger module receive a power-on signal; The discharge module is used to discharge the through-silicon via module to a second level after the charging module charges the through-silicon via module. The first trigger module is used to perform triggering processing based on the first level and the second level to obtain a first test result; The second trigger module is used to perform triggering processing based on the first level and the second level to obtain a second test result.

2. The test circuit according to claim 1, characterized in that, The plurality of chips further includes N intermediate chips, and the test circuit further includes N third test modules, with a corresponding relationship between the N third test modules and the N intermediate chips; the through-silicon via (TSV) module includes N+1 sub-TSVs, where N is an integer greater than 0; wherein: The bottom chip and the first intermediate chip are connected through the first sub-through silicon via; the first end of the first sub-through silicon via is connected to the first test module, and the second end of the first sub-through silicon via is connected to the third test module corresponding to the first intermediate chip; The i-th intermediate chip and the (i+1)-th intermediate chip are connected through the (i+1)-th sub-through silicon via, where i is an integer greater than 0 and less than N; the first end of the (i+1)-th sub-through silicon via is connected to the third test module corresponding to the i-th intermediate chip, and the second end of the (i+1)-th sub-through silicon via is connected to the third test module corresponding to the (i+1)-th intermediate chip. The Nth intermediate chip is connected to the top-level chip through the (N+1)th sub-through silicon via; the first end of the (N+1)th sub-through silicon via is connected to the third test module corresponding to the Nth intermediate chip, and the second end of the (N+1)th sub-through silicon via is connected to the second test module.

3. The test circuit according to claim 2, characterized in that, The second test module has the same structure as the third test module.

4. The test circuit according to claim 2, characterized in that, The test circuit is also used to determine whether there is any abnormality in the N+1 sub-through silicon vias based on the first test result output by the first test module, the N third test results output by the N third test modules, and the second test result output by the second test module.

5. The test circuit according to claim 2, characterized in that, The test circuit is further configured to, when the test result indicates that the through-silicon via module is abnormal, determine the Nth intermediate chip as the top-level chip, test the remaining sub-through-silicon vias except the N+1th sub-through-silicon via according to the first test module and the Nth intermediate chip, determine the test result, and if the test result indicates that the through-silicon via module is abnormal, determine the N-1th intermediate chip as the top-level chip, until the test result is a pass.

6. The test circuit according to claim 1, characterized in that: The first trigger module includes a first trigger and a first inverter. The clock input of the first trigger is connected to the output of the first inverter. The input of the first inverter is connected to the through-silicon via module and the charging module. The input of the first trigger is connected to the first power supply module. The output of the first trigger is used to output the first test result. The second trigger module includes a second trigger and a second inverter. The clock input of the second trigger is connected to the output of the second inverter. The input of the second inverter is connected to the through-silicon via module and the discharge module. The input of the second trigger is connected to the second power supply module. The output of the second trigger is used to output the second test result.

7. The test circuit according to claim 6, characterized in that: The first test module further includes a first transistor, the input terminal of the first inverter is connected to the first terminal of the first transistor, the second terminal of the first transistor is connected to the first ground module, and the gate of the first transistor is connected to the inverted signal of the power-on signal. The second test module also includes a second transistor, the input terminal of the second inverter is connected to the first terminal of the second transistor, the second terminal of the second transistor is connected to the second ground module, and the gate of the second transistor is connected to the inverted signal of the power-on signal.

8. The test circuit according to claim 7, characterized in that, The control terminal of the charging module is connected to the first drive signal, and the control terminal of the discharge module in the second test module is connected to the second drive signal.

9. The test circuit according to claim 6, characterized in that, The first trigger module further includes a third inverter, and the second trigger module further includes a fourth inverter, wherein: The input terminal of the third inverter is connected to the output terminal of the first inverter, and the output terminal of the third inverter is connected to the input terminal of the first inverter. The input terminal of the fourth inverter is connected to the output terminal of the second inverter, and the output terminal of the fourth inverter is connected to the input terminal of the second inverter.

10. The test circuit according to claim 6, characterized in that, The plurality of chips further includes N intermediate chips, and the test circuit further includes N third test modules, with a corresponding relationship between the N third test modules and the N intermediate chips; the through-silicon via (TSV) module includes N+1 sub-TSVs, where N is an integer greater than 0; wherein: The bottom chip and the first intermediate chip are connected through the first sub-through silicon via; the first end of the first sub-through silicon via is connected to the first test module, and the second end of the first sub-through silicon via is connected to the third test module corresponding to the first intermediate chip; The i-th intermediate chip and the (i+1)-th intermediate chip are connected through the (i+1)-th sub-through silicon via, where i is an integer greater than 0 and less than N; the first end of the (i+1)-th sub-through silicon via is connected to the third test module corresponding to the i-th intermediate chip, and the second end of the (i+1)-th sub-through silicon via is connected to the third test module corresponding to the (i+1)-th intermediate chip. The Nth intermediate chip is connected to the top-level chip through the (N+1)th sub-through silicon via; the first end of the (N+1)th sub-through silicon via is connected to the third test module corresponding to the Nth intermediate chip, and the second end of the (N+1)th sub-through silicon via is connected to the second test module.

11. The test circuit according to claim 10, characterized in that, The test circuit also includes N+2 register modules, wherein: In the underlying chip, the register module is connected to the output of the first trigger and is used to save the first test result; In the intermediate chip, the register module is connected to the output of the second flip-flop and is used to save the third test result; In the top-level chip, the register module is connected to the output of the second flip-flop and is used to save the second test result.

12. The test circuit according to claim 1, characterized in that: The test circuit is further configured to determine, when both the first test result and the second test result are first values, that the test result indicates that the through-silicon via module has no abnormality; The test circuit is further configured to determine that the test result indicates an abnormality in the through-silicon via module if at most one of the first test result and the second test result is a first value.

13. The test circuit according to claim 4, characterized in that: The test circuit is further configured to determine that the (j+1)th sub-silicon via is abnormal if the first test result output by the first test module is a second value, and the third test result output by the third test module corresponding to the 1st to jth intermediate chips is a second value, the third test result output by the third test module corresponding to the (j+1)th to Nth intermediate chips is a first value, and the second test result output by the second test module is a first value; The test circuit is further configured to determine that the (j+1)th sub-silicon via is abnormal if the first test result output by the first test module is a first value, the third test result output by the third test module corresponding to the 1st to jth intermediate chips is a first value, the third test result output by the third test module in the (j+1)th to Nth intermediate chips is a second value, and the second test result output by the second test module is a second value.

14. The test circuit according to any one of claims 1 to 12, characterized in that, The underlying chip among the plurality of chips is a logic chip, and the chips other than the underlying chip among the plurality of chips are memory chips.

15. A test structure applied to a chip stack structure, the chip stack structure comprising a plurality of chips, the plurality of chips being interconnected by through-silicon via (TSV) modules and at least one redundant TSV module, and the test structure comprising a test circuit as described in any one of claims 1 to 14, wherein: The test structure is used to select a redundant through-silicon via module to replace the through-silicon via module if the test circuit detects an abnormality in the through-silicon via module.

16. The test structure according to claim 15, characterized in that, The test structure also includes at least one redundant test circuit, which has the same structure and function as the test circuit; wherein, the redundant test circuit is used to test whether the corresponding redundant through-silicon via module is abnormal.

17. A test method applied to a test circuit as described in any one of claims 1 to 14, the method comprising: The test results are determined by jointly testing the through-silicon via (TSV) module between the bottom-layer chip and the top-layer chip using the first test module and the second test module; wherein the test results are used to indicate whether there is an abnormality in the TSV module.

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