A packaging structure and method for high-density optoelectronic co-packaging of a silicon photonics chip

Abstract

The present invention discloses a packaging structure and packaging method for high-density optoelectronic co-packaging of silicon photonic chips, including a silicon photonic chip, a fan-out structure substrate, and a transfer circuit module. The fan-out structure substrate serves as both a substrate and a fan-out structure. Through the high-density second electrical pin, internal circuit diagram, and third electrical pin at its bottom, the high-density first electrical pin of the silicon photonic chip is fanned out to the third electrical pin while fixing the silicon photonic chip. The pin is then electrically connected to the fourth electrical pin of the transfer circuit module by wire welding, thereby achieving electrical packaging and avoiding thermal mismatch problems during packaging and use. The I-shaped fan-out structure substrate and the groove areas on both sides of the fan-out structure substrate serve as avoidance spaces, facilitating the coupling packaging of the optical coupling ports on both sides of the silicon photonic chip with the external optical fiber array, meeting the packaging requirements of silicon photonic chips and similar optical chips with high-density coexistence of electrical pins and optical coupling ports.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip packaging, and in particular relates to a packaging structure and a packaging method for high-density optoelectronic co-packaging of silicon photonic chips. Background Art

[0002] With the continuous development of big data, artificial intelligence, telemedicine, the Internet of Things, e-commerce, and 5G communications, global data traffic is exploding. Driven by ultra-high data capacity, traditional electronic chip manufacturing processes are approaching 10nm, and CMOS processes are approaching their physical limits. The industry generally believes that silicon photonic chips, by organically combining mature microelectronics and optoelectronics technologies, can reduce chip size, lower costs and power consumption, and improve reliability, promising to become the high-speed information engine of "More Than Moore's Law."

[0003] Currently, silicon photonic chips with large-scale, high-density electrical pins, such as large-array silicon photonic switching chips, have thousands of electrical pins on their bare chip surfaces and hundreds of optical coupling ports such as gratings. For the packaging of such silicon photonic chips and similar optical chips with high density of electrical pins and optical coupling ports, their packaging structure needs to take into account both electrical and optical requirements. Packaging structures that only target high-density electrical pins, such as various advanced stacked packaging structures and various BGA packaging structures of current electrical chips, are not fully applicable. As shown in patent documents CN201310189098, patent document CN201310189144, and patent document CN202111349184, the most important external interface of their packaging structure, namely solder balls such as metal balls or copper core balls, needs to be made on the basis of plastic sealing of the bare chip. However, silicon photonic chips and similar optical chips must not be plastic sealed on the bare chip to avoid blocking the optical coupling port.

[0004] In addition, the high-density electrical pin packaging structure of this chip, with solder balls as the external interface, requires high thermal compatibility of the component materials on both sides of the solder balls. Otherwise, the large difference in deformation of the component materials on both sides under high-temperature welding conditions will greatly reduce the welding success rate and welding quality. In addition, under variable temperature conditions, there will be large stress in the package, and long-term strain accumulation will reduce the service life of the package. The plastic packaging material on the outside of the bare chip of the electronic chip package has a high degree of thermal compatibility with the circuit board material on the other side of the solder balls, which can circumvent this problem. However, silicon photonic chips and similar optical chips cannot be plastic-encapsulated. The thermal properties of substrate materials such as ceramics, silicon, and glass directly packaged with the bare chip differ significantly from those of the circuit board material. If the silicon photonic chip or its substrate is directly packaged with the circuit board using high-density solder balls, the thermal mismatch problem will be more serious. Therefore, the packaging of the silicon photonic chip or its substrate with the circuit board requires an interface form that is not sensitive to thermal mismatch. Summary of the Invention

[0005] In view of the above, the purpose of the present invention is to provide a packaging structure and packaging method for high-density optoelectronic co-packaging of silicon photonic chips. The packaging structure takes into account the packaging requirements of both high-density electrical packaging and high-density optical packaging, and reasonably selects the interface form between the substrate and the circuit board to avoid thermal mismatch problems during packaging and use. The packaging method is simple to operate and has high packaging quality.

[0006] To achieve the above-mentioned purpose of the invention, an embodiment provides a silicon photonic chip high-density optoelectronic co-package structure comprising a silicon photonic chip, a fan-out structure substrate, and a switching circuit module.

[0007] The silicon photonic chip has a high-density first electrical pin arranged in the middle, and also has high-density optical coupling ports arranged on both side edges;

[0008] The fan-out structure substrate is I-shaped and consists of two wing plates and a web. The web surface is provided with a second electrical pin adapted to be electrically connected to the first electrical pin of the silicon photonic chip. The edges of the two wing plates are provided with third electrical pins with a large spacing. The two wing plates and the web form groove areas on both sides.

[0009] The switching circuit module is provided with a fourth electrical pin adapted to be electrically connected to the third electrical pins of the two wing plates;

[0010] After the first electrical pin of the silicon photonic chip is electrically connected to the second electrical pin of the fan-out structure substrate, it is fanned out to the third electrical pin through the internal circuit diagram of the fan-out structure substrate. The third electrical pin is then electrically connected to the fourth electrical pin of the adapter circuit module to achieve electrical packaging. The groove areas on both sides of the fan-out structure substrate serve as avoidance space to facilitate the coupling packaging of the optical coupling ports on both sides of the silicon photonic chip with the external optical fiber array.

[0011] Preferably, the fan-out structure substrate is made of ceramic material or silicon material that is thermally compatible with the silicon photonic chip.

[0012] Preferably, when the fan-out structure substrate is made of ceramic material, the fan-out structure substrate is a thick-film hybrid multi-layer LTCC ceramic substrate.

[0013] Preferably, when the fan-out structure substrate is made of silicon material, the fan-out structure substrate is a silicon substrate with single-layer or multi-layer circuit wiring.

[0014] Preferably, a hole blank area is provided in the middle of the switching circuit module for accommodating a silicon photonic chip or an external optical fiber array packaged on a fan-out structure substrate.

[0015] Preferably, the third electrical pin of the fan-out structure substrate is electrically connected to the fourth electrical pin of the switching circuit module by adopting a wire welding method that is insensitive to material thermal mismatch.

[0016] Preferably, the switching circuit module has a circuit switching function and / or a drive control function.

[0017] To achieve the above-mentioned purpose of the invention, an embodiment provides a packaging method for high-density optoelectronic co-packaging of a silicon photonic chip, which implements the packaging of the above-mentioned packaging structure. The packaging method includes the following steps:

[0018] Step 1: Create micro solder bumps on the first electrical pins of the silicon photonic chip, align and bond the cured micro solder bumps to the second high-density electrical pins of the fan-out structure substrate using conductive silver glue, and cure the conductive silver glue at high temperature to achieve electrical connection and fixation between the silicon photonic chip and the fan-out structure substrate.

[0019] Step 2: Mount the fan-out structure substrate with the silicon photonic chip fixed thereon in step 1 onto the transfer circuit module;

[0020] Step 3: electrically connecting the third electrical pin of the fan-out structure substrate and the fourth electrical pin of the adapter board circuit module by wire welding;

[0021] Step 4: Couple and package the high-density optical coupling port of the silicon photonic chip with the external optical fiber array by avoiding space.

[0022] Preferably, laser ball implantation technology is used to make micro solder bumps on the first electrical pin of the silicon photonic chip to adapt to more types of solders with a wider ball diameter range and the process processing of bare chips after dicing.

[0023] Preferably, the micro solder bumps are tin-silver-copper alloy solder balls.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] The fan-out structure substrate serves as both a substrate and a fan-out structure. Through its high-density second electrical pins, internal circuitry, and third electrical pins, the high-density first electrical pins of the silicon photonics chip are fanned out to the third electrical pins while securing the silicon photonics chip. These pins are then electrically connected to the fourth electrical pins of the adapter circuit module using wire bonding, achieving electrical packaging and avoiding thermal mismatch issues during packaging and use. The I-shaped fan-out structure substrate features recessed areas on both sides that serve as escape spaces, facilitating the coupling and packaging of the optical coupling ports on both sides of the silicon photonics chip with an external fiber array. This meets the packaging requirements of silicon photonics chips and similar optical chips with high densities of electrical pins and optical coupling ports. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0027] Figure 1 and Figure 2 1 is a schematic diagram of the top and bottom of a packaging structure provided by an embodiment;

[0028] Figure 3 yes Figure 1 A schematic cross-sectional view of the package structure shown;

[0029] Figure 4 and Figure 5 1 is a schematic diagram of the top and bottom of another packaging structure provided by an embodiment;

[0030] Figure 6 yes Figure 4 Schematic cross-sectional view of the package structure shown. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and do not limit the scope of protection of the present invention.

[0032] In response to the packaging requirements of silicon photonic chips and similar optical chips with high-density coexistence of electrical pins and optical coupling ports, an embodiment of the present invention provides a packaging structure and packaging method for high-density optoelectronic co-packaging of silicon photonic chips. The packaging structure and packaging method are described in detail below in combination with two specific embodiments.

[0033] Example 1

[0034] Figure 1-Figure 3 The top schematic diagram, bottom schematic diagram and cross-sectional schematic diagram of the packaging structure of the silicon photonic chip high-density optoelectronic co-packaging provided in Example 1 are shown. Figure 1-3 As shown, the packaging structure provided in Example 1 includes a silicon photonic chip 1, a fan-out structure substrate 2, and a switching circuit module 6, wherein the silicon photonic chip 1 has a high-density first electrical pin 103 and high-density optical coupling ports 101 and 102, wherein the first electrical pin 103 is concentrated in the middle of the surface of the silicon photonic chip 1, and the high-density optical coupling ports 101 and 102 are concentrated on the edges of both sides of the silicon photonic chip 1.

[0035] The fan-out structure substrate 2 serves as both a connection substrate for the silicon photonic chip 1 and a fan-out structure for its electrical signals. It is an I-shaped structure consisting of two wings and a web. Specifically, it utilizes a thick-film hybrid multilayer LTCC ceramic substrate. The web's bottom surface is provided with high-density second electrical pins 201, which are adapted to electrically connect to the first electrical pins 103 of the silicon photonic chip 1. The top edge surfaces of the wings are provided with single or multiple layers of widely spaced third electrical pins 202, corresponding to the adapter circuit module 6. The inner layer of the fan-out structure substrate 2 is composed of stacked circuit wiring layers fabricated using a thick-film process. Through-holes electrically connect the stacked circuits. This allows the high-density second electrical pins 201 on the web's bottom surface to be routed to a more spacious electrical pin arrangement through the stacked circuits and through-holes in the fan-out structure substrate 2's inner layers, thereby achieving electrical interconnection with the widely spaced third electrical pins 202 on the top surfaces of the wings. Both the second and third electrical pins 201, 202, are fabricated using a thin-film process. The two wing plates and the web plate form two side groove areas 203 and 204 .

[0036] The transfer circuit module 6 has a single or multiple layers of large-pitch fourth electrical pins 601 corresponding to the fan-out structure substrate 2. A blank area 602 is left in the center of the transfer circuit module 6 for the placement of the silicon photonic chip 1. Depending on actual needs, the transfer circuit module 6 can primarily function as a circuit switch or have complex drive control capabilities.

[0037] In the packaging structure, the first electrical pin 103 of the silicon photonic chip 1 is electrically connected to the second electrical pin 201 of the fan-out structure substrate 2, and then fans out to the third electrical pin 202 through the internal circuit diagram of the fan-out structure substrate 2. The third electrical pin 202 is then connected to the fourth electrical pin 601 of the switching circuit module 6 to achieve electrical packaging. The groove areas 203 and 204 on both sides of the fan-out structure substrate 2 serve as avoidance spaces to facilitate the coupling packaging of the optical coupling ports 101 and 102 on both sides of the silicon photonic chip 1 with the external optical fiber array, thereby completing the co-packaging of the first electrical pin 103 and high-density optical coupling ports 101 and 102 of the silicon photonic chip 1.

[0038] Example 1 also provides a Figure 1-3 The packaging method for high-density optoelectronic co-packaging of silicon photonic chips shown includes the following steps:

[0039] First, a tin-silver-copper alloy solder bump 3 is fabricated on the first electrical pin 103 of the silicon photonic chip 1 using laser ball implantation technology. After the cured micro solder bump 3 is dipped in an appropriate amount of conductive silver glue 4, the first electrical pin 103 of the silicon photonic chip 1 and the second electrical pin 201 of the fan-out structure substrate 2 are aligned and bonded. The conductive silver glue between the two is cured at high temperature to achieve electrical connection and fixation between the silicon photonic chip 1 and the fan-out structure substrate 2.

[0040] The assembled fan-out structure substrate 2 is then attached to the adapter circuit module 6 using ordinary electronic glue. The bottom surfaces of the two wings of the fan-out structure substrate 2 are bonded to the adapter circuit module 6, and the web containing the silicon photonic chip 1 is embedded in the blank area 602 of the hole in the adapter circuit module 6. Leads 5 are used to electrically connect the large-pitch third electrical pins 202 of the fan-out structure substrate 2 to the large-pitch fourth electrical pins 601 of the adapter circuit module 6. This wire-welded packaging method effectively avoids packaging issues caused by thermal mismatch between the fan-out structure substrate 2 and the adapter circuit module 6. The external drive control circuit ultimately achieves electrical control of the high-density electrical pins 103 of the silicon photonic chip 1 through the electrical path of the adapter circuit module 6, leads 5, fan-out structure substrate 2, and micro solder bumps 3.

[0041] Finally, the high-density optical coupling ports 101 and 102 of the silicon photonic chip 1 are coupled and packaged with the external large-scale optical fiber array FA.

[0042] Example 2

[0043] Figure 4-Figure 6 The top schematic diagram, bottom schematic diagram and cross-sectional schematic diagram of the packaging structure of the silicon photonic chip high-density optoelectronic co-packaging provided in Example 1 are shown. Figure 4-6 As shown, the packaging structure provided in Example 2 includes a silicon photonic chip 1, a fan-out structure substrate 2, and a switching circuit module 6, wherein the silicon photonic chip 1 has a high-density first electrical pin 103 and high-density optical coupling ports 101 and 102, wherein the first electrical pin 103 is concentrated in the middle of the surface of the silicon photonic chip 1, and the high-density optical coupling ports 101 and 102 are concentrated on the edges of both sides of the silicon photonic chip 1.

[0044] The fan-out structure substrate 2 also serves as both a connection substrate for the silicon photonic chip 1 and a fan-out structure for the silicon photonic chip 1's electrical signals. It is an I-shaped structure consisting of two wings and a web, specifically employing a single-layer or multi-layer silicon substrate for circuit wiring. The web's top surface is provided with high-density second electrical pins 201, which are adapted to electrically connect to the first electrical pins 103 of the silicon photonic chip 1. The top edge surfaces of the two wings are provided with single-layer or multi-layer, large-pitch third electrical pins 202, corresponding to the transfer circuit module 6. In other words, the high-density second electrical pins 201 and the single-layer or multi-layer, large-pitch third electrical pins 202 are all located on the same surface of the fan-out structure substrate 2. A single-layer or multi-layer circuit pattern is fabricated on the fan-out structure substrate 2 using a CMOS process to arrange the high-density second electrical pins 201 of the fan-out structure substrate 2 into a more spacious electrical pin arrangement, thereby achieving electrical interconnection with the large-pitch third electrical pins 202 located on the bottom of the fan-out structure substrate 2. The second electrical pins 201 and the third electrical pins 202 are also fabricated using a CMOS process. The two wing plates and the web plate also form groove areas 203 and 204 on both sides.

[0045] The transfer circuit module 6 has a single or multiple layer of widely spaced fourth electrical pins 601 corresponding to the fan-out structure substrate 2. A blank area 602 with holes is left in the middle of the transfer circuit module 6 to accommodate the external optical fiber array. Depending on actual needs, the transfer circuit module 6 can primarily function as a circuit switch or have complex drive control capabilities.

[0046] In the packaging structure, the first electrical pin 103 of the silicon photonic chip 1 is electrically connected to the second electrical pin 201 of the fan-out structure substrate 2, and then fans out to the third electrical pin 202 through the internal circuit diagram of the fan-out structure substrate 2. The third electrical pin 202 is then connected to the fourth electrical pin 601 of the switching circuit module 6 to achieve electrical packaging. The groove areas 203 and 204 on both sides of the fan-out structure substrate 2 serve as avoidance spaces to facilitate the coupling packaging of the optical coupling ports 101 and 102 on both sides of the silicon photonic chip 1 with the external optical fiber array, thereby completing the co-packaging of the first electrical pin 103 and high-density optical coupling ports 101 and 102 of the silicon photonic chip 1.

[0047] Example 2 also provides a Figure 4-6 The packaging method for high-density optoelectronic co-packaging of silicon photonic chips shown includes the following steps:

[0048] First, laser ball implantation is used to create high-temperature micro solder bumps 3 made of SAC305 or other materials on the first electrical pin 103 of the silicon photonic chip 1. After the solidified micro solder bumps 3 are dipped in an appropriate amount of conductive silver glue 4, the first electrical pin 103 of the silicon photonic chip 1 and the second electrical pin 201 of the fan-out structure substrate 2 are aligned and bonded. The conductive silver glue between the two is cured at high temperature to achieve electrical connection and fixation between the silicon photonic chip 1 and the fan-out structure substrate 2.

[0049] The assembled fan-out structure substrate 2 is then attached to the adapter circuit module 6 using standard electronic glue. The bottom surfaces of the two wings of the fan-out structure substrate 2 are now bonded to the adapter circuit module 6. Wire leads 5 are used to electrically connect the widely spaced third electrical pins 202 of the fan-out structure substrate 2 to the widely spaced fourth electrical pins 601 of the adapter circuit module 6. This wire-welded packaging method effectively mitigates packaging issues caused by thermal mismatch between the fan-out structure substrate 2 and the adapter circuit module 6. The external drive control circuit ultimately electrically controls the high-density electrical pins 103 of the silicon photonic chip 1 through the electrical pathways connecting the adapter circuit module 6, wire leads 5, the fan-out structure substrate 2, and the micro-solder bumps 3.

[0050] Finally, the external optical fiber array FA is embedded in the hole blank area 602 of the switching circuit module 6 to perform coupling packaging between the high-density optical coupling ports 101 and 102 of the silicon photonic chip 1 and the large-scale external optical fiber array FA.

[0051] In the above two embodiments, the high density in the high-density first electrical pins 103 and the high-density second electrical pins 201 is understood to mean that the pin density of the electrical pins is very high, reaching more than 1000 electrical pins within the area of a single silicon photonic chip. The large pitch in the large-pitch third electrical pins 202 and the large-pitch fourth electrical pins 601 is understood to mean that the arrangement pitch is larger than the arrangement pitch of the first electrical pins 103 and the second electrical pins 201, reaching a pitch greater than 80μm.

[0052] The specific implementation methods described above provide a detailed description of the technical solutions and beneficial effects of the present invention. It should be understood that the above is only the most preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, supplements and equivalent substitutions made within the scope of the principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A high-density optoelectronic co-packaging structure for silicon photonic chips, characterized in that: Including silicon photonic chips, fan-out structure substrates and switching circuit modules, The silicon photonic chip has a high-density first electrical pin arranged in the middle, and also has high-density optical coupling ports arranged on both side edges; The fan-out structure substrate is I-shaped and consists of two wing plates and a web. The web surface is provided with a second electrical pin adapted to be electrically connected to the first electrical pin of the silicon photonic chip. The edges of the two wing plates are provided with third electrical pins with a large spacing. The two wing plates and the web form groove areas on both sides. The switching circuit module is provided with a fourth electrical pin adapted to be electrically connected to the third electrical pins of the two wing plates; After the first electrical pin of the silicon photonic chip is electrically connected to the second electrical pin of the fan-out structure substrate, it is fanned out to the third electrical pin through the single-layer or multi-layer circuit diagram inside the fan-out structure substrate. The third electrical pin is then electrically connected to the fourth electrical pin of the adapter circuit module to achieve electrical packaging. The groove areas on both sides of the fan-out structure substrate serve as avoidance spaces to facilitate the coupling packaging of the optical coupling ports on both sides of the silicon photonic chip and the external optical fiber array. A hole blank area is provided in the middle of the switching circuit module for accommodating a silicon photonic chip or an external optical fiber array packaged on a fan-out structure substrate.

2. The high-density optoelectronic co-packaging structure of silicon photonic chips according to claim 1, characterized in that: The fan-out structure substrate is made of ceramic material or silicon material that is thermally compatible with the silicon photonic chip.

3. The high-density optoelectronic co-packaging structure of silicon photonic chips according to claim 2, characterized in that: When the fan-out structure substrate is made of ceramic material, the fan-out structure substrate is a thick-film hybrid multi-layer LTCC ceramic substrate.

4. The high-density optoelectronic co-packaging structure of silicon photonic chips according to claim 2, characterized in that: When the fan-out structure substrate is made of silicon material, the fan-out structure substrate is a silicon substrate with single-layer or multi-layer circuit wiring.

5. The high-density optoelectronic co-packaging structure of silicon photonic chips according to claim 1, characterized in that: The third electrical pin of the fan-out structure substrate is electrically connected to the fourth electrical pin of the switching circuit module by using a wire welding method that is insensitive to material thermal mismatch.

6. The high-density optoelectronic co-packaging structure of silicon photonic chips according to claim 1, characterized in that: The switching circuit module has a circuit switching function and / or a drive control function.

7. A packaging method for high-density optoelectronic co-packaging of silicon photonic chips, characterized in that: To achieve packaging of the packaging structure according to any one of claims 1 to 6, the packaging method comprises the following steps: Step 1: Create micro solder bumps on the first electrical pins of the silicon photonic chip, align and bond the cured micro solder bumps to the second high-density electrical pins of the fan-out structure substrate using conductive silver glue, and cure the conductive silver glue at high temperature to achieve electrical connection and fixation between the silicon photonic chip and the fan-out structure substrate. Step 2: Mount the fan-out structure substrate with the silicon photonic chip fixed thereon in step 1 onto the transfer circuit module; Step 3: electrically connecting the third electrical pin of the fan-out structure substrate and the fourth electrical pin of the adapter board circuit module by wire welding; Step 4: Couple and package the high-density optical coupling port of the silicon photonic chip with the external optical fiber array by avoiding space.

8. The packaging method for high-density optoelectronic co-packaging of silicon photonic chips according to claim 7, characterized in that: Laser ball implantation technology is used to make micro solder bumps on the first electrical pin of the silicon photonic chip.

9. The packaging method for high-density optoelectronic co-packaging of silicon photonic chips according to claim 7, characterized in that: The micro solder bumps are tin-silver-copper alloy solder balls.

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