A Chopper-Stabilized Buffer for Delta Sigma Modulators

Abstract

The present invention provides a chopper-stabilized buffer suitable for a Delta Sigma modulator, comprising a first chopper, a folded input stage, a second chopper, a common-gate amplifier stage, a third chopper and a Miller amplifier stage. The first chopper uses a periodic clock signal higher than the signal bandwidth of the Delta Sigma modulator as a chopping clock, the second chopper uses the output code stream of the Delta Sigma modulator as a chopping clock, and the third chopper uses the XOR of the chopping clock of the first chopper and the chopping clock of the second chopper as a chopping clock. The present invention can reduce the switching capacitor effect of the input chopper in the buffer and reduce the impact on the input DC voltage. At the same time, the flicker noise and mismatch in the circuit present an effect equivalent to chopping with the XOR of the output code stream of the Delta Sigma modulator with a lower frequency periodic clock at the output end of the buffer, and are located at the frequency of the chopping clock of the first chopper on the output spectrum of the Delta Sigma modulator, that is, located outside the signal bandwidth of the Delta Sigma modulator.

Description

Technical Field

[0001] The present invention relates to the technical field of buffers, and in particular to a chopper-stabilized buffer suitable for a Delta Sigma modulator. Background Art

[0002] Delta Sigma ADCs (analog-to-digital converters) using Delta Sigma modulators are widely used in metering and sensing due to their simple structure, low power consumption, and high accuracy. Delta Sigma modulators require a high-precision reference voltage. In multi-channel applications, if the Delta Sigma modulators of multiple channels are driven by the same buffer, crosstalk between channels is inevitable. To prevent flicker noise within the buffer from affecting the Delta Sigma modulator, chopper stabilization is often used. This involves using the exclusive OR of the Delta Sigma modulator's output bit stream with a periodic clock signal as the buffer's chopping clock signal. Generally, the frequency of the output bit stream of a Delta Sigma modulator is much higher than the frequency of the periodic clock signal, that is, the flicker noise and mismatch of the buffer are modulated on the exclusive OR of the output bit stream of the Delta Sigma modulator and a periodic clock signal. Since the output voltage of the buffer is used according to the output bit stream of the Delta Sigma modulator inside the Delta Sigma modulator, the flicker noise and mismatch of the buffer at the output end of the Delta Sigma modulator are modulated at the frequency of the periodic clock signal, and can be filtered out by subsequent digital filtering.

[0003] During the implementation of the present invention, the inventors discovered that the prior art presents at least the following problems: To reduce costs, a fully integrated bandgap reference circuit and on-chip low-pass filter are more attractive for providing a reference voltage for the buffer. To reduce the noise of the reference voltage itself, the narrower the bandwidth of the on-chip low-pass filter, the lower the noise in the output reference voltage. However, the on-chip capacitors in on-chip low-pass filters are typically not very large, and relatively large resistors are generally used to achieve a narrow low-pass bandwidth, resulting in a large output DC impedance of the low-pass filter. The buffer uses the exclusive OR of the output bit stream of a Delta Sigma modulator and a periodic clock signal as the chopper clock signal. The buffer's input terminals are the gates of the chopper and the input transistor pair. The gate capacitances of the chopper and the input transistor pair form a switched capacitor. The higher the chopper clock signal frequency, the lower the equivalent DC impedance of the switched capacitor. When this equivalent DC impedance decreases to a level that is not negligible compared to the output DC impedance of the low-pass filter, it can seriously affect the accuracy of the reference voltage output by the low-pass filter. Summary of the Invention

[0004] Purpose of the invention: In order to overcome at least one problem of the prior art, the present invention provides a chopper-stabilized buffer in which the input chopper clock is a relatively low frequency clock, while flicker noise and mismatch are still modulated at the output by the exclusive-OR of the output code stream of the Delta Sigma modulator and a periodic clock signal.

[0005] To achieve the above objectives, a first aspect discloses a chopper-stabilized buffer suitable for a Delta Sigma modulator, comprising a first chopper, a folded input stage, a second chopper, a common-gate amplifier stage, a third chopper, and a Miller amplifier stage:

[0006] The first chopper has an input signal and an output signal of the chopper-stabilized buffer as input, outputs a first signal, and the output is connected to the folding input stage;

[0007] The folding input stage has an output connected to the input of the second chopper, and is used to separate flicker noise and mismatch from the first signal to obtain a first error amplified signal in the form of current;

[0008] The second chopper has an output connected to the input of the common-gate amplifier stage, and uses the output code stream of the Delta Sigma modulator as a clock to chop and modulate the first error amplified signal to obtain a second signal in the form of current;

[0009] The common-gate amplifier stage has an output connected to the input of the third chopper, and is used to amplify the second signal and convert the second signal in current form into a second error amplified signal in voltage form;

[0010] The third chopper has an output connected to the input terminal of the Miller amplifier stage and the bias terminal of the common-gate amplifier stage, and uses the exclusive OR of the clock signals of the first chopper and the second chopper as a clock to chop and modulate the second error amplified signal, and output a third signal;

[0011] The Miller amplifier stage is used to amplify the third signal and output it.

[0012] Furthermore, the first chopper uses a periodic clock signal with a higher bandwidth than the Delta Sigma modulator signal as a chopping clock. The clock signal frequency of the first chopper is relatively low, which can reduce the switching capacitance effect and reduce the impact on the input DC voltage.

[0013] Furthermore, the folded input stage includes a current source tube, an input pair tube, a low-pass filter, a load pair tube and a coupling capacitor, wherein the current source tube is used to provide current to the input pair tube;

[0014] The input pair of transistors is used to receive the first signal and convert the first signal in voltage form into a first error amplified signal in current form;

[0015] The low-pass filter is used to obtain low-frequency flicker noise and mismatch, and send them to the gate of the load pair tube;

[0016] The load pair tube is used to receive low-frequency flicker noise and mismatch and isolate the first error amplified signal at the first chopping frequency;

[0017] The coupling capacitor exhibits a high-pass characteristic, isolating low-frequency flicker noise and mismatch, and only passes the first error amplification signal at the first chopping frequency.

[0018] The first chopper and folded input stage separate the flicker noise and signal of the folded input stage. The low-pass filter and load pair transistor present low impedance to low-frequency flicker noise and mismatch, and high impedance to signals at higher frequencies. The coupling capacitor presents high negative impedance to low-frequency flicker noise and mismatch, and low impedance to signals at higher frequencies. Thus, the flicker noise and mismatch of the folded input stage flow to the load transistor, while the signal passes through the coupling capacitor and the second chopper to the common-gate amplifier stage.

[0019] Furthermore, a fully integrated bandgap reference circuit and an on-chip low-pass filter provide a reference voltage as an input signal of the chopper-stabilized buffer.

[0020] Furthermore, the current source transistor of the folded input stage includes a first PMOS transistor M1, and the input pair transistors include a second PMOS transistor M2 and a third PMOS transistor M3.

[0021] A reference voltage Vref is connected to the positive input terminal of the first chopper, an output Vout of the chopper-stabilized buffer is connected to the negative input terminal of the first chopper, a positive output terminal of the first chopper is connected to the gate of the second PMOS transistor M2, and a negative output terminal of the first chopper is connected to the gate of the third PMOS transistor M3; a source of the second PMOS transistor M2 and a source of the third PMOS transistor M3 are connected together and to the drain of the first PMOS transistor M1, a source of the first PMOS transistor M1 is connected to the power supply voltage, and a gate of the first PMOS transistor M1 is connected to a first bias voltage VP1.

[0022] Furthermore, the load pair includes a fourth NMOS transistor M4 and a fifth NMOS transistor M5, the coupling capacitor includes a first capacitor C1 and a second capacitor C2, the drain VD1 of the second PMOS transistor M2 is connected to the positive input terminal of the low-pass filter and the drain of the fourth NMOS transistor M4, the drain VD2 of the third PMOS transistor M3 is connected to the negative input terminal of the low-pass filter and the drain of the fifth NMOS transistor M5; the positive output terminal of the low-pass filter is connected to the gate of the fourth NMOS transistor M4, and the negative output terminal of the low-pass filter is connected to the gate of the fifth NMOS transistor M5; the source of the fourth NMOS transistor M4 and the source of the fifth NMOS transistor M5 are both grounded; the drain VD1 of the second PMOS transistor M2 is connected to one end of the first capacitor C1, the other end of the first capacitor C1 is connected to the positive input terminal of the second chopper; the drain VD2 of the third PMOS transistor M3 is connected to one end of the second capacitor C2, the other end of the second capacitor C2 is connected to the negative input terminal of the second chopper.

[0023] Furthermore, the common-gate amplifier stage includes a sixth PMOS transistor M6, a seventh PMOS transistor M7, an eighth PMOS transistor M8, a ninth PMOS transistor M9, a tenth NMOS transistor M10, an eleventh NMOS transistor M11, a twelfth NMOS transistor M12, and a thirteenth NMOS transistor M13; the positive output end of the second chopper is connected to the source of the eleventh NMOS transistor M11 and the drain of the thirteenth NMOS transistor M13, and the negative output end of the second chopper is connected to the source of the tenth NMOS transistor M10 and the drain of the twelfth NMOS transistor M12; the gate of the tenth NMOS transistor M10 and the gate of the eleventh NMOS transistor M11 are both connected to the fourth bias voltage VN2, the drain of the tenth NMOS transistor M10 is connected to the drain of the eighth PMOS transistor M8 and the positive input end of the third chopper, and the eleventh NMOS transistor M11 is connected to the drain of the eighth PMOS transistor M8 and the positive input end of the third chopper. The drain of M11 is connected to the drain of the ninth PMOS transistor M9 and the negative input terminal of the third chopper; the gate of the eighth PMOS transistor M8 and the gate of the ninth PMOS transistor M9 are both connected to the second bias voltage VP2, the source of the eighth PMOS transistor M8 is connected to the drain of the sixth PMOS transistor M6, and the source of the ninth PMOS transistor M9 is connected to the drain of the seventh PMOS transistor M7; the gate of the sixth PMOS transistor M6 and the gate of the seventh PMOS transistor M7 are both connected to the positive output terminal of the third chopper, and the source of the sixth PMOS transistor M6 and the source of the seventh PMOS transistor M7 are both connected to the power supply voltage; the gate of the twelfth NMOS transistor M12 and the gate of the thirteenth NMOS transistor M13 are both connected to the third bias voltage VN1, and the source of the twelfth NMOS transistor M12 and the source of the thirteenth NMOS transistor M13 are both grounded.

[0024] The flicker noise and mismatch of the common-gate amplifier stage are modulated by the third chopper to a lower-frequency periodic clock and the output code stream of the Delta Sigma modulator is XORed. When the subsequent Delta Sigma modulator uses the output of the buffer as the reference voltage, the overall equivalent is to chopping the reference voltage with a lower-frequency periodic clock.

[0025] Furthermore, the Miller amplifier includes a fourteenth PMOS transistor M14, a fifteenth NMOS transistor M15, a third capacitor C3, and a first resistor R1. The negative output end of the third chopper is connected to the gate of the fourteenth PMOS transistor M14 and one end of the third capacitor C3. The other end of the third capacitor C3 is connected to one end of the first resistor R1. The other end of the first resistor R1 is connected to the drain of the fourteenth PMOS transistor M14 and the drain of the fifteenth NMOS transistor M15. The source of the fourteenth PMOS transistor M14 is connected to the power supply voltage, the gate of the fifteenth NMOS transistor M15 is connected to the first bias voltage VN1, and the source of the fifteenth NMOS transistor M15 is grounded.

[0026] A second aspect discloses a Delta Sigma modulator comprising at least one channel, each channel comprising the above-mentioned chopper-stabilized buffer, wherein the input signal of the chopper-stabilized buffer is a reference voltage provided by a fully integrated bandgap reference circuit and an on-chip low-pass filter.

[0027] Furthermore, each channel also includes a two-way selector, a loop filter and a comparator. The output voltage of the chopper-stabilized buffer is input to one input end of the two-way selector, the other input end of the two-way selector is grounded, and the output end is connected to the L1 input end of the loop filter. The input signal of the channel is connected to the L0 end of the loop filter, and the output of the loop filter is connected to the input end of the comparator. The output of the comparator is the code stream of the Delta Sigma modulator, and the code stream is connected to the control end of the two-way selector.

[0028] Beneficial effects: The present invention uses a relatively low-frequency periodic clock signal to chop the input signal, which can reduce the switching capacitance effect and the impact on the input DC voltage. At the same time, the flicker noise and mismatch in the circuit appear at the output end of the buffer to be equivalent to the effect of chopping the signal by using the XOR of a relatively low-frequency periodic clock and the output code stream of the Delta Sigma modulator. The present invention is particularly suitable for providing a reference voltage for a fully integrated bandgap reference circuit and an on-chip low-pass filter. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, and the above and / or other advantages of the present invention will become more apparent.

[0030] Figure 1The present invention provides a circuit diagram of a chopper-stabilized buffer suitable for a Delta Sigma modulator.

[0031] Figure 2 This is a structural diagram of a Delta Sigma modulator provided by the present invention.

[0032] Figure 3 The present invention provides a circuit diagram of a third chopper clock signal generator in a chopper-stabilized buffer suitable for a Delta Sigma modulator.

[0033] Figure 4 The present invention provides a schematic diagram of the waveforms of clock signals of three choppers in a chopper-stabilized buffer suitable for a Delta Sigma modulator.

[0034] Figure 5 The figure is a schematic diagram of the frequency spectrum of an output signal of a Delta Sigma modulator provided by the present invention. DETAILED DESCRIPTION

[0035] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0036] The chopper-stabilized buffer suitable for a Delta Sigma modulator and the Delta Sigma modulator provided in this embodiment can be applied to metering chips and other high-precision sensor chips.

[0037] The first embodiment of the present application discloses a chopper-stabilized buffer suitable for a Delta Sigma modulator, comprising a first chopper, a folded input stage, a second chopper, a common-gate amplifier stage, a third chopper, and a Miller amplifier stage:

[0038] The first chopper has an input signal and an output signal of the chopper-stabilized buffer as input, outputs a first signal, and the output is connected to the folding input stage;

[0039] The folding input stage has an output connected to the input of the second chopper, and is used to separate flicker noise and mismatch from the first signal to obtain a first error amplified signal in the form of current;

[0040] The second chopper has an output connected to the input of the common-gate amplifier stage, and uses the output code stream of the Delta Sigma modulator as a clock to chop and modulate the first error amplified signal to obtain a second signal in the form of current;

[0041] The common-gate amplifier stage has an output connected to the input of the third chopper, and is used to amplify the second signal and convert the second signal in current form into a second error amplified signal in voltage form;

[0042] The third chopper has an output connected to the input terminal of the Miller amplifier stage and the bias terminal of the common-gate amplifier stage, and uses the exclusive OR of the clock signals of the first chopper and the second chopper as a clock to chop and modulate the second error amplified signal, and output a third signal;

[0043] The Miller amplifier stage is used to amplify the third signal and output it.

[0044] The input signal of the chopper-stabilized buffer is a reference voltage provided by a fully integrated bandgap reference circuit and an on-chip low-pass filter.

[0045] In this embodiment, the first chopper uses a periodic clock signal having a bandwidth higher than that of a Delta Sigma modulator signal as a chopping clock.

[0046] The folded input stage includes a current source tube, an input pair tube, a low-pass filter, a load pair tube and a coupling capacitor, wherein the current source tube is used to provide current to the input pair tube;

[0047] The input pair of transistors is used to receive the first signal and convert the first signal in voltage form into a first error amplified signal in current form;

[0048] The low-pass filter is used to obtain low-frequency flicker noise and mismatch, and send them to the gate of the load pair tube;

[0049] The load pair is configured to receive low-frequency flicker noise and mismatch and isolate the first error amplified signal at the first chopping frequency. Specifically, the load pair is configured to be a low-resistance diode connection for low-frequency flicker noise and mismatch, and a high-resistance current source connection for the first error amplified signal at the first chopping frequency. That is, the first error amplified signal does not enter the gate. Thus, the load pair is configured to be a current source for the first error amplified signal, and the drain is in a high-resistance state.

[0050] The coupling capacitor exhibits a high-pass characteristic and only passes the first error amplified signal at the first chopping frequency, thereby isolating low-frequency flicker noise and mismatch.

[0051] like Figure 1As shown, the current source transistors of the folded input stage include a first PMOS transistor M1, the input transistor pair includes a second PMOS transistor M2 and a third PMOS transistor M3, the load transistor pair includes a fourth NMOS transistor M4 and a fifth NMOS transistor M5, and the coupling capacitor includes a first capacitor C1 and a second capacitor C2. A reference voltage Vref is connected to the positive input of the first chopper, the output Vout of the chopper-stabilized buffer is connected to the negative input of the first chopper, the positive output of the first chopper is connected to the gate of the second PMOS transistor M2, and the negative output of the first chopper is connected to the gate of the third PMOS transistor M3. The sources of the second PMOS transistor M2 and the third PMOS transistor M3 are connected together and to the drain of the first PMOS transistor M1. The source of the first PMOS transistor M1 is connected to the power supply voltage, and the gate of the first PMOS transistor M1 is connected to the first bias voltage VP1. The drain VD1 of the second PMOS transistor M2 is connected to the positive input of the low-pass filter and the drain of the fourth NMOS transistor M4. The drain VD2 of the third PMOS transistor M3 is connected to the negative input of the low-pass filter and the drain of the fifth NMOS transistor M5. The positive output of the low-pass filter is connected to the gate of the fourth NMOS transistor M4, and the negative output of the low-pass filter is connected to the gate of the fifth NMOS transistor M5. The sources of the fourth NMOS transistor M4 and the fifth NMOS transistor M5 are both grounded. The drain VD1 of the second PMOS transistor M2 is connected to one end of the first capacitor C1, the other end of which is connected to the positive input of the second chopper. The drain VD2 of the third PMOS transistor M3 is connected to one end of the second capacitor C2, the other end of which is connected to the negative input of the second chopper.

[0052] The first chopper and folded input stage separate the flicker noise and signal from the folded input stage. The low-pass filter and load pair of transistors (fourth NMOS transistor M4 and fifth NMOS transistor M5) present low impedance to low-frequency flicker noise and mismatch, and high impedance to higher-frequency signals. The coupling capacitor presents a high negative impedance to low-frequency flicker noise and mismatch, and a low impedance to higher-frequency signals. Consequently, the flicker noise and mismatch from the folded input stage flow to the load transistor, while the signal passes through the coupling capacitor and the second chopper to the common-gate amplifier stage. Figure 1 V in offset1 It is the equivalent of low-frequency flicker noise and mismatch.

[0053] As a preferred solution, Figure 1As shown, the common-gate amplifier stage includes a sixth PMOS transistor M6, a seventh PMOS transistor M7, an eighth PMOS transistor M8, a ninth PMOS transistor M9, a tenth NMOS transistor M10, an eleventh NMOS transistor M11, a twelfth NMOS transistor M12, and a thirteenth NMOS transistor M13. The positive output terminal of the second chopper is connected to the source of the eleventh NMOS transistor M11 and the drain of the thirteenth NMOS transistor M13, and the negative output terminal of the second chopper is connected to the source of the tenth NMOS transistor M10 and the drain of the twelfth NMOS transistor M12. The gates of the tenth NMOS transistor M10 and the eleventh NMOS transistor M11 are both connected to a fourth bias voltage VN2. The drain of the tenth NMOS transistor M10 is connected to the drain of the eighth PMOS transistor M8 and the positive input terminal of the third chopper. The drain of the eleventh NMOS transistor M11 is connected to the drain of the ninth PMOS transistor M9 and the negative input terminal of the third chopper. The gates of the eighth PMOS transistor M8 and the ninth PMOS transistor M9 are both connected to the second bias voltage VP2, the source of the eighth PMOS transistor M8 is connected to the drain of the sixth PMOS transistor M6, and the source of the ninth PMOS transistor M9 is connected to the drain of the seventh PMOS transistor M7. The gates of the sixth PMOS transistor M6 and the seventh PMOS transistor M7 are both connected to the positive output terminal of the third chopper, and the sources of the sixth PMOS transistor M6 and the seventh PMOS transistor M7 are both connected to the power supply voltage. The gates of the twelfth NMOS transistor M12 and the thirteenth NMOS transistor M13 are both connected to the third bias voltage VN1, and the sources of the twelfth NMOS transistor M12 and the thirteenth NMOS transistor M13 are both grounded. Figure 1 V in offset2 It is the equivalent of flicker noise and mismatch of the common-gate amplifier stage. Figure 2 V in offset =V offset1 +V offset2 .

[0054] The first chopper uses a periodic clock signal with a bandwidth higher than that of the Delta Sigma modulator signal as the chopping clock, the second chopper uses the output code stream of the Delta Sigma modulator as the chopping clock, and the third chopper uses the XOR of the chopping clock of the first chopper and the chopping clock of the second chopper as the chopping clock. Figure 3 As shown, the clock signal CLK1 of the first chopper is input to one input of the XOR gate, and the clock signal CLK2 of the second chopper (i.e., the output code stream of the Delta Sigma modulator) is connected to the other output of the XOR gate. The output of the XOR gate is the clock signal CLK3 of the third chopper. The waveforms of CLK1, CLK2, and CLK3 are shown in Figure 1. Figure 4 As shown, CLK1 is a periodic signal with a relatively low frequency, and the frequencies of CLK2 and CLK3 are much higher than CLK1.

[0055] In this embodiment, Figure 1 As shown, the Miller amplifier includes a fourteenth PMOS transistor M14, a fifteenth NMOS transistor M15, a third capacitor C3, and a first resistor R1. The negative output end of the third chopper is connected to the gate of the fourteenth PMOS transistor M14 and one end of the third capacitor C3. The other end of the third capacitor C3 is connected to one end of the first resistor R1. The other end of the first resistor R1 is connected to the drain of the fourteenth PMOS transistor M14 and the drain of the fifteenth NMOS transistor M15. The source of the fourteenth PMOS transistor M14 is connected to the power supply voltage, the gate of the fifteenth NMOS transistor M15 is connected to the first bias voltage VN1, and the source of the fifteenth NMOS transistor M15 is grounded.

[0056] A second embodiment of the present application discloses a Delta Sigma modulator comprising at least one channel, each channel comprising the aforementioned chopper-stabilized buffer, wherein the input signal of the chopper-stabilized buffer is a reference voltage provided by a fully integrated bandgap reference circuit and an on-chip low-pass filter.

[0057] like Figure 2 As shown, the bandgap reference voltage passes through a low-pass filter composed of a resistor Ro and a capacitor Co and is input to the input terminals of the chopper-stabilized buffers of multiple channels. Within each channel, the output voltage of the chopper-stabilized buffer is input to one input terminal of a two-way selector MUX. The other input terminal of the two-way selector MUX is grounded, and the output terminal is connected to the L1 input terminal of the loop filter. The input signal of the channel is connected to the L0 terminal of the loop filter. The output of the loop filter is connected to the input terminal of the comparator. The output of the comparator is the bit stream BS of the Delta Sigma modulator, and the output bit stream BS is connected to the control terminal of the two-way selector MUX. In the fully integrated circuit, in order to reduce the noise of the reference voltage Vref, the resistance value of the resistor Ro is large. Thanks to the first chopper clock of this embodiment being a relatively low-frequency periodic signal, its frequency is much lower than the frequency of the output bit stream BS of the Delta Sigma modulator. This greatly reduces the switching capacitance effect at the buffer input, and the impact on the DC voltage value of the reference voltage Vref can be made negligible.

[0058] In this embodiment, the flicker noise and mismatch of the common-gate amplifier stage are modulated by a third chopper to a lower-frequency periodic clock, which is then XORed with the output bit stream of the Delta Sigma modulator. Since the Delta Sigma modulator internally uses the buffer's output voltage according to the Delta Sigma modulator's output bit stream, the output bit stream BS controls the two-way selector MUX to determine whether the input of loop filter L1 is connected to the buffer output or ground. At the output of the two-way selector MUX, the reference voltage is effectively chopped using the lower-frequency periodic clock. At the output of the Delta Sigma modulator, the flicker noise and mismatch of the chopper-stabilized buffer are modulated at the frequency of the periodic clock signal CLK1, allowing subsequent digital filtering to remove them.

[0059] Figure 5 This is a diagram of the frequency spectrum of the output signal of the Delta Sigma modulator, where fs is the sampling frequency, OSR is the oversampling rate of the Delta Sigma modulator, and f CLK1 is the frequency of the clock signal CLK1, then the signal bandwidth of the Delta Sigma modulator is fs / 2 / OSR, and the quantization noise of the Delta Sigma modulator is located at a high frequency. When the buffer is not chopped and modulated, the flicker noise and mismatch voltage of the buffer are near the DC frequency at the output end of the Delta Sigma modulator, which is within the signal bandwidth, thereby affecting the signal-to-noise ratio of the Delta Sigma modulator; when the chopper-stabilized buffer of the present invention is used, the flicker noise and mismatch voltage of the buffer are at f at the output end of the Delta Sigma modulator. CLK1 Frequency near f CLK1 The frequency is higher than the signal bandwidth fs / 2 / OSR, and the subsequent digital filtering can filter it out, so it will not affect the signal-to-noise ratio of the Delta Sigma modulator.

[0060] The present invention provides a chopper-stabilized buffer suitable for a delta-sigma modulator. There are numerous methods and approaches for implementing this technical solution. The foregoing description is merely a specific embodiment of the present invention. It should be noted that those skilled in the art may make various improvements and modifications without departing from the principles of the present invention, and such improvements and modifications are also within the scope of protection of the present invention. Components not specified in this embodiment may be implemented using existing technologies.

Claims

1. A chopper-stabilized buffer for a Delta Sigma modulator, characterized in that: It includes a first chopper, a folded input stage, a second chopper, a common-gate amplifier stage, a third chopper and a Miller amplifier stage. The first chopper has an input signal and an output signal of the chopper-stabilized buffer as input, outputs a first signal, and the output is connected to the folding input stage; The folding input stage, whose output is connected to the input terminal of the second chopper, is used to separate the flicker noise and the mismatch from the first signal to obtain a first error amplified signal in the form of current; The second chopper has an output connected to the input of the common-gate amplifier stage, and uses the output code stream of the Delta Sigma modulator as a clock to perform chopping modulation on the first error amplified signal to obtain a second signal in the form of current; The common-gate amplifier stage has an output connected to the input end of the third chopper, and is used to amplify the second signal and convert the second signal in the form of current into a second error amplified signal in the form of voltage; A third chopper, the output of which is connected to the input end of the Miller amplifier stage and the bias end of the common-gate amplifier stage, uses the exclusive OR of the clock signals of the first chopper and the second chopper as a clock to chop and modulate the second error amplified signal, and outputs a third signal; The Miller amplifier stage is used to amplify the third signal and output it.

2. A chopper-stabilized buffer suitable for a Delta Sigma modulator according to claim 1, characterized in that: The first chopper uses a periodic clock signal with a bandwidth higher than that of a Delta Sigma modulator signal as a chopping clock.

3. A chopper-stabilized buffer suitable for a Delta Sigma modulator according to claim 2, characterized in that: The folded input stage includes a current source tube, an input pair tube, a low-pass filter, a load pair tube and a coupling capacitor, wherein the current source tube is used to provide current for the input pair tube; The input pair of transistors is used to receive the first signal and convert the first signal in voltage form into a first error amplified signal in current form; The low-pass filter is used to obtain low-frequency flicker noise and mismatch, and send them to the grid of the load pair tube; The load pair tube is used to receive low-frequency flicker noise and mismatch and isolate the first error amplification signal at the first chopping frequency; The coupling capacitor exhibits a high-pass characteristic, is used to isolate low-frequency flicker noise and mismatch, and only passes the first error amplification signal at the first chopping frequency.

4. A chopper-stabilized buffer suitable for a Delta Sigma modulator according to claim 3, characterized in that: A fully integrated bandgap reference circuit and an on-chip low-pass filter provide a reference voltage as the input signal to the chopper-stabilized buffer.

5. A chopper-stabilized buffer suitable for a Delta Sigma modulator according to claim 4, characterized in that: The current source tube of the folded input stage includes a first PMOS tube M1, and the input pair tube includes a second PMOS tube M2 and a third PMOS tube M3. The reference voltage Vref is connected to the positive input terminal of the first chopper, the output Vout of the chopper-stabilized buffer is connected to the negative input terminal of the first chopper, the positive output terminal of the first chopper is connected to the gate of the second PMOS tube M2, and the negative output terminal of the first chopper is connected to the gate of the third PMOS tube M3; The source of the second PMOS tube M2 and the source of the third PMOS tube M3 are connected together and connected to the drain of the first PMOS tube M1. The source of the first PMOS tube M1 is connected to the power supply voltage. The gate of the first PMOS tube M1 is connected to the first bias voltage VP1.

6. A chopper-stabilized buffer suitable for a Delta Sigma modulator according to claim 5, characterized in that: The load pair of tubes includes a fourth NMOS tube M4 and a fifth NMOS tube M5, the coupling capacitor includes a first capacitor C1 and a second capacitor C2, the drain VD1 of the second PMOS tube M2 is connected to the positive input end of the low-pass filter and the drain of the fourth NMOS tube M4, the drain VD2 of the third PMOS tube M3 is connected to the negative input end of the low-pass filter and the drain of the fifth NMOS tube M5; the positive output end of the low-pass filter is connected to the gate of the fourth NMOS tube M4, and the negative output end of the low-pass filter is connected to the gate of the fifth NMOS tube M5; the source of the fourth NMOS tube M4 and the source of the fifth NMOS tube M5 are both grounded; the drain VD1 of the second PMOS tube M2 is connected to one end of the first capacitor C1, and the other end of the first capacitor C1 is connected to the positive input end of the second chopper; the drain VD2 of the third PMOS tube M3 is connected to one end of the second capacitor C2, and the other end of the second capacitor C2 is connected to the negative input end of the second chopper.

7. A chopper-stabilized buffer suitable for a Delta Sigma modulator according to claim 6, characterized in that: The common-gate amplifier stage includes a sixth PMOS tube M6, a seventh PMOS tube M7, an eighth PMOS tube M8, a ninth PMOS tube M9, a tenth NMOS tube M10, an eleventh NMOS tube M11, a twelfth NMOS tube M12 and a thirteenth NMOS tube M13; the positive output end of the second chopper is connected to the source of the eleventh NMOS tube M11 and the drain of the thirteenth NMOS tube M13, and the negative output end of the second chopper is connected to the source of the tenth NMOS tube M10 and the drain of the twelfth NMOS tube M12; the gate of the tenth NMOS tube M10 and the gate of the eleventh NMOS tube M11 are both connected to the fourth bias voltage VN2, the drain of the tenth NMOS tube M10 is connected to the drain of the eighth PMOS tube M8 and the positive input end of the third chopper, and the eleventh NMOS tube M11 is connected to the drain of the eighth PMOS tube M8 and the positive input end of the third chopper. The drain of the eighth PMOS tube M8 and the gate of the ninth PMOS tube M9 are both connected to the second bias voltage VP2, the source of the eighth PMOS tube M8 is connected to the drain of the sixth PMOS tube M6, and the source of the ninth PMOS tube M9 is connected to the drain of the seventh PMOS tube M7; the gate of the sixth PMOS tube M6 and the gate of the seventh PMOS tube M7 are both connected to the positive output end of the third chopper, and the source of the sixth PMOS tube M6 and the source of the seventh PMOS tube M7 are both connected to the power supply voltage; the gate of the twelfth NMOS tube M12 and the gate of the thirteenth NMOS tube M13 are both connected to the third bias voltage VN1, and the source of the twelfth NMOS tube M12 and the source of the thirteenth NMOS tube M13 are both grounded.

8. A chopper-stabilized buffer suitable for a Delta Sigma modulator according to claim 7, characterized in that: The Miller amplifier stage includes a fourteenth PMOS tube M14, a fifteenth NMOS tube M15, a third capacitor C3 and a first resistor R1, the negative output end of the third chopper is connected to the gate of the fourteenth PMOS tube M14 and one end of the third capacitor C3, the other end of the third capacitor C3 is connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to the drain of the fourteenth PMOS tube M14 and the drain of the fifteenth NMOS tube M15, the source of the fourteenth PMOS tube M14 is connected to the power supply voltage, the gate of the fifteenth NMOS tube M15 is connected to the bias voltage first VN1, and the source of the fifteenth NMOS tube M15 is grounded.

9. A Delta Sigma modulator, characterized in that: The invention comprises at least one channel, each channel comprises the chopper-stabilized buffer according to any one of claims 1 to 8, and the input signal of the chopper-stabilized buffer is a reference voltage provided by a fully integrated bandgap reference circuit and an on-chip low-pass filter.

10. A Delta Sigma modulator according to claim 9, characterized in that: Each channel also includes a two-way selector, a loop filter and a comparator. The output voltage of the chopper-stabilized buffer is input to one input end of the two-way selector, the other input end of the two-way selector is grounded, the output end is connected to the L1 input end of the loop filter, the input signal of the channel is connected to the L0 end of the loop filter, the output of the loop filter is connected to the input end of the comparator, the output of the comparator is the code stream of the Delta Sigma modulator, and the code stream is connected to the control end of the two-way selector.

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