CMOS Current Multiplexing Self-Oscillation Receiver Front End

Abstract

The present invention discloses a CMOS current multiplexing self-oscillating receiver front end, comprising a low-noise transconductance amplifier circuit and a mixer, and an orthogonal voltage-controlled oscillator; the input ends of the low-noise transconductance amplifier circuit Gm are Vin+ and Vin-; the mixer comprises a first mixer and a second mixer; the output end V1 of the low-noise transconductance amplifier circuit Gm is connected to the input end Vm1 of the first mixer and the input end Vm3 of the second mixer, and the input end V of the orthogonal voltage-controlled oscillator QVCO is connected to the output end V Q1 The output terminal V2 of the low noise transconductance amplifier circuit Gm and the input terminal Vm2 of the first mixer are connected to the input terminal Vm4 of the second mixer and the input terminal V of the orthogonal voltage controlled oscillator QVCO. Q2 The current of the transconductor of the present invention is reused by the mixer and the oscillator, which significantly reduces power consumption.

Description

Technical Field

[0001] The present invention relates to the technical field of radio frequency integrated circuits, in particular to a CMOS current multiplexing type self-oscillating receiver front end. Background Art

[0002] With the development of semiconductor integrated circuits and the booming development of wireless communications, the front-end circuits of receivers are constantly facing technological innovation and performance improvement. Among them, the demand for low power consumption has become more and more prominent. At the same time, it is noted that orthogonal signal generation is very commonly used for direct frequency conversion receiver structures. In retrospect, the commonly used methods for generating orthogonal signals include using analog multiphase filtering structures, or digital orthogonal logic gate frequency division structures, or direct orthogonal coupled VCO structures; for the current millimeter wave broadband communication application field, the first two structures are limited by technical bottlenecks and are no longer competent, resulting in orthogonal coupled oscillators becoming a rare effective solution. Its superior power and area efficiency are attractive technical advantages; however, traditional orthogonal coupled oscillators have the disadvantages of phase noise and poor orthogonal accuracy performance.

[0003] In traditional technology, low noise amplifiers, mixers, and oscillators are usually designed in a modular way, which means that, to a large extent, they are designed as independent modules and finally connected together. Over the years, there have been continuous innovative designs trying to highly integrate these modules to reduce the power consumption of the receiver. Typical representatives include Figure 1 It is shown that in the existing literature 1, its innovative structure includes an oscillator and a mixer, and the oscillator is stacked on the output load of the mixer and shares the DC path; this circuit is called a self-oscillating mixer. However, there is a trade-off between the phase noise of the oscillator and the noise index of the mixer. Low phase noise requires the oscillator to have sufficient bias current, but this will inevitably cause the switch to contribute a large amount of noise, which will deteriorate the noise index of the mixer. In addition, this structure does not have orthogonal performance and cannot be applied to mainstream direct conversion receiver solutions. For this reason, we propose a more practical CMOS current multiplexing self-oscillating receiver front end. Summary of the invention

[0004] The purpose of the present invention is to provide a CMOS current multiplexing type self-oscillating receiver front end, which solves the existing problems.

[0005] To achieve the above object, the present invention provides the following technical solution: a CMOS current multiplexing self-oscillating receiver front end, comprising a low-noise transconductance amplifier circuit and a mixer, and an orthogonal voltage-controlled oscillator;

[0006] The input terminals of the low noise transconductance amplifier circuit Gm are Vin+ and Vin- respectively;

[0007] The mixer includes a first mixer and a second mixer;

[0008] The output terminal V1 of the low noise transconductance amplifier circuit Gm is connected to the input terminal Vm1 of the first mixer and the input terminal Vm3 of the second mixer, as well as the input terminal V Q1 The output terminal V2 of the low noise transconductance amplifier circuit Gm and the input terminal Vm2 of the first mixer are connected to the input terminal Vm4 of the second mixer and the input terminal V of the orthogonal voltage controlled oscillator QVCO. Q2 connect.

[0009] Preferably, the low-noise transconductance amplifier circuit includes NMOS tube Mn1, NMOS tube Mn2, PMOS tube Mp1, PMOS tube Mp2, PMOS tube Mp3, PMOS tube Mp4, capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5, capacitor C6, capacitor C16, capacitor C17, capacitor Cntr1, capacitor Cntr2, inductor L5, resistor R9, resistor R10, resistor R11, resistor R12, resistor R13 and resistor R14.

[0010] Preferably, one end of the capacitor C1 is connected to one end of the capacitor C2 and one end of the capacitor C16 as the input end Vin+ of the low-noise transconductance amplifier circuit, the other end of the capacitor C2 is connected to the gate end of the NMOS tube Mn1, one end of the capacitor Cntr1 and one end of the resistor R10, the source end of the NMOS tube Mn1 is grounded, the drain end of the NMOS tube Mn1 is connected to the drain end of the PMOS tube Mp3, and the drain end of the PMOS tube Mp1 is connected to one end of the capacitor Cntr2 as the low-noise The output end V1 of the acoustic transconductance amplifier circuit, the gate end of the PMOS tube Mp3 is connected to the other end of the capacitor C1 and one end of the resistor R9, the source end of the PMOS tube Mp3 is connected to the power supply voltage VDD, the gate end of the PMOS tube Mp1 is connected to one end of the capacitor C6 and one end of the resistor R11, the source end of the PMOS tube Mp1 is connected to one end of the capacitor C5 and one end of the capacitor C17 and the a end of the inductor L5, the c end of the inductor L5 is connected to the power supply voltage VDD, and the inductor L The b end of the transistor 5 is connected to the other end of the capacitor C16 and the other end of the capacitor C6 is connected to the source end of the PMOS tube Mp2, the gate end of the PMOS tube Mp2 is connected to the other end of the capacitor C5 and one end of the resistor R12, the other end of the resistor R12 is connected to the other end of the resistor R11, the drain end of the PMOS tube Mp2 is connected to the other end of the capacitor Cntr1 and the drain end of the PMOS tube Mp4 and the drain end of the NMOS tube Mn2 as the output end V2 of the low noise transconductance amplifier circuit, the source end of the PMOS tube Mp4 is connected to the power supply voltage VDD, the gate end of the PMOS tube Mp4 is connected to one end of the capacitor C4 and one end of the resistor R13, the other end of the capacitor C4 is connected to the other end of the capacitor C17 and one end of the capacitor C3 as the input end Vin- of the low noise transconductance amplifier circuit, the other end of the capacitor C3 is connected to the gate end of the NMOS tube Mn2 and the other end of the capacitor Cntr2 and one end of the resistor R14, and the source end of the NMOS tube Mn2 is grounded.

[0011] Preferably, the output terminals of the first mixer are IFq+ and IFq-, respectively, and the input terminal LO0 of the first mixer is connected to the output terminal V QO2 The first mixer input terminal LO2 is connected to the output terminal V of the orthogonal voltage controlled oscillator QVCO through the capacitor C10. QO1 The output terminals of the second mixer are IFi+ and IFi-, respectively, and the input terminal LO3 of the second mixer is connected to the output terminal V QO3 The input terminal LO1 of the second mixer is connected to the output terminal V of the orthogonal voltage controlled oscillator QVCO through the capacitor C8. QO4 connect.

[0012] Preferably, the first mixer and the second mixer have the same structure, including a PMOS tube M1, a PMOS tube M2, an NMOS tube M3, an NMOS tube M4, an NMOS tube M5, an NMOS tube M6, a capacitor C L1 , resistor R L1 , resistor R L2 , resistor R7 and resistor R8, and comparator Opamp.

[0013] Preferably, the gate end of the NMOS tube M4 is connected to the gate end of the NMOS tube M5 and one end of the resistor R7 as the input end V of the mixer. LO+ The source end of the NMOS tube M4 is connected to the source end of the NMOS tube M3 as Vmix+, and the drain end of the NMOS tube M4 is connected to the drain end of the PMOS tube M1 and the resistor R L1 One end and capacitor C L1 The output terminal of the mixer is connected to the drain terminal of the NMOS tube M6 as the output terminal IF+ of the mixer, the source terminal of the PMOS tube M1 is connected to the power supply voltage VDD, the gate terminal of the PMOS tube M1 is connected to the output terminal of the comparator Opamp and the gate terminal of the PMOS tube M2, the positive terminal of the comparator Opamp is connected to the reference voltage vref, and the negative terminal of the comparator Opamp is connected to the resistor R L1 The other end and resistor R L2 One end of the resistor R L2 The other end is connected to the drain end of PMOS tube M2 and capacitor C L1 The other end of the NMOS tube M3 is connected to the drain end of the NMOS tube M3 as the output end IF- of the mixer, the source end of the PMOS tube M2 is connected to the power supply voltage VDD, and the gate end of the NMOS tube M3 is connected to the gate end of the NMOS tube M6 and one end of the resistor R8 as the input end V LO- The other end of the resistor R8 is connected to the other end of the resistor R7, and the source end of the NMOS tube M6 is connected to the source end of the NMOS tube M5 as Vmix-.

[0014] Preferably, the orthogonal voltage-controlled oscillator includes inductor L1, inductor L2, inductor L3, inductor L4, NMOS tube Mn3, NMOS tube Mn4, PMOS tube Mp5, PMOS tube Mp6, NMOS tube Mn5, NMOS tube Mn6, PMOS tube M7, NMOS tube M8, resistor R1, resistor R2, resistor R3, resistor R4, resistor R5, resistor R6, capacitor C7, capacitor C12, capacitor C13, capacitor Cp1, capacitor Cp2, capacitor C14, capacitor C15, variable capacitor Cvar1, variable capacitor Cvar2, variable capacitor Cvar3 and variable capacitor Cvar4.

[0015] Preferably, the a terminal of the inductor L4 is connected to the input terminal VQ1 , the b terminal of the inductor L4 is connected to the input terminal V Q2 The c-end of the inductor L4 is connected to the drain end of the PMOS tube M7 and the source end of the NMOS tube M8 and the drain end of the NMOS tube M8, the gate end of the NMOS tube M8 is connected to the power supply voltage VDD, the gate end of the PMOS tube M7 is connected to the bias voltage Vbp2, the source end of the PMOS tube M7 is connected to one end of the capacitor C7 and the c-end of the inductor L3, the other end of the capacitor C7 is grounded, the a-end of the inductor L3 is connected to the source end of the NMOS tube Mn3 and the source end of the NMOS tube Mn4 and the drain end of the PMOS tube Mp5 and one end of the capacitor Cp1, the gate end of the NMOS tube Mn3 is connected to the resistor R1 and one end of the capacitor C13 The drain end of the NMOS tube Mn3 is connected to one end of the capacitor C12, one end of the variable capacitor Cvar1 and the a end of the inductor L1 as the output end Vosc+ of the orthogonal voltage controlled oscillator, the c end of the inductor L1 is connected to the power supply voltage VDD, the b end of the inductor L1 is connected to the drain end of the NMOS tube Mn4, the other end of the capacitor C13 and one end of the variable capacitor Cvar2 as the output end Vosc- of the orthogonal voltage controlled oscillator, the other end of the variable capacitor Cvar2 is connected to the other end of the variable capacitor Cvar1, the gate end of the NMOS tube Mn4 is connected to the other end of the capacitor C12 and one end of the resistor R2, the other end of the resistor R2 is connected to the gate end of the NMOS tube Mn4 One end is connected to the other end of the resistor R1, the b end of the inductor L3 is connected to the source end of the NMOS tube Mn6, the source end of the NMOS tube Mn5, the drain end of the PMOS tube Mp6 and one end of the capacitor Cp2, the gate end of the NMOS tube Mn6 is connected to the resistor R6 and one end of the capacitor C14, the drain end of the NMOS tube Mn6 is connected to one end of the capacitor C15, one end of the variable capacitor Cvar4 and the b end of the inductor L2 as the output end Voscq- of the orthogonal voltage controlled oscillator, the c end of the inductor L2 is connected to the power supply voltage VDD, the a end of the inductor L2 is connected to the drain of the NMOS tube Mn5, the other end of the capacitor C14, the variable capacitor C var3, the other end of the variable capacitor Cvar3 is connected to the other end of the variable capacitor Cvar4, the gate end of the NMOS tube Mn5 is connected to the other end of the capacitor C15 and one end of the resistor R5, the other end of the resistor R5 is connected to the other end of the resistor R6, the gate end of the PMOS tube Mp6 is connected to one end of the resistor R4 and the other end of the capacitor Cp1, the source end of the PMOS tube Mp6 is connected to the source end of the PMOS tube Mp5 and the power supply voltage VDD, the gate end of the PMOS tube Mp5 is connected to one end of the resistor R3 and the other end of the capacitor Cp2, and the other end of the resistor R3 is connected to the other end of the resistor R4.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] 1. The current of the transconductor of the present invention is reused by the mixer and the oscillator, which significantly reduces power consumption.

[0018] 2. The auxiliary positive feedback cross-coupling structure of the present invention improves the differential mode loop gain of the tail node transformer, making the output signal phase quadrature accuracy of the orthogonal oscillator more accurate and the phase noise lower. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a diagram of the traditional self-oscillating mixer circuit structure;

[0020] Figure 2 It is the front-end architecture diagram of the present invention;

[0021] Figure 3 It is a specific circuit diagram of the present invention;

[0022] Figure 4 It is a schematic diagram of a low noise transconductance amplifier circuit of the present invention;

[0023] Figure 5 is a schematic diagram of a mixer of the present invention;

[0024] Figure 6 is a schematic diagram of an orthogonal voltage-controlled oscillator of the present invention;

[0025] Figure 7 Schematic diagram of input matching characteristic S11 of the present invention;

[0026] Figure 8 Schematic diagram of gain bandwidth of the present invention

[0027] Fig. 9 A schematic diagram of the noise coefficient of the present invention;

[0028] Fig.10 is a schematic diagram of the in-band linearity of the present invention;

[0029] Fig.11 is a schematic diagram of the oscillation frequency of the orthogonal oscillator of the present invention;

[0030] Fig.12 is a phase noise schematic diagram of the present invention;

[0031] Fig.13 is a schematic diagram of the orthogonal phase error of the orthogonal oscillator of the present invention;

[0032] Fig.14 It is a schematic diagram of the differential phase error of the orthogonal oscillator of the present invention. DETAILED DESCRIPTION

[0033] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0034] Specific implementation case 1

[0035] like Figure 1 and Figure 2 As shown, a CMOS current multiplexing self-oscillating receiver front end includes a low-noise transconductance amplifier circuit and a mixer, and an orthogonal voltage-controlled oscillator;

[0036] The input terminals of the low noise transconductance amplifier circuit Gm are Vin+ and Vin- respectively;

[0037] The mixer includes a first mixer and a second mixer;

[0038] The output terminal V1 of the low noise transconductance amplifier circuit Gm is connected to the input terminal Vm1 of the first mixer and the input terminal Vm3 of the second mixer, as well as the input terminal V Q1 The output terminal V2 of the low noise transconductance amplifier circuit Gm and the input terminal Vm2 of the first mixer are connected to the input terminal Vm4 of the second mixer and the input terminal V of the orthogonal voltage controlled oscillator QVCO. Q2 connect;

[0039] The input RF signal is input from both ports Vin+ and Vin-, converted into current by a low-noise transconductance amplifier circuit, and mixed by a mixer to obtain useful intermediate frequency signal outputs IFi+ / - and IFq+ / -. In particular, the local oscillator source of the mixer is provided by a self-oscillating voltage-controlled oscillator, and the DC current of the oscillator and the mixer is reused by the transconductor, thereby achieving the effect of reducing power consumption; in addition, based on the superharmonic coupling structure, an auxiliary cross-coupling structure is adopted, and the oscillator can provide a local oscillator signal with high phase accuracy.

[0040] refer to Figure 3 The overall structure diagram of the present invention is clearly displayed. The front end of the CMOS current multiplexing self-oscillating receiver is composed of a low-noise transconductance amplifier circuit, a mixer, and an orthogonal voltage-controlled oscillator; the bias current of the low-noise transconductor is multiplexed by the mixer and the oscillator to achieve a low power consumption effect.

[0041] As for the low noise transconductor, its structure diagram is as follows Figure 4As shown, it includes a capacitor cross-coupled common-gate input structure (Mp1 / Mp2) for providing input impedance matching; it also includes a complementary common-source input stage (Mn1 / Mp3 and Mn2 / Mp4); the complementary common-source stage improves the input transconductance of the circuit on the one hand, and can also partially eliminate the noise of the common-gate input pole, and the capacitor cross-coupling (C5, C6) reduces the noise output of the common-gate transistor by half; so this structure ensures the low-noise effect of the circuit to a large extent; in addition, the cross-coupled neutralizing capacitors (Cntr1, Cntr2) are used to reduce the adverse effects of the Maitreya effect on input matching.

[0042] Mixer circuit in Figure 5 It is given that, based on the classic Gilbert fully differential structure, an active feedback structure is used at the intermediate frequency load; the active feedback structure samples the common mode level of the load resistance, and controls the gate bias of the transistor through the feedback of the comparator, thereby ensuring that the DC level bias of the load is appropriate and obtaining good linearity; at the same time, the bias current of the oscillator shunts the bias current of the transconductor through the transistor M7, so that the mixer obtains a reduced bias current and reduced noise output, and indirectly obtains the technical effect of current injection; further, the inductor L4 is used to resonate and absorb the parasitic capacitance of the tail node of the mixer switch tube, so that the noise charging and discharging effect of the switch tube is avoided, which is also beneficial to the low noise effect of the overall circuit.

[0043] Quadrature Oscillator Circuit Figure 6 The display includes two main LC oscillators and an auxiliary positive feedback cross-coupling structure (Mp5 / Mp6); specifically, the two LC oscillators use a transformer (L3) coupling structure at the tail node; in this way, while ensuring the reverse coupling resonance of the transformer at the 2f0 frequency (the transformer's self-inductance and the parasitic capacitance at the node), an orthogonal oscillation at the f0 frequency of the LC oscillator can be formed. However, the 2f0 frequency signal amplitude is very weak, and the transformer coupling coefficient is often less than 1. In this way, considering the mismatch caused by the layout, and the RF signal leaked from the transconductor and mixer through the M7 path, the strong common-mode interference generated on the transformer is likely to destroy the orthogonal oscillation of the LC oscillator at the f0 frequency and turn it into an undesirable same-direction oscillation.

[0044] In order to solve this problem, on the one hand, a positive feedback loop can be designed at the transformer to appropriately increase the differential loop gain of the tail node, thereby improving the orthogonality of the output signal of the LC oscillator; of course, the differential loop gain cannot be too large, so that the positive feedback cross-coupling structure and the transformer constitute another oscillator at the 2f0 frequency, affecting the on and off of the main LC oscillator transistor; specifically, the differential loop gain can be controlled and tuned by adjusting the control bias voltage Vadj; on the other hand, a filter capacitor is added through the M7 path to overcome the RF signal leakage of the transconductor mixer; in the case of RF input differential pair layout mismatch, there must be RF port signals that interfere with the differential mode operation of the oscillator tail node transformer in a common mode manner; of course, the 2f0 harmonic frequency signal at the mixer tail node directly constitutes the common mode interference of the oscillator tail node transformer. For these two mechanisms, two capacitors M8 and C7 can be added to filter them out; here, the transistor M8 acts as a filter capacitor. Although the transistor capacitor has noise and linearity disadvantages, the transistor M8 is located in the common mode path and will not affect the output of the mixer. The capacitor C7 can absorb the interference of the transistor M8 noise and nonlinearity on the oscillator. Thanks to the above design strategies, the accuracy of the orthogonal oscillator of the present invention is improved and guaranteed.

[0045] Injection locking is also a technical issue to be considered. In document 2, when the signal at the RF port is strong, it can be coupled to the output node of the intermediate frequency load through the parasitic capacitance of the mixer transistor, which may cause the oscillator there to be injection locked, and the mixer cannot operate at the desired intermediate frequency. In contrast, in the structure of the present invention, the strong signal at the RF port can be filtered out by the two capacitors M8 and C7, and the M7 transistor can also play a certain reverse isolation effect, making the present invention less prone to injection locking.

[0046] Specific implementation case 2

[0047] The current multiplexing self-oscillation direct frequency conversion receiver front-end circuit provided in this embodiment is designed and implemented using a 65nm standard CMOS process.

[0048] In the circuit, only the intermediate frequency load transistors (M1 / M2) of the mixer adopt a 250nm long channel structure to reduce flicker noise, and other transistors use a 60nm length to obtain good RF performance; the power supply voltage is 1.2V, the differential transconductor consumes 4.6mA*2, the overall power consumption is 12mW, the bias current of a single transistor of the mixer is 128uA, the current of M7 in the industrial mode path is 3.3mA, the auxiliary cross unit coupling consumes 0.3mA, the common gate input stage bias current is 0.6mA, the capacitor C7 is 15pF, and the equivalent capacitance of transistor M8 is 200pF; based on the above optimized bias current, the circuit simulation performance is obtained, and the results are as follows.

[0049] Figure 7 The simulation results of the input matching characteristic S11 of the circuit are given. It can be seen that in the 7.7-9.8GHz frequency band, S 11 All less than -10dB;

[0050] Figure 8 The simulation results of the circuit's gain-bandwidth are given. The 3dB bandwidth is about 50MHz, and at low frequencies, the gain is as high as 34.8dB.

[0051] Fig. 9 The simulation results of the noise factor NF of the circuit are given. It can be seen that within 1MHz to 100MHz, the noise factor is less than 3dB. And the flicker noise corner is around 400KHz;

[0052] Fig.10 The simulation result of the third-order intermodulation input IP3 of the circuit is given, which is -19.5dBm;

[0053] Fig.11 The orthogonal oscillator output waveform of the circuit is given. The frequency of the four signals is 8.5215GHz. Adjusting the tuning capacitor of the oscillator can change the frequency within a certain range. No more diagrams are given here.

[0054] Fig.12 The simulation results of the phase noise of the circuit are given. In the frequency range of 0.1MHz to 1MHz, the phase noise is reduced from -80dBc / Hz to -108dBc / Hz. Thanks to the cross-coupling structure of the oscillator auxiliary and the CLASS C configuration (avoiding the main oscillator transistor from entering the deep triode region, which causes the degradation of the loaded Q value of the LC resonant network), the phase noise has reached a good level.

[0055] Fig.13 The simulation results of the 270° phase error between the orthogonal ports of the orthogonal oscillator are given. The delay curve in the figure shows that its phase quadrature error is within 2° and its stabilization time is about 8ns. The simulation also shows that without the auxiliary cross-coupling structure, the obtained quadrature error is about 5°. A separate figure is not given here. The lower the orthogonal error, the better the demodulation signal-to-noise ratio of the receiver can be obtained at the baseband.

[0056] Fig.14 The simulation results of the 180° phase error of the circuit's orthogonal oscillator differential port are given, and the delay curve shows that a single oscillator has good differential performance and the stabilization time is within 1ns.

[0057] Table 1 shows a comprehensive performance comparison between the present invention and previous documents. It can be seen that the power consumption is the same, but the structure of the present invention provides an IQ dual-channel receiving method, which saves half the power compared to the comparative document for the same dual-channel reception, making the present invention very competitive; in terms of key electrical indicators, such as gain, noise / phase noise, the present invention also obtains overwhelming technical advantages. Even if the linearity is measured by the output IP3 (OIP3), the present invention also has significant advantages; the comparative document requires 6 inductors, which occupies a large area; the present invention requires 5 inductors / transformers, which reduces the chip area and cost. Based on the above comparison and discussion, the present invention proposes a current multiplexing type orthogonal receiver front end as a whole; the current of the oscillator and the mixer is reused by the transconductor, and the highly integrated circuit structure significantly reduces the power consumption and even simplifies the bias circuit; the orthogonal oscillator including the auxiliary cross-coupling structure provides more accurate phase accuracy and lower phase noise.

[0058] Table 1 Comprehensive performance comparison

[0059]

[0060] Among them, references 1 and 2 are both [Stanley SKHo; Carlos E. Saavedra “A Low-Noise Self-Oscillating Mixer Using a Balanced VCO Load,” IEEE Transactions on Circuits and Systems, vol. 58, no. 8, pp. 1705–1712, Feb. 2011.].

Claims

1. CMOS current multiplexing self-oscillating receiver front end, characterized in that: Including low noise transconductance amplifier circuit and mixer, and orthogonal voltage controlled oscillator; The input terminals of the low noise transconductance amplifier circuit Gm are Vin+ and Vin- respectively; The mixer includes a first mixer and a second mixer; The output terminal V1 of the low noise transconductance amplifier circuit Gm is connected to the input terminal Vm1 of the first mixer and the input terminal Vm3 of the second mixer, as well as the input terminal V Q1 The output terminal V2 of the low noise transconductance amplifier circuit Gm and the input terminal Vm2 of the first mixer are connected to the input terminal Vm4 of the second mixer and the input terminal V of the orthogonal voltage controlled oscillator QVCO. Q2 connect.

2. The CMOS current multiplexing self-oscillating receiver front end according to claim 1, characterized in that: The low-noise transconductance amplifier circuit includes NMOS tube Mn1, NMOS tube Mn2, PMOS tube Mp1, PMOS tube Mp2, PMOS tube Mp3, PMOS tube Mp4, capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5, capacitor C6, capacitor C16, capacitor C17, capacitor Cntr1, capacitor Cntr2, inductor L5, resistor R9, resistor R10, resistor R11, resistor R12, resistor R13 and resistor R14.

3. The CMOS current multiplexing self-oscillating receiver front end according to claim 2, characterized in that: One end of the capacitor C1 is connected to one end of the capacitor C2 and one end of the capacitor C16 as the input end Vin+ of the low noise transconductance amplifier circuit, the other end of the capacitor C2 is connected to the gate end of the NMOS tube Mn1, one end of the capacitor Cntr1 and one end of the resistor R10, the source end of the NMOS tube Mn1 is grounded, the drain end of the NMOS tube Mn1 is connected to the drain end of the PMOS tube Mp3, and the drain end of the PMOS tube Mp1 is connected to one end of the capacitor Cntr2 as the low noise transconductance amplifier circuit. The output end V1 of the amplifier circuit, the gate end of the PMOS tube Mp3 is connected to the other end of the capacitor C1 and one end of the resistor R9, the source end of the PMOS tube Mp3 is connected to the power supply voltage VDD, the gate end of the PMOS tube Mp1 is connected to one end of the capacitor C6 and one end of the resistor R11, the source end of the PMOS tube Mp1 is connected to one end of the capacitor C5 and one end of the capacitor C17 and the a end of the inductor L5, the c end of the inductor L5 is connected to the power supply voltage VDD, and the The b end is connected to the other end of the capacitor C16 and the other end of the capacitor C6 and the source end of the PMOS tube Mp2, the gate end of the PMOS tube Mp2 is connected to the other end of the capacitor C5 and one end of the resistor R12, the other end of the resistor R12 is connected to the other end of the resistor R11, the drain end of the PMOS tube Mp2 is connected to the other end of the capacitor Cntr1 and the drain end of the PMOS tube Mp4 and the drain end of the NMOS tube Mn2 as the output end V2 of the low noise transconductance amplifier circuit, the source end of the PMOS tube Mp4 is connected to the power supply voltage VDD, the gate end of the PMOS tube Mp4 is connected to one end of the capacitor C4 and one end of the resistor R13, the other end of the capacitor C4 is connected to the other end of the capacitor C17 and one end of the capacitor C3 as the input end Vin- of the low noise transconductance amplifier circuit, the other end of the capacitor C3 is connected to the gate end of the NMOS tube Mn2 and the other end of the capacitor Cntr2 and one end of the resistor R14, and the source end of the NMOS tube Mn2 is grounded.

4. The CMOS current multiplexing self-oscillating receiver front end according to claim 1, characterized in that: The output terminals of the first mixer are IFq+ and IFq-, respectively. The input terminal LO0 of the first mixer is connected to the output terminal V of the quadrature voltage controlled oscillator QVCO through a capacitor C11. QO2 The first mixer input terminal LO2 is connected to the output terminal V of the orthogonal voltage controlled oscillator QVCO through the capacitor C10. QO1 The output terminals of the second mixer are IFi+ and IFi-, respectively, and the input terminal LO3 of the second mixer is connected to the output terminal V QO3 The input terminal LO1 of the second mixer is connected to the output terminal V of the orthogonal voltage controlled oscillator QVCO through the capacitor C8. QO4 connect.

5. The CMOS current multiplexing self-oscillating receiver front end according to claim 1, characterized in that: The first mixer and the second mixer have the same structure, including a PMOS tube M1, a PMOS tube M2, an NMOS tube M3, an NMOS tube M4, an NMOS tube M5, an NMOS tube M6, a capacitor C L1 , resistor R L1 , resistor R L2 , resistor R7 and resistor R8, and comparator Opamp.

6. The CMOS current multiplexing self-oscillating receiver front end according to claim 5, characterized in that: The gate end of the NMOS tube M4 is connected to the gate end of the NMOS tube M5 and one end of the resistor R7 as the input end V of the mixer. LO+ The source end of the NMOS tube M4 is connected to the source end of the NMOS tube M3 as Vmix+, and the drain end of the NMOS tube M4 is connected to the drain end of the PMOS tube M1 and the resistor R L1 One end and capacitor C L1 The output terminal of the mixer is connected to the drain terminal of the NMOS tube M6 as the output terminal IF+ of the mixer, the source terminal of the PMOS tube M1 is connected to the power supply voltage VDD, the gate terminal of the PMOS tube M1 is connected to the output terminal of the comparator Opamp and the gate terminal of the PMOS tube M2, the positive terminal of the comparator Opamp is connected to the reference voltage vref, and the negative terminal of the comparator Opamp is connected to the resistor R L1 The other end and resistor R L2 One end of the resistor R L2 The other end is connected to the drain end of PMOS tube M2 and capacitor C L1 The other end of the NMOS tube M3 is connected to the drain end of the NMOS tube M3 as the output end IF- of the mixer, the source end of the PMOS tube M2 is connected to the power supply voltage VDD, and the gate end of the NMOS tube M3 is connected to the gate end of the NMOS tube M6 and one end of the resistor R8 as the input end V LO- The other end of the resistor R8 is connected to the other end of the resistor R7, and the source end of the NMOS tube M6 is connected to the source end of the NMOS tube M5 as Vmix-.

7. The CMOS current multiplexing self-oscillating receiver front end according to claim 1, characterized in that: The orthogonal voltage-controlled oscillator includes an inductor L1, an inductor L2, an inductor L3, an inductor L4, an NMOS tube Mn3, an NMOS tube Mn4, a PMOS tube Mp5, a PMOS tube Mp6, an NMOS tube Mn5, an NMOS tube Mn6, a PMOS tube M7, an NMOS tube M8, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a capacitor C7, a capacitor C12, a capacitor C13, a capacitor Cp1, a capacitor Cp2, a capacitor C14, a capacitor C15, a variable capacitor Cvar1, a variable capacitor Cvar2, a variable capacitor Cvar3 and a variable capacitor Cvar4.

8. The CMOS current multiplexing self-oscillating receiver front end according to claim 7, characterized in that: The a terminal of the inductor L4 is connected to the input terminal V Q1 , the b terminal of the inductor L4 is connected to the input terminal V Q2 The c-end of the inductor L4 is connected to the drain end of the PMOS tube M7 and the source end of the NMOS tube M8 and the drain end of the NMOS tube M8, the gate end of the NMOS tube M8 is connected to the power supply voltage VDD, the gate end of the PMOS tube M7 is connected to the bias voltage Vbp2, the source end of the PMOS tube M7 is connected to one end of the capacitor C7 and the c-end of the inductor L3, the other end of the capacitor C7 is grounded, the a-end of the inductor L3 is connected to the source end of the NMOS tube Mn3 and the source end of the NMOS tube Mn4 and the drain end of the PMOS tube Mp5 and one end of the capacitor Cp1, the gate end of the NMOS tube Mn3 is connected to the resistor R1 and one end of the capacitor C13 The drain end of the NMOS tube Mn3 is connected to one end of the capacitor C12, one end of the variable capacitor Cvar1 and the a end of the inductor L1 as the output end Vosc+ of the orthogonal voltage controlled oscillator, the c end of the inductor L1 is connected to the power supply voltage VDD, the b end of the inductor L1 is connected to the drain end of the NMOS tube Mn4, the other end of the capacitor C13 and one end of the variable capacitor Cvar2 as the output end Vosc- of the orthogonal voltage controlled oscillator, the other end of the variable capacitor Cvar2 is connected to the other end of the variable capacitor Cvar1, the gate end of the NMOS tube Mn4 is connected to the other end of the capacitor C12 and one end of the resistor R2, the other end of the resistor R2 is connected to the gate end of the NMOS tube Mn4 One end is connected to the other end of the resistor R1, the b end of the inductor L3 is connected to the source end of the NMOS tube Mn6, the source end of the NMOS tube Mn5, the drain end of the PMOS tube Mp6 and one end of the capacitor Cp2, the gate end of the NMOS tube Mn6 is connected to the resistor R6 and one end of the capacitor C14, the drain end of the NMOS tube Mn6 is connected to one end of the capacitor C15, one end of the variable capacitor Cvar4 and the b end of the inductor L2 as the output end Voscq- of the orthogonal voltage controlled oscillator, the c end of the inductor L2 is connected to the power supply voltage VDD, the a end of the inductor L2 is connected to the drain of the NMOS tube Mn5, the other end of the capacitor C14, the variable capacitor C var3, the other end of the variable capacitor Cvar3 is connected to the other end of the variable capacitor Cvar4, the gate end of the NMOS tube Mn5 is connected to the other end of the capacitor C15 and one end of the resistor R5, the other end of the resistor R5 is connected to the other end of the resistor R6, the gate end of the PMOS tube Mp6 is connected to one end of the resistor R4 and the other end of the capacitor Cp1, the source end of the PMOS tube Mp6 is connected to the source end of the PMOS tube Mp5 and the power supply voltage VDD, the gate end of the PMOS tube Mp5 is connected to one end of the resistor R3 and the other end of the capacitor Cp2, and the other end of the resistor R3 is connected to the other end of the resistor R4.

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