Command decoding circuit, memory, and electronic device
By designing a command decoding circuit for LPDDR5, dynamic clock signals are used to replace the system clock signals, the problem of high power consumption when decoding active commands in the prior art is solved, and the effect of reducing power consumption is achieved.
Patent Information
- Application Number
- CN202110811873.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-07-19
- Publication Date
- 2025-06-27
- Estimated Expiration
- 2041-07-19
AI Technical Summary
In the prior art, when decoding the active commands ACT1 and ACT2 in LPDDR5, it is necessary to rely on the system clock signal, resulting in high power consumption.
A command decoding circuit is designed, including a first decoding unit, a second decoding unit and a clock gate. The first decoding unit decodes the first command signal according to the system clock signal, and the second decoding unit decodes the second command signal according to the dynamic clock signal generated by the clock gate. The clock gate generates a dynamic clock signal after decoding the first command signal by the first decoding unit, and turns off the dynamic clock signal after decoding the second command signal by the second decoding unit.
Power consumption is reduced by avoiding continuous switching of the clock signal after decoding the second active command.
Smart Images
Figure CN115641891B_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present application relate to the field of integrated circuit technologies, and in particular, to a command decoding circuit, a memory, and an electronic device. Background Art
[0002] In various electronic devices, memory is an essential component that affects the performance of the electronic device. A commonly used memory can be SDRAM (synchronous dynamic random-access memory). During the research on SDRAM, various types of SDRAM have emerged. For example, LPDDR (low power double data rate SDRAM). In the new protocol of LPDDR5 (the fifth generation of LPDDR), two active commands, ACT1 and ACT2, are defined. The system chip sends ACT1 and ACT2 in sequence, and after being decoded, ACT1 and ACT2 are executed to perform row operations on the memory storage bank, that is, data reading or data writing.
[0003] In the prior art, when decoding ACT1 and ACT2, it is necessary to rely on the system clock signal provided by the system chip. Since the system clock signal is constantly switching between high level and low level, the power consumption is relatively high. Summary of the Invention
[0004] Embodiments of the present application provide a command decoding circuit, a memory, and an electronic device to reduce the power consumption during decoding of active commands.
[0005] In a first aspect, an embodiment of the present application provides a command decoding circuit, including:
[0006] A first decoding unit for decoding a first command signal according to a system clock signal;
[0007] A second decoding unit for decoding a second command signal according to a dynamic clock signal generated by a clock gating, where the second command signal is triggered within a preset period after the first command signal;
[0008] The clock gating is configured to generate a dynamic clock signal after the first decoding unit decodes the first command signal, and to turn off the dynamic clock signal after the second decoding unit decodes the second command signal.
[0009] Optionally, it further includes:
[0010] An enable signal generation unit for generating an enable signal according to the first command signal and the second command signal;
[0011] The clock gate is further configured to generate the dynamic clock signal or turn off the dynamic clock signal according to the enable signal and the system clock signal.
[0012] Optionally, the enable signal generation unit is further configured to generate the high-level enable signal when both the first command signal and the second command signal are at high level; or generate the low-level enable signal when the first command signal or the second command signal is at low level.
[0013] The clock gate is further configured to turn off the dynamic clock signal when the enable signal is at high level; or generate the dynamic clock signal according to the system clock signal when the enable signal is at low level.
[0014] Optionally, the enable signal generation unit is an AND gate, and is configured to determine the AND signal of the first command signal and the second command signal as the enable signal;
[0015] The clock gate is an OR gate, and is configured to determine the OR signal of the system clock signal and the enable signal as the dynamic clock signal.
[0016] Optionally, the enable signal generation unit is further configured to generate the low-level enable signal when both the first command signal and the second command signal are at high level; or generate the high-level enable signal when the first command signal or the second command signal is at low level.
[0017] The clock gate is further configured to turn off the dynamic clock signal when the enable signal is at low level; or generate the dynamic clock signal according to the system clock signal when the enable signal is at high level.
[0018] Optionally, the enable signal generation unit includes:
[0019] An AND gate, configured to determine the AND signal of the first command signal and the second command signal;
[0020] A NOT gate, configured to use the NOT signal of the AND signal as the enable signal;
[0021] The clock gate is an AND gate, and is configured to determine the AND signal of the system clock signal and the enable signal as the dynamic clock signal.
[0022] Optionally, it further includes:
[0023] A timer, configured to generate a timing signal after the first decoding unit decodes the first command signal, where the timing signal is used to indicate whether the duration between the current time and the decoding of the first command signal is greater than the preset period, and the timing signal changes over time;
[0024] The clock gate is further configured to turn off the dynamic clock signal when the duration is greater than the preset period.
[0025] Optionally, the timer is further configured to generate the timing signal according to the dynamic clock signal after the first decoding unit decodes the first command signal.
[0026] Optionally, it further includes:
[0027] An enable signal generation unit, configured to generate the enable signal according to the first command signal, the second command signal, and the timing signal;
[0028] The clock gate is further configured to generate the dynamic clock signal or turn off the dynamic clock signal according to the enable signal and the system clock signal.
[0029] Optionally, the enable signal generation unit is further configured to generate the high-level enable signal when the first command signal is at a high level and the second command signal or the timing signal is at a high level; or generate the low-level enable signal when the first command signal, or the second command signal, or the timing signal is at a low level;
[0030] The clock gate is further configured to turn off the dynamic clock signal when the enable signal is at a high level; or generate the dynamic clock signal according to the system clock signal when the enable signal is at a low level.
[0031] Optionally, the enable signal generation unit includes:
[0032] An OR gate, configured to determine the OR signal of the second command signal and the timing signal;
[0033] A first AND gate, configured to determine the AND signal between the first command signal and the AND signal output by the second AND gate;
[0034] A second AND gate, configured to determine the AND signal between the OR signal and the AND signal output by the first AND gate, where the AND signal output by the first AND gate is the enable signal;
[0035] The clock gate is an OR gate, configured to determine the OR signal of the system clock signal and the enable signal as the dynamic clock signal.
[0036] Optionally, the enable signal generation unit is further configured to generate the low-level enable signal when the first command signal is at a high level and the second command signal or the timing signal is at a high level; or, generate the high-level enable signal when the first command signal, or the second command signal, or the timing signal is at a low level;
[0037] The clock gate is further configured to turn off the dynamic clock signal when the enable signal is at a low level; or, generate the dynamic clock signal according to the system clock signal when the enable signal is at a high level.
[0038] Optionally, the enable signal generation unit includes:
[0039] An OR gate for determining the OR signal of the second command signal and the timing signal;
[0040] A first AND gate for determining the AND signal between the first command signal and the AND signal output by the second AND gate;
[0041] A second AND gate for determining the AND signal between the OR signal and the AND signal output by the first AND gate;
[0042] A NOT gate for determining the inverted signal of the AND signal output by the first AND gate as the enable signal;
[0043] The clock gate is an AND gate for determining the AND signal between the system clock signal and the enable signal as the dynamic clock signal.
[0044] Optionally, when the timing signal is at a low level, it represents that the duration between the current time and decoding the first command signal is less than or equal to the preset period; when the timing signal is at a high level, it represents that the duration between the current time and decoding the first command signal is greater than the preset period.
[0045] Optionally, the preset period is 8 cycles of the system clock signal.
[0046] Optionally, the first command signal is used to trigger the second command signal, and the second command signal is used to perform a row operation on the storage group.
[0047] In a second aspect, an embodiment of the present application further provides a memory, including:
[0048] The command decoding circuit, system chip, and storage group as described in the first aspect;
[0049] The system chip is configured to generate the system clock signal, and trigger the first command signal and the second command signal;
[0050] The second command signal is used to operate on the storage group.
[0051] Optionally, the memory is a low-power double data rate synchronous dynamic random access memory (LPDDR).
[0052] In a third aspect, an embodiment of the present application further provides an electronic device, including the memory described in the second aspect.
[0053] The command decoding circuit, memory, and electronic device provided in the embodiments of the present application. The circuit includes: a first decoding unit, a second decoding unit, and a clock gate. Among them, the first decoding unit is configured to decode a first command signal according to a system clock signal; the second decoding unit is configured to decode a second command signal according to a dynamic clock signal generated by the clock gate, and the second command signal is triggered within a preset period after the first command signal; the clock gate is configured to generate a dynamic clock signal after the first decoding unit decodes the first command signal, and turn off the dynamic clock signal after the second decoding unit decodes the second command signal. The embodiments of the present application can avoid the clock signal from continuously switching between high and low levels after decoding the second active command. In this way, power consumption can be reduced. Description of the Drawings
[0054] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.
[0055] Figure 1 Exemplarily shows a schematic diagram of the process of performing a row operation on a storage group in the prior art;
[0056] Figures 2 to 6 Exemplarily shows five structural schematic diagrams of the command decoding circuit provided in the embodiments of the present application;
[0057] Figure 7 Exemplarily shows a structural schematic diagram of a memory provided in the embodiments of the present application. Detailed Embodiments
[0058] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the following will clearly and completely describe the technical solutions in the embodiments of this application with reference to the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are some, but not all, of the embodiments of this application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in this application without creative efforts shall fall within the scope of protection of the embodiments of this application.
[0059] The embodiments of this application are applicable to the decoding process of active commands for memory data reading and writing. After decoding, the active commands can be used to read and write data to the memory. Among them, after the continuous evolution of SDRAM, LPDDR emerged.
[0060] In LPDDR5, active commands are divided into first active commands and second active commands. The first active command is used to keep the following signals at a high level after the rising edge of the system clock signal arrives: CS (chip select) signal, the first CA (command address) signal CA0, the second CA signal CA1, and the third CA signal CA2. The second active command is used to keep the CS signal at a high level, CA0 at a high level, CA1 at a high level, and CA2 at a low level after the rising edge of the system clock signal arrives. The second active command is triggered within 8 clock cycles after the first active command is triggered. If the second active command is not triggered within 8 clock cycles, it is determined that a timeout has occurred. After that, the second active command is no longer waited for, but the next round of the first active command is waited for. Within these 8 clock cycles, only CA signals, write signals, read signals, masked write signals, MRR, precharge signals, memory bank update signals, etc. can be triggered.
[0061] Figure 1 Exemplarily shows a schematic diagram of the process of performing a row operation on a memory bank in the prior art. Refer to Figure 1 As shown, the controller includes a decoding circuit, which can decode the command address signal according to the system clock signal to obtain the first active command ACT1 or the second active command ACT2. Among them, the system clock signal is provided by the system chip. The decoded second command signal can be used to perform a row operation on the memory bank, that is, data reading or data writing.
[0062] However, since the system clock signal is always constantly switching back and forth between a high level and a low level, the power consumption of the decoding circuit is relatively high.
[0063] To solve the above problems, it can be considered to avoid the system clock signal constantly switching back and forth between a high level and a low level when decoding is not required.
[0064] As can be seen from the above definitions of the first active command and the second active command, the second active command is usually triggered within 8 clock cycles after the first active command is triggered. When the second active command is triggered, the command representing a data read / write ends, and it is necessary to wait for the next first active command. Thus, after decoding the second active command, it is possible to avoid the clock signal continuously switching between high and low levels. In this way, power consumption can be reduced.
[0065] Figure 2 An exemplary structural diagram of the command decoding circuit 100 provided by an embodiment of the present application is shown. Refer to Figure 2 As shown, the command decoding circuit 100 includes a first decoding unit 101, a second decoding unit 102, and a clock gate 103.
[0066] Among them, the first decoding unit 101 is used to decode the first command signal according to the system clock signal.
[0067] The second decoding unit 102 is used to decode the second command signal according to the dynamic clock signal generated by the clock gate 103, and the second command signal is triggered within a preset period after the first command signal.
[0068] The clock gate 103 is used to generate a dynamic clock signal after the first decoding unit 101 decodes the first command signal, and to turn off the dynamic clock signal after the second decoding unit 102 decodes the second command signal. It can be seen that the clock gate 103 also needs to generate a dynamic clock signal in combination with the system clock signal.
[0069] Among them, the first decoding unit 101 and the second decoding unit 102 are circuits that decode the first command signal and the second command signal from the CA signal. Specifically, the first command signal and the second command signal are determined according to the CA signal sent by each command address line.
[0070] The first command signal is the signal corresponding to the aforementioned first active command, and the second command signal is the signal of the aforementioned second active command. The first command signal is used to trigger the second command signal, and the second command signal is used to perform a row operation on the storage group, and the operation includes but is not limited to: reading data from the storage group and writing data to the storage group.
[0071] It can be seen that when the first decoding unit 101 decodes the first command signal, it is based on the system clock signal. Since the system clock signal is constantly switching, the decoding of the first decoding unit 101 cannot achieve power saving.
[0072] When the second decoding unit 102 decodes the second command signal, it is based on the dynamic clock signal generated by the clock gate 103. Before decoding the second command signal after decoding the first command signal, the dynamic clock signal is the same as the system clock signal and also continuously switches between high and low levels. This dynamic clock signal is turned off after the second decoding unit 102 decodes the second command signal. That is, after that, the dynamic clock signal does not continuously switch between high and low levels but always remains at a high level or a low level. In this way, the power consumption during the decoding by the second decoding unit 102 is reduced.
[0073] To implement the above relationships among the first command signal, the second command signal, and the dynamic clock signal, the above command decoding circuit further includes:
[0074] An enable signal generation unit 104 for generating an enable signal according to the first command signal and the second command signal.
[0075] Based on the above enable signal generation unit 104, the above clock gate 103 is further configured to generate a dynamic clock signal or turn off the dynamic clock signal according to the enable signal and the system clock signal.
[0076] Specifically, when both the first command signal and the second command signal are at a high level, that is, when the first command signal is decoded and the second command signal is decoded, the dynamic clock signal can be turned off. Or, when the first command signal or the second command signal is at a low level, that is, when the first command signal is not decoded or the first command signal is decoded but the second command signal is not decoded, the dynamic clock signal can be generated at this time.
[0077] To implement the relationships among the above first command signal, second command signal, and dynamic clock signal, the enable signal can be at a high level or a low level. The following will be described in detail through two examples.
[0078] In the first example, the above enable signal generation unit 104 is specifically configured to generate a high-level enable signal when both the first command signal and the second command signal are at a high level; or generate a low-level enable signal when the first command signal or the second command signal is at a low level.
[0079] Correspondingly, the above clock gate 103 is configured to turn off the dynamic clock signal when the enable signal is at a high level; or generate a dynamic clock signal according to the system clock signal when the enable signal is at a low level.
[0080] To implement the above relationships among the first command signal, the second command signal, and the enable signal, referring to Figure 3 As shown, the above enable signal generation unit 104 can be an AND gate.
[0081] Among them, the above AND gate is used to determine the AND signal of the first command signal and the second command signal. That is, when the first command signal and the second command signal are at a high level, the enable signal is at a high level; when the first command signal or the second command signal is at a low level, the enable signal is at a low level.
[0082] AND Figure 3 corresponds to the shown enable signal generation unit 104, refer to Figure 3 As shown, the above clock gate 103 can be an OR gate, which is used to determine the OR signal of the system clock signal and the enable signal as the dynamic clock signal. That is, when the system clock signal or the enable signal is at a high level, the OR signal output by the OR gate is at a high level, and the dynamic clock signal is at a high level; when both the system clock signal and the enable signal are at a low level, the OR signal output by the OR gate is at a low level, and the dynamic clock signal is at a low level. In this case, when the enable signal is at a low level, since the system clock signal switches between a high level and a low level, the OR signal of it and the low level, that is, the output dynamic clock signal, also switches with the switching of the system clock signal; when the enable signal is at a high level, since the OR signal of the system clock signal and the high level, that is, the output dynamic clock signal does not switch, the dynamic clock signal is turned off.
[0083] In the second example, the above enable signal generation unit 104 is specifically configured to generate a low-level enable signal when both the first command signal and the second command signal are at a high level; or, generate a high-level enable signal when the first command signal or the second command signal is at a low level.
[0084] Correspondingly, the above clock gate 103 is specifically configured to turn off the dynamic clock signal according to when the enable signal is at a low level; or, generate a dynamic clock signal according to the system clock signal when the enable signal is at a high level.
[0085] To implement the above relationship between the first command signal, the second command signal and the enable signal, the above enable signal generation unit 104 may include an AND gate and a NOT gate. Refer to Figure 4 As shown, the AND gate and the NOT gate are combined into a NAND gate.
[0086] Among them, the AND gate is used to determine the AND signal of the first command signal and the second command signal. That is, when both the first command signal and the second command signal are at a high level, the AND signal output by the AND gate is at a high level; when the first command signal or the second command signal is at a low level, the AND signal output by the AND gate is at a low level.
[0087] The NOT gate is used to use the inverted signal of the AND signal as the enable signal. That is to say, when the AND signal output by the AND gate is at a high level, the inverted signal output by the NOT gate is at a low level, and the enable signal is at a low level; when the AND signal output by the AND gate is at a low level, the inverted signal output by the NOT gate is at a high level, and the enable signal is at a high level.
[0088] AND Figure 4 corresponding to the enable signal generation unit 104 shown in the figure, refer to Figure 4 As shown in the figure, the above clock gate 103 is an AND gate, which is used to determine the AND signal of the system clock signal and the enable signal as the dynamic clock signal. That is to say, when both the system clock signal and the enable signal are at a high level, the dynamic clock signal output by the clock gate 103 is at a high level; when the system clock signal or the enable signal is at a low level, the dynamic clock signal output by the clock gate 103 is at a low level. In this case, when the enable signal is at a high level, its AND signal with the system clock signal, that is, the output dynamic clock signal, switches with the switching of the system clock signal; when the enable signal is at a low level, its AND signal with the system clock signal, that is, the output dynamic clock signal is always at a low level, so that the dynamic clock signal is turned off.
[0089] Optionally, the above command decoding circuit may further include: a timer 105, which is used to generate a timing signal after the first decoding unit 101 decodes the first command signal. The timing signal is used to indicate whether the duration between the current time and the decoding of the first command signal is greater than a preset period, and the timing signal changes over time. Correspondingly, the above clock gate 103 is further used to turn off the dynamic clock signal when the duration between the current time and the decoding of the first command signal is greater than the preset period, or to generate a dynamic clock signal when the duration between the current time and the decoding of the first command signal is less than or equal to the preset period.
[0090] Wherein, the preset period is 8 clock cycles of the system clock signal defined in the new protocol of LPDDR5.
[0091] The timing signal may be a signal with different levels before and after reaching the preset period after decoding the first command signal. Two typical timing signals are illustrated below.
[0092] First, before reaching the preset period after decoding the first command signal, that is, when the duration between the current time and the decoding of the first command signal is less than or equal to the preset period, the above timing signal may be at a high level; after reaching the preset period after decoding the first command signal, that is, when the duration between the current time and the decoding of the first command signal is greater than the preset period, the above timing signal is at a low level.
[0093] Second, before reaching the preset period after decoding the first command signal, that is, when the duration between the current time and the decoding of the first command signal is less than or equal to the preset period, the above timing signal can be at a low level; after reaching the preset period after decoding the first command signal, that is, when the duration between the current time and the decoding of the first command signal is greater than the preset period, the above timing signal is at a high level. Below, the second case is taken as an example to illustrate the relationship between the timing signal, the first command signal, the second command signal, and the dynamic clock signal.
[0094] In the embodiment of the present application, within 8 clock cycles after decoding the first command signal, if the second command signal is not triggered, it is determined as a timeout. At this time, the waiting for the second command signal is no longer continued, and the dynamic clock signal is turned off so that the dynamic clock signal is always at a high level or a low level. In this way, the power consumption can be further reduced.
[0095] Optionally, the above timer 105 is further configured to generate a timing signal according to the dynamic clock signal after the first decoding unit 101 decodes the first command signal.
[0096] It can be understood that after decoding the first command signal, the dynamic clock signal, like the system clock signal, continuously switches between a high level and a low level. At this time, the timer 105 needs to generate a timing signal according to the dynamic clock signal that continuously switches between a high level and a low level to wait for the second command signal or a timeout. After decoding the second command signal or a timeout, since the dynamic clock signal is turned off, the timer 105 no longer generates a timing signal, and in this way, the power consumption can be further reduced.
[0097] In summary, after decoding the first command signal, the clock gate 103 generates a dynamic clock signal; after decoding the second command signal or when the timing signal represents a timeout, the clock gate 103 turns off the dynamic clock signal.
[0098] To implement the above relationships among the first command signal, the second command signal, the timing signal, and the dynamic clock signal, the above command decoding circuit further includes:
[0099] An enable signal generation unit 104, configured to generate an enable signal according to the first command signal, the second command signal, and the timing signal.
[0100] Based on the above enable signal generation unit 104, the above clock gate 103 is further configured to generate a dynamic clock signal or turn off the dynamic clock signal according to the enable signal and the system clock signal.
[0101] Specifically, when the first command signal is at a high level and the second command signal or the timing signal is at a high level, that is, when the first command signal is decoded and the second command signal is decoded, or when the second command signal is not triggered within 8 clock cycles after the first command signal is decoded, the dynamic clock signal is turned off. Or, when the first command signal, or the second command signal, or the timing signal is at a low level, that is, when the first decoding unit is decoding, or the second decoding unit is decoding, a dynamic clock signal is generated so that the first decoding unit or the second decoding unit can perform decoding according to the dynamic clock signal.
[0102] To implement the relationship between the first command signal, the second command signal, the timing signal, and the dynamic clock signal, the enable signal can be at a high level or a low level. Two examples are described in detail below.
[0103] In the first example, the enable signal generation unit 104 is specifically configured to generate a high-level enable signal when the first command signal is at a high level and the second command signal or the timing signal is at a high level; or, to generate a low-level enable signal when the first command signal, or the second command signal, or the timing signal is at a low level.
[0104] Correspondingly, the clock gate 103 is configured to turn off the dynamic clock signal according to the enable signal when the enable signal is at a high level; or, to generate a dynamic clock signal according to the system clock signal when the enable signal is at a low level.
[0105] To implement the above relationship between the first command signal, the second command signal, and the timing signal and the enable signal, referring to Figure 5 As shown, the enable signal generation unit 104 may include an OR gate, a first AND gate, and a second AND gate.
[0106] Among them, the OR gate is used to determine the OR signal of the second command signal and the timing signal. That is, when at least one of the second command signal and the timing signal is at a high level, the OR signal is at a high level; when both the second command signal and the timing signal are at a low level, the OR signal is at a low level.
[0107] The first AND gate is used to determine the AND signal between the first command signal and the AND signal output by the second AND gate, and the AND signal output by the first AND gate is the enable signal. That is, when both the first command signal and the AND signal output by the second AND gate are at a high level, the AND signal output by the first AND gate is at a high level, and the enable signal is at a high level; when the first command signal or the AND signal output by the second AND gate is at a low level, the AND signal output by the first AND gate is at a low level, and the enable signal is at a low level.
[0108] The second AND gate is used to determine the AND signal between the OR signal and the AND signal output by the first AND gate. That is to say, when both the OR signal output by the OR gate and the AND signal output by the first AND gate are at a high level, the AND signal output by the second AND gate is at a high level; when either the OR signal output by the OR gate or the AND signal output by the first AND gate is at a low level, the AND signal output by the second AND gate is at a low level.
[0109] AND Figure 5 corresponds to the enabling signal generation unit 104 shown, refer to Figure 5 As shown, the above clock gate 103 can be an OR gate, which is used to determine the OR signal of the system clock signal and the enabling signal as the dynamic clock signal. That is to say, when either the system clock signal or the enabling signal is at a high level, the OR signal output by the OR gate is at a high level, and the dynamic clock signal is at a high level; when both the system clock signal and the enabling signal are at a low level, the OR signal output by the OR gate is at a low level, and the dynamic clock signal is at a low level. In this case, when the enabling signal is at a low level, since the system clock signal switches between a high level and a low level, the OR signal of it and the low level, that is, the output dynamic clock signal, also switches with the switching of the system clock signal; when the enabling signal is at a high level, since the OR signal of the system clock signal and the high level, that is, the output dynamic clock signal does not switch, the dynamic clock signal is turned off.
[0110] In the second example, the above enabling signal generation unit 104 is specifically configured to generate a low-level enabling signal when the first command signal is at a high level and the second command signal or the timing signal is at a high level; or, to generate a high-level enabling signal when the first command signal, or the second command signal, or the timing signal is at a low level.
[0111] Correspondingly, the above clock gate 103 is specifically configured to turn off the dynamic clock signal when the enabling signal is at a low level; or, to generate a dynamic clock signal according to the system clock signal when the enabling signal is at a high level.
[0112] In order to implement the above relationship between the first command signal, the second command signal, the timing signal and the enabling signal, refer to Figure 6 As shown, the above enabling signal generation unit 104 may include an OR gate, a first AND gate, a second AND gate and a NOT gate.
[0113] Among them, the above OR gate is used to determine the OR signal of the second command signal and the timing signal. That is to say, when at least one of the second command signal and the timing signal is at a high level, the OR signal is at a high level; when both the second command signal and the timing signal are at a low level, the OR signal is at a low level.
[0114] The first AND gate is used to determine the AND signal between the first command signal and the AND signal output by the second AND gate. That is, when both the first command signal and the AND signal output by the second AND gate are at high level, the AND signal output by the first AND gate is at high level; when either the first command signal or the AND signal output by the second AND gate is at low level, the AND signal output by the first AND gate is at low level.
[0115] The second AND gate is used to determine the AND signal between the OR signal and the AND signal output by the first AND gate. That is, when both the OR signal output by the OR gate and the AND signal output by the first AND gate are at high level, the AND signal output by the second AND gate is at high level; when either the OR signal output by the OR gate or the AND signal output by the first AND gate is at low level, the AND signal output by the second AND gate is at low level.
[0116] The NOT gate is used to invert the AND signal output by the first AND gate, and this inverted signal is used as the enable signal.
[0117] AND Figure 6 Corresponding to the enable signal generation unit 104 shown, refer to Figure 6 As shown, the above clock gate 103 is an AND gate, which is used to determine the AND signal of the system clock signal and the enable signal as the dynamic clock signal. That is, when both the system clock signal and the enable signal are at high level, the dynamic clock signal output by the clock gate 103 is at high level; when either the system clock signal or the enable signal is at low level, the dynamic clock signal output by the clock gate 103 is at low level. In this case, when the enable signal is at high level, its AND signal with the system clock signal, that is, the output dynamic clock signal, switches with the switching of the system clock signal; when the enable signal is at low level, its AND signal with the system clock signal, that is, the output dynamic clock signal is always at low level, so that the dynamic clock signal is turned off.
[0118] Figure 7 An exemplary structural schematic diagram of a memory provided by an embodiment of the present application is shown, including: a command decoding circuit 302, a system chip 301, and a storage bank 303.
[0119] Among them, the system chip 301 is used to generate a system clock signal, and trigger a first command signal and a second command signal, and the second command signal is used to operate on the storage bank 303.
[0120] The command decoding circuit 302 is used to decode the first command signal and the second command signal.
[0121] Optionally, the above memory is LPDDR (low power double data rate SDRAM, low-power double-data-rate synchronous dynamic random access memory).
[0122] An embodiment of the present application further provides an electronic device, including the aforementioned memory.
[0123] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the present application, and are not intended to limit them; although the embodiments of the present application have been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.
Claims
1. A command decoding circuit, characterized in that, Including: A first decoding unit for decoding a first command signal according to a system clock signal; A second decoding unit for decoding a second command signal according to a dynamic clock signal generated by a clock gate, where the second command signal is triggered within a preset period after the first command signal; The clock gate is used to generate the dynamic clock signal after the first decoding unit decodes the first command signal, and to turn off the dynamic clock signal after the second decoding unit decodes the second command signal.
2. The command decoding circuit according to claim 1, wherein Further including: An enable signal generation unit for generating an enable signal according to the first command signal and the second command signal; The clock gate is further used to generate the dynamic clock signal or turn off the dynamic clock signal according to the enable signal and the system clock signal.
3. The command decoding circuit according to claim 2, wherein: The enable signal generation unit is further used to generate the high-level enable signal when both the first command signal and the second command signal are high level; or, to generate the low-level enable signal when the first command signal or the second command signal is low level; The clock gate is further used to turn off the dynamic clock signal when the enable signal is high level; or, to generate the dynamic clock signal according to the system clock signal when the enable signal is low level.
4. The command decoding circuit according to claim 3, wherein: The enable signal generation unit is an AND gate for determining the AND signal of the first command signal and the second command signal as the enable signal; The clock gate is an OR gate for determining the OR signal of the system clock signal and the enable signal as the dynamic clock signal.
5. The command decoding circuit according to claim 2, wherein: The enable signal generation unit is further used to generate the low-level enable signal when both the first command signal and the second command signal are high level; or, to generate the high-level enable signal when the first command signal or the second command signal is low level; The clock gate is further used to turn off the dynamic clock signal when the enable signal is low level; or, to generate the dynamic clock signal according to the system clock signal when the enable signal is high level.
6. The command decoding circuit according to claim 5, wherein: The enable signal generation unit includes: An AND gate for determining the AND signal of the first command signal and the second command signal; An inverter for using the inverted signal of the AND signal as the enable signal; The clock gate is an AND gate for determining the AND signal of the system clock signal and the enable signal as the dynamic clock signal.
7. The command decoding circuit according to claim 6, wherein Further including: A timer for generating a timing signal after the first decoding unit decodes the first command signal, where the timing signal is used to indicate whether the duration between the current time and the decoding of the first command signal is greater than the preset period, and the timing signal changes over time; The clock gate is further configured to turn off the dynamic clock signal when it is greater than a preset period.
8. The command decoding circuit according to claim 7, wherein The timer is further configured to generate the timing signal according to the dynamic clock signal after the first decoding unit decodes the first command signal.
9. The command decoding circuit according to claim 8, characterized in that, It further includes: An enable signal generating unit, configured to generate the enable signal according to the first command signal, the second command signal, and the timing signal; The clock gate is further configured to generate the dynamic clock signal or turn off the dynamic clock signal according to the enable signal and the system clock signal.
10. The command decoding circuit according to claim 9, wherein The enable signal generating unit is further configured to generate the high-level enable signal when the first command signal is high level and the second command signal or the timing signal is high level; or generate the low-level enable signal when the first command signal, or the second command signal, or the timing signal is low level; The clock gate is further configured to turn off the dynamic clock signal when the enable signal is high level; or generate the dynamic clock signal according to the system clock signal when the enable signal is low level.
11. The command decoding circuit according to claim 10, wherein The enable signal generating unit includes: An OR gate, configured to determine the OR signal of the second command signal and the timing signal; A first AND gate, configured to determine the AND signal between the first command signal and the AND signal output by the second AND gate; A second AND gate, configured to determine the AND signal between the OR signal and the AND signal output by the first AND gate, and the AND signal output by the first AND gate is the enable signal; The clock gate is an OR gate, configured to determine the OR signal of the system clock signal and the enable signal as the dynamic clock signal.
12. The command decoding circuit according to claim 9, wherein The enable signal generating unit is further configured to generate the low-level enable signal when the first command signal is high level and the second command signal or the timing signal is high level; or generate the high-level enable signal when the first command signal, or the second command signal, or the timing signal is low level; The clock gate is further configured to turn off the dynamic clock signal when the enable signal is low level; or generate the dynamic clock signal according to the system clock signal when the enable signal is high level.
13. The command decoding circuit according to claim 12, characterized in that, The enable signal generating unit includes: An OR gate, configured to determine the OR signal of the second command signal and the timing signal; A first AND gate, configured to determine the AND signal between the first command signal and the AND signal output by the second AND gate; A second AND gate, configured to determine the AND signal between the OR signal and the AND signal output by the first AND gate; A NOT gate, configured to determine the NOT signal of the AND signal output by the first AND gate as the enable signal; The clock gate is an AND gate, configured to determine the AND signal of the system clock signal and the enable signal as the dynamic clock signal.
14. The command decoding circuit according to claim 7, characterized in that, When the timing signal is at a low level, it represents that the duration between the current time and decoding the first command signal is less than or equal to the preset period; when the timing signal is at a high level, it represents that the duration between the current time and decoding the first command signal is greater than the preset period.
15. The command decoding circuit according to any one of claims 1 to 14, characterized in that, The preset period is 8 periods of the system clock signal.
16. The command decoding circuit according to any one of claims 1 to 14, characterized in that, The first command signal is used to trigger the second command signal, and the second command signal is used to perform a row operation on the memory bank group.
17. A memory, characterized in that, Comprising: The command decoding circuit, system chip and memory bank group according to any one of claims 1 to 16; The system chip is used to generate the system clock signal, and to trigger the first command signal and the second command signal; The second command signal is used to operate on the memory bank group.
18. The memory according to claim 17, wherein The memory is a low-power double data rate synchronous dynamic random access memory LPDDR.
19. An electronic device, characterized in that, Comprising the memory according to claim 17 or 18.
Citation Information
Patent Citations
Semiconductor device and semiconductor system including the same
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Semiconductor devices
US20200302980A1