A voltage comparator with adjustable hysteresis voltage

Abstract

The present invention discloses a voltage comparator with adjustable hysteresis voltage, belonging to the field of electronic circuits, which includes NMOS transistors M0 to M13, a hysteresis voltage adjustment circuit, and inverters INV1 and INV2; one output terminal a of the hysteresis voltage adjustment circuit is simultaneously connected to the drain terminal of NMOS transistor M6, the source terminal of NMOS transistor M8, and the source terminal of NMOS transistor M3; the other output terminal b of the hysteresis voltage adjustment circuit is simultaneously connected to the drain terminal of NMOS transistor M7, the source terminal of NMOS transistor M9, and the source terminal of NMOS transistor M4; the input terminal of inverter INV1 is connected between the drain terminal of NMOS transistor M9 and the source terminal of NMOS transistor M11, and the output terminal is connected to the input terminal of inverter INV2; the enable terminal EN of the hysteresis voltage adjustment circuit is connected between the output terminal of inverter INV1 and the input terminal of inverter INV2. The present invention can provide different hysteresis voltages according to the noise energy in a complex environment, thereby resisting noise and achieving correct level actions and signal judgments.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and particularly relates to a voltage comparator with adjustable hysteresis voltage. Background Art

[0002] It is difficult to make the hysteresis voltages of voltage comparators manufactured under different processes consistent. In some cases, the smaller the hysteresis voltage is, the better. In some other cases, an adjustable hysteresis voltage is required to resist the varying noise energy in a complex environment.

[0003] Therefore, there is an urgent need for a voltage comparator with variable hysteresis voltage to meet the above requirements. Summary of the Invention

[0004] The purpose of the present invention is to provide a voltage comparator with adjustable hysteresis voltage to solve the problems in the background art.

[0005] To solve the above technical problems, the present invention provides a voltage comparator with adjustable hysteresis voltage, which includes NMOS transistors M0 to M13, a hysteresis voltage adjustment circuit, and inverters INV1 and INV2;

[0006] The drain terminal of NMOS transistor M0 is simultaneously connected to the source terminals of NMOS transistors M1 and M2; the source terminal of NMOS transistor M5 is simultaneously connected to the drain terminals of NMOS transistors M3 and M4; the source terminal of NMOS transistor M0 is connected to the power supply voltage VDD, and the drain terminal of NMOS transistor M5 is grounded;

[0007] The source terminal of NMOS transistor M6 is connected to the power supply voltage VDD, the drain terminal is connected to the source terminal of NMOS transistor M8, the drain terminal of NMOS transistor M8 is connected to the source terminal of NMOS transistor M10, the drain terminal of NMOS transistor M10 is connected to the source terminal of NMOS transistor M12, and the drain terminal of NMOS transistor M12 is grounded;

[0008] The source terminal of NMOS transistor M7 is connected to the power supply voltage VDD, the drain terminal is connected to the source terminal of NMOS transistor M9, the drain terminal of NMOS transistor M9 is connected to the source terminal of NMOS transistor M11, the drain terminal of NMOS transistor M11 is connected to the source terminal of NMOS transistor M13, and the drain terminal of NMOS transistor M13 is grounded;

[0009] The drain terminal of NMOS transistor M1 is simultaneously connected to the drain terminals of NMOS transistors M11 and M13 and the source terminal of NMOS transistor M13, and the drain terminal of NMOS transistor M2 is simultaneously connected to the drain terminals of NMOS transistors M10 and M12 and the source terminal of NMOS transistor M12;

[0010] One output terminal a of the hysteresis voltage regulation circuit is simultaneously connected to the drain terminal of NMOS transistor M6, the source terminal of NMOS transistor M8, and the source terminal of NMOS transistor M3; the other output terminal b of the hysteresis voltage regulation circuit is simultaneously connected to the drain terminal of NMOS transistor M7, the source terminal of NMOS transistor M9, and the source terminal of NMOS transistor M4.

[0011] The input terminal of inverter INV1 is connected between the drain terminal of NMOS transistor M9 and the source terminal of NMOS transistor M11, and the output terminal is connected to the input terminal of inverter INV2; the enable terminal EN of the hysteresis voltage regulation circuit is connected between the output terminal of inverter INV1 and the input terminal of inverter INV2.

[0012] In one embodiment, the gate terminals of NMOS transistors M1 and M3 are both connected to the positive input voltage terminal VM, and the gate terminals of NMOS transistors M2 and M4 are both connected to the negative input voltage terminal VP.

[0013] The gate terminals of NMOS transistors M0, M6, and M7 are all connected to the first bias voltage Bias1; the gate terminals of NMOS transistors M5, M12, and M13 are all connected to the second bias voltage Bias2; the gate terminals of NMOS transistors M8 and M9 are both connected to the third bias voltage Bias3; the gate terminals of NMOS transistors M10 and M1 are both connected to the fourth bias voltage Bias4.

[0014] In one embodiment, the first bias voltage Bias1, the second bias voltage Bias2, the third bias voltage Bias3, and the fourth bias voltage Bias4 are generated by a bias voltage generation circuit CMP Bias to provide correct bias for each tail transistor so that it is in the correct state.

[0015] In one embodiment, the hysteresis voltage regulation circuit has n stages, and each stage has the same structure, and respectively includes a zero-th NMOS transistor, a first NMOS transistor, a second NMOS transistor, a first NAND gate, and a second NAND gate.

[0016] The drain terminal of the zero-th NMOS transistor is simultaneously connected to the source terminals of the first NMOS transistor and the second NMOS transistor. The gate terminal of the first NMOS transistor is connected to the output terminal of the first NAND gate, and the drain terminal is connected to one output terminal a of the hysteresis voltage regulation circuit; the gate terminal of the second NMOS transistor is connected to the output terminal of the second NAND gate, and the drain terminal is connected to the other output terminal b of the hysteresis voltage regulation circuit.

[0017] One of the input terminals of the first NAND gate and the second NAND gate in each stage is connected to the enable terminal EN of the hysteresis voltage regulation circuit; the source terminals of the zero-th NMOS transistors in each stage are all connected to the power supply voltage VDD, and the gate terminals are all connected to the first bias voltage Bias1.

[0018] In one embodiment, the NMOS transistors M0, M5, M6, M7, M12, M13 have the same size as the zero-th NMOS transistor in each stage of the hysteresis voltage regulation circuit, and their function is to provide a suitable current path.

[0019] In one embodiment, the NMOS transistors M8 and M9 have the same size as the first NMOS transistor and the second NMOS transistor in each stage of the hysteresis voltage regulation circuit.

[0020] In one embodiment, the NMOS transistors M10 and M11 have the same size to have sufficient hysteresis voltage regulation margin.

[0021] In one embodiment, the size of the NMOS transistor M8 is more than 3n times that of the NMOS transistor MM10, and the number of parallel NMOS transistors M8 is more than 3n times that of the NMOS transistor MM10.

[0022] A voltage comparator with adjustable hysteresis voltage provided by the present invention can provide different hysteresis voltages according to the noise energy in a complex environment, so as to resist noise and achieve correct level actions and signal judgments. Description of the Drawings

[0023] Figure 1 is a schematic structural diagram of a voltage comparator with adjustable hysteresis voltage provided by the present invention;

[0024] Figure 2 is a schematic structural diagram of the hysteresis voltage regulation circuit;

[0025] Figure 3 is a schematic diagram of the output result of the hysteresis voltage regulation circuit. Detailed Embodiments

[0026] The following further describes in detail a voltage comparator with adjustable hysteresis voltage proposed by the present invention in conjunction with the drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0027] The present invention provides a voltage comparator with adjustable hysteresis voltage, which can adjust the hysteresis voltage in multiple stages to achieve the purpose of resisting the changing noise in the environment.

[0028] The voltage comparator structure with adjustable hysteresis voltage provided by the present invention is as shown in Figure 1 Figure 1, and includes NMOS transistors M0 to M13, a hysteresis voltage adjustment circuit, and inverters INV1 and INV2; the drain terminal of NMOS transistor M0 is simultaneously connected to the source terminals of NMOS transistors M1 and M2; the source terminal of NMOS transistor M5 is simultaneously connected to the drain terminals of NMOS transistors M3 and M4; the source terminal of NMOS transistor M0 is connected to the power supply voltage VDD, and the drain terminal of NMOS transistor M5 is grounded. The source terminal of NMOS transistor M6 is connected to the power supply voltage VDD, the drain terminal is connected to the source terminal of NMOS transistor M8, the drain terminal of NMOS transistor M8 is connected to the source terminal of NMOS transistor M10, the drain terminal of NMOS transistor M10 is connected to the source terminal of NMOS transistor M12, and the drain terminal of NMOS transistor M12 is grounded. The source terminal of NMOS transistor M7 is connected to the power supply voltage VDD, the drain terminal is connected to the source terminal of NMOS transistor M9, the drain terminal of NMOS transistor M9 is connected to the source terminal of NMOS transistor M11, the drain terminal of NMOS transistor M11 is connected to the source terminal of NMOS transistor M13, and the drain terminal of NMOS transistor M13 is grounded. The drain terminal of NMOS transistor M1 is simultaneously connected to the drain terminals of NMOS transistors M11 and M13 and the source terminal of NMOS transistor M13, and the drain terminal of NMOS transistor M2 is simultaneously connected to the drain terminals of NMOS transistors M10 and M12 and the source terminal of NMOS transistor M12.

[0029] One output terminal a of the hysteresis voltage adjustment circuit is simultaneously connected to the drain terminal of NMOS transistor M6, the source terminal of NMOS transistor M8, and the source terminal of NMOS transistor M3; the other output terminal b of the hysteresis voltage adjustment circuit is simultaneously connected to the drain terminal of NMOS transistor M7, the source terminal of NMOS transistor M9, and the source terminal of NMOS transistor M4. The gate terminals of NMOS transistors M1 and M3 are both connected to the positive input voltage terminal VM, and the gate terminals of NMOS transistors M2 and M4 are both connected to the negative input voltage terminal VP. The gate terminals of NMOS transistors M0, M6, and M7 are all connected to the first bias voltage Bias1; the gate terminals of NMOS transistors M5, M12, and M13 are all connected to the second bias voltage Bias2; the gate terminals of NMOS transistors M8 and M9 are both connected to the third bias voltage Bias3; the gate terminals of NMOS transistors M10 and M11 are both connected to the fourth bias voltage Bias4. The first bias voltage Bias1, the second bias voltage Bias2, the third bias voltage Bias3, and the fourth bias voltage Bias4 are generated by a bias voltage generation circuit CMP Bias to provide correct bias for each tail transistor and make it in the correct state.

[0030] The input terminal of the inverter INV1 is connected between the drain terminal of the NMOS transistor M9 and the source terminal of the NMOS transistor M11, and the output terminal is connected to the input terminal of the inverter INV2; the enable terminal EN of the hysteresis voltage regulating circuit is connected between the output terminal of the inverter INV1 and the input terminal of the inverter INV2.

[0031] The structure of the hysteresis voltage regulating circuit is as Figure 2 shown, with n stages, and each stage includes three NMOS transistors and two NAND gates. Please continue to refer to Figure 2 , in the 0th stage, the drain terminal of the NMOS transistor N00 is simultaneously connected to the source terminals of the NMOS transistors N01 and N02, the gate terminal of the NMOS transistor N01 is connected to the output terminal of the NAND gate S00, and the drain terminal is connected to an output terminal a of the hysteresis voltage regulating circuit; the gate terminal of the NMOS transistor N02 is connected to the output terminal of the NAND gate S01, and the drain terminal is connected to another output terminal b of the hysteresis voltage regulating circuit; in the 1st stage, the drain terminal of the NMOS transistor N10 is simultaneously connected to the source terminals of the NMOS transistors N11 and N12, the gate terminal of the NMOS transistor N11 is connected to the output terminal of the NAND gate S10, and the drain terminal is connected to an output terminal a of the hysteresis voltage regulating circuit; the gate terminal of the NMOS transistor N12 is connected to the output terminal of the NAND gate S11, and the drain terminal is connected to another output terminal b of the hysteresis voltage regulating circuit;...; in the nth stage, the drain terminal of the NMOS transistor Nn0 is simultaneously connected to the source terminals of the NMOS transistors Nn1 and Nn2, the gate terminal of the NMOS transistor Nn1 is connected to the output terminal of the NAND gate Sn0, and the drain terminal is connected to an output terminal a of the hysteresis voltage regulating circuit; the gate terminal of the NMOS transistor Nn2 is connected to the output terminal of the NAND gate Sn1, and the drain terminal is connected to another output terminal b of the hysteresis voltage regulating circuit. One of the input terminals of the NAND gates S00, S01, S10, S11,..., Sn0, Sn1 is connected to the enable terminal EN of the hysteresis voltage regulating circuit. The source terminals of the NMOS transistors N00, N10,..., Nn0 are all connected to the power supply voltage VDD, and the gate terminals are all connected to the first bias voltage Bias1.

[0032] The NMOS transistors M0, M5, M6, M7, M12, M13 and the NMOS transistors N00, N10, ..., Nn0 have the same dimensions, and their function is to provide a proper current path; the NMOS transistors M8 and M9 have the same dimensions as the NMOS transistors N11, N12, ..., Nn1, Nn2, and the NMOS transistors M10 and M11 have the same dimensions, in order to have sufficient hysteresis voltage regulation margin; generally, the dimension of the NMOS transistor M8 is more than 3n times that of the NMOS transistor MM10, and the number of parallel-connected transistors of the NMOS transistor M8 is more than 3n times that of the NMOS transistor MM10.

[0033] The enable terminal RN of the hysteresis voltage regulation circuit is an n-bit digital regulation code, which can turn on or off the switch corresponding to the current regulation code through high and low levels, so as to control the on and off of the NMOS transistors Nx1 and Nx2 (x is 0, 1, 2, ..., n). By controlling the current magnitude in the input voltage comparator at the two output terminals a and b, the cost of the input terminal voltage can be increased, so as to achieve the purpose of controlling the hysteresis voltage magnitude; when the output of the hysteresis voltage regulation circuit rises, the hysteresis voltage regulation circuit can be turned off through the enable terminal EN, so that the voltage comparator can be used normally.

[0034] The hysteresis voltage regulation circuit has n levels, and the output hysteresis voltage can be divided into levels of n-bit system high-level amplitude. Each level of switch opening can increase the hysteresis voltage by 1 / n of the system high-level amplitude, as Figure 3 shown.

[0035] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention according to the above disclosure are within the protection scope of the claims.

Claims

1. A voltage comparator with adjustable hysteresis voltage, characterized in that, It includes NMOS transistors M0 to M13, a hysteresis voltage regulation circuit, and inverters INV1 and INV2; The drain terminal of NMOS transistor M0 is connected to the source terminals of NMOS transistors M1 and M2 simultaneously; the source terminal of NMOS transistor M5 is connected to the drain terminals of NMOS transistors M3 and M4 simultaneously; the source terminal of NMOS transistor M0 is connected to the power supply voltage VDD, and the drain terminal of NMOS transistor M5 is grounded; The source terminal of NMOS transistor M6 is connected to the power supply voltage VDD, the drain terminal is connected to the source terminal of NMOS transistor M8, the drain terminal of NMOS transistor M8 is connected to the source terminal of NMOS transistor M10, the drain terminal of NMOS transistor M10 is connected to the source terminal of NMOS transistor M12, and the drain terminal of NMOS transistor M12 is grounded; The source terminal of NMOS transistor M7 is connected to the power supply voltage VDD, the drain terminal is connected to the source terminal of NMOS transistor M9, the drain terminal of NMOS transistor M9 is connected to the source terminal of NMOS transistor M11, the drain terminal of NMOS transistor M11 is connected to the source terminal of NMOS transistor M13, and the drain terminal of NMOS transistor M13 is grounded; The drain terminal of NMOS transistor M1 is connected to the drain terminals of NMOS transistors M11 and the source terminal of NMOS transistor M13 simultaneously, and the drain terminal of NMOS transistor M2 is connected to the drain terminals of NMOS transistors M10 and the source terminal of NMOS transistor M12 simultaneously; One output terminal a of the hysteresis voltage regulation circuit is connected to the drain terminal of NMOS transistor M6, the source terminal of NMOS transistor M8, and the source terminal of NMOS transistor M3 simultaneously; the other output terminal b of the hysteresis voltage regulation circuit is connected to the drain terminal of NMOS transistor M7, the source terminal of NMOS transistor M9, and the source terminal of NMOS transistor M4 simultaneously; The input terminal of inverter INV1 is connected between the drain terminal of NMOS transistor M9 and the source terminal of NMOS transistor M11, and the output terminal is connected to the input terminal of inverter INV2; the enable terminal EN of the hysteresis voltage regulation circuit is connected between the output terminal of inverter INV1 and the input terminal of inverter INV2.

2. The hysteresis voltage adjustable voltage comparator according to claim 1, characterized in that The gate terminals of NMOS transistors M1 and M3 are both connected to the positive input voltage terminal VM, and the gate terminals of NMOS transistors M2 and M4 are both connected to the negative input voltage terminal VP; The gate terminals of NMOS transistors M0, M6, and M7 are all connected to the first bias voltage Bias1; the gate terminals of NMOS transistors M5, M12, and M13 are all connected to the second bias voltage Bias2; the gate terminals of NMOS transistors M8 and M9 are both connected to the third bias voltage Bias3; the gate terminals of NMOS transistors M10 and M1 are both connected to the fourth bias voltage Bias4.

3. The voltage comparator with adjustable hysteresis voltage according to claim 2, wherein The first bias voltage Bias1, the second bias voltage Bias2, the third bias voltage Bias3, and the fourth bias voltage Bias4 are generated by a bias voltage generation circuit CMP Bias to provide correct biasing for each tail transistor so that it is in the correct state.

4. The hysteresis voltage adjustable voltage comparator according to claim 3, characterized in that, The hysteresis voltage regulation circuit has n stages, and the structure of each stage is the same, and each stage includes a zero-th NMOS transistor, a first NMOS transistor, a second NMOS transistor, a first NAND gate, and a second NAND gate; The drain terminal of the zero-th NMOS transistor is simultaneously connected to the source terminal of the first NMOS transistor and the source terminal of the second NMOS transistor. The gate terminal of the first NMOS transistor is connected to the output terminal of the first NAND gate, and the drain terminal is connected to an output terminal a of the hysteresis voltage regulation circuit. The gate terminal of the second NMOS transistor is connected to the output terminal of the second NAND gate, and the drain terminal is connected to another output terminal b of the hysteresis voltage regulation circuit; One input terminal of the first NAND gate and the second NAND gate in each stage is connected to the enable terminal EN of the hysteresis voltage regulation circuit. The source terminals of the zero-th NMOS transistors in each stage are all connected to the power supply voltage VDD, and the gate terminals are all connected to the first bias voltage Bias1.

5. The hysteresis voltage adjustable voltage comparator according to claim 4, characterized in that, The NMOS transistors M0, M5, M6, M7, M12, and M13 have the same size as the zero-th NMOS transistor in each stage of the hysteresis voltage regulation circuit, and their function is to provide a suitable current path.

6. The hysteresis voltage adjustable voltage comparator according to claim 5, wherein The NMOS transistor M8 and the NMOS transistor M9 have the same size as the first NMOS transistor and the second NMOS transistor in each stage of the hysteresis voltage regulation circuit.

7. The hysteresis voltage adjustable voltage comparator according to claim 6, characterized in that, The NMOS transistors M10 and M11 have the same size to have sufficient hysteresis voltage regulation margin.

8. The hysteresis voltage adjustable voltage comparator according to claim 7, characterized in that, The size of the NMOS transistor M8 is more than 3n times that of the NMOS transistor MM10, and the number of parallel NMOS transistors M8 is more than 3n times that of the NMOS transistor MM10.

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