An artificial neural synapse based on OECT and its preparation method

Abstract

The present invention discloses an artificial neural synapse based on OECT and a preparation method thereof, which mainly includes a substrate, a source electrode, a semiconductor layer, a drain electrode, an encapsulation layer, an electrolyte layer and a gate electrode. During the preparation process, a substrate is first prepared in a vertical structure, and the substrate is cleaned and dried. Then, a source electrode is prepared on the substrate, a semiconductor layer is prepared on the source electrode, a drain electrode is prepared on the semiconductor layer, an encapsulation layer is prepared on the substrate, and the semiconductor layer located between the source electrode and the drain electrode is exposed. An electrolyte layer is prepared above the semiconductor layer, and finally a gate electrode connected to the dielectric layer is prepared.

Description

Technical Field

[0001] The present invention belongs to the technical field of organic electrochemical transistors, and more specifically, relates to an artificial neural synapse based on OECT and a preparation method thereof. Background Art

[0002] Traditional transistors have the advantages of stable performance, low cost, high integration, and high degree of commercialization. However, traditional transistors have extremely poor flexibility and biocompatibility, and general scalability, making them unsuitable for cutting-edge applications in the era of artificial intelligence, such as brain-computer interfaces and implantable devices.

[0003] Compared with traditional silicon-based transistors, organic electrochemical transistors (OECTs) generally use organic polymer semiconductors as channel materials and adopt solution preparation methods, such as spin coating, which effectively reduces the problems of large-area preparation and cost control. In addition, OECTs use electrolyte solutions as dielectric layers, which are characterized by being able to achieve μF / cm without reducing the dielectric layer thickness to the nm level. 2 The capacitance of the OECT is above 100 nm, which enables ultra-low driving voltage and extremely high transconductance. Therefore, OECT is developing rapidly in the fields of artificial intelligence, intelligent robots, smart medical care, etc.

[0004] In recent years, the rapid development of brain-inspired electronics and chips has not only promoted the development of a variety of software based on artificial intelligence algorithms, but also put forward new performance requirements for electronic components. However, due to the structural characteristics of the traditional von Neumann architecture, the separation of computing and storage in hardware has limited room for further optimization in terms of intelligence and energy consumption control. Therefore, there is an urgent need for electronic components with low operating voltage (less than 1V), good stability, flexibility, biocompatibility, and high sensitivity.

[0005] Based on the advantages of OECT in flexibility, biocompatibility, low-voltage drive, etc., researchers have carried out a lot of research in recent years, and it has shown great application value in various fields closely related to human production and life as well as cutting-edge fields such as biological detection, flexible sensors, artificial synapses, etc. Summary of the Invention

[0006] The purpose of the present invention is to overcome the shortcomings of the existing technology and provide an artificial neural synapse based on OECT and a preparation method thereof, so as to prepare the artificial neural synapse by using a vertical structure device, thereby achieving controllable ion and electron mobility and migration path, and then generating an electrical signal response with the response characteristics of a biological neural synapse.

[0007] To achieve the above-mentioned object of the invention, the present invention provides an artificial neural synapse based on OECT, characterized by comprising: a substrate, a source electrode, a semiconductor layer, a drain electrode, an encapsulation layer, an electrolyte layer and a gate electrode;

[0008] A rectangular strip source electrode is arranged in the center of the substrate, a square semiconductor layer is arranged in the center of the source electrode, and the width of the semiconductor layer is greater than that of the source electrode; a rectangular strip drain electrode is arranged in the center of the semiconductor layer, and the width of the drain electrode is less than that of the semiconductor layer; an encapsulation layer is arranged in the center of the drain electrode, and a square hole is opened in the center of the encapsulation layer. When viewed from a top view, the size of the hole is such that the drain electrode is exposed on the left and right rectangular strips; an electrolyte layer is covered on the top of the encapsulation layer, and the size of the electrolyte layer is such that it completely covers the square hole of the encapsulation layer; a gate electrode is arranged on the electrolyte layer, and the gate electrode is in full contact with the electrolyte layer, or a gate electrode is arranged on the side of the semiconductor layer, and the gate electrode and the source electrode are located in the same plane;

[0009] A control signal is applied to the gate. Under the action of the source-drain voltage between the drain and source, the ions in the electrolyte layer can penetrate into or precipitate out of the semiconductor layer, thereby generating an electrical signal that simulates a synapse.

[0010] The object of the invention of the present invention is achieved like this:

[0011] The artificial neural synapse based on OECT of the present invention and the preparation method thereof mainly include a substrate, a source electrode, a semiconductor layer, a drain electrode, an encapsulation layer, an electrolyte layer and a gate electrode; during the preparation process, the substrate is first prepared in a vertical structure, and the substrate is cleaned and dried; then the source electrode is prepared on the substrate, the semiconductor layer is prepared on the source electrode, the drain electrode is prepared on the semiconductor layer, the encapsulation layer is prepared on the substrate, and the semiconductor layer located between the source electrode and the drain electrode is exposed, the electrolyte layer is prepared above the semiconductor layer, and finally the gate electrode connected to the dielectric layer is prepared.

[0012] At the same time, the artificial neural synapse based on OECT and the preparation method thereof of the present invention also have the following beneficial effects:

[0013] (1) Using vertical structure devices, the ion and electron mobility and migration path are controllable; the control means include: source and drain electrode width, semiconductor layer thickness and composite semiconductor material mixing ratio;

[0014] (2) Under the action of the gate voltage, ions in the electrolyte dielectric layer are doped into or precipitated into the semiconductor through the drain edge, thereby controlling the carrier concentration in the semiconductor and changing the conductivity of the semiconductor;

[0015] (3) This process simulates the biological phenomenon of synaptic release of neurotransmitters causing membrane potential changes, making the device's electrical signal response have the basic characteristics of biological synaptic response;

[0016] (4) The vertical organic electrochemical transistor artificial synapse provided by the present invention has excellent controllability and synaptic plasticity, and has the advantages of low power consumption, miniaturization, and good biocompatibility. Its applications include brain-like computing, brain-computer / human-computer interfaces, and biological function repair / enhancement;

[0017] (5) Ratio: The semiconductor / crosslinker ratio of the device channel layer is adjustable; devices prepared using semiconductor solutions with different ratios have different ion permeability and therefore exhibit different electrical properties;

[0018] (6) Package opening: The device of the present invention can change the shape of the package layer opening to control the efficiency of ion incorporation / exfiltration; as described in effect (2), ions are doped into and out of the semiconductor channel through the edge of the electrode (or channel), and changing the size and method of the opening can change the ion penetration method: for example, when the complete channel layer is exposed to the outside and a gate voltage is applied to turn on the device, ions simultaneously penetrate into the channel from all sides of the rectangular film, and when the voltage is removed, the ions penetrate from all sides; if only one of the left or right rectangular strips of the drain is exposed to the outside, ions penetrate into / exfiltrate from one side of the rectangular film, thereby controlling the ion movement distance and changing the characteristics of the artificial neural synapse; if the length of the exposed rectangular strip is changed, the size of the channel for ion incorporation or precipitation will be changed, effectively regulating the number of ions entering the channel per unit time, and further regulating the characteristics of the artificial neural synapse. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 1 is a hierarchical structure diagram of the artificial neural synapse based on OECT of the present invention;

[0020] Figure 2 is the transfer characteristic curve of output current under different electrode widths;

[0021] Figure 3 is the double pulse response curve output under different electrode widths;

[0022] Figure 4 is the first impulse response peak curve;

[0023] Figure 5 is the peak curve of the second impulse response;

[0024] Figure 6 It is the curve fitted with the double pulse facilitation (PPF) characteristic;

[0025] Figure 7 is the leakage current I under different electrode widths D The pulse number-dependent plasticity response curve was drawn along with the pulse variation pattern;

[0026] Figure 8This is a structural diagram of an artificial neural synapse based on OECT using a top full-coverage gate and a side gate; DETAILED DESCRIPTION

[0027] The following describes the specific embodiments of the present invention in conjunction with the accompanying drawings so that those skilled in the art can better understand the present invention. It should be noted that in the following description, when detailed descriptions of known functions and designs may dilute the main content of the present invention, such descriptions will be omitted here.

[0028] Example

[0029] Figure 1 This is a hierarchical structure diagram of the artificial neural synapse based on OECT of the present invention.

[0030] In this embodiment, an artificial neural synapse based on OECT, such as Figure 1 (a) shows a cross-sectional view of an artificial neural synapse, comprising a substrate 1, a source electrode 2, a semiconductor layer 3, a drain electrode 4, an encapsulation layer 5, an electrolyte layer 6, and a gate electrode 7;

[0031] exist Figure 1 (b) The source electrode 2 in the form of a rectangular strip is set in the center of the substrate 1. Figure 1 As shown in (c), the length of the source 2 is aligned with the width of the substrate 1; Figure 1 As shown in (d), a square semiconductor layer 3 is provided at the center of the source 2, and the width of the semiconductor layer 3 is greater than the width of the source 2; Figure 1 As shown in (e), a rectangular strip-shaped drain electrode 4 is provided at the center of the semiconductor layer 3. The length of the drain electrode 4 is aligned with the width of the substrate 1, and the width of the drain electrode 4 is smaller than the width of the semiconductor layer 3. Figure 1 As shown in (f), an encapsulation layer 5 is provided at the center of the drain electrode 3, and a square hole is opened in the center of the encapsulation layer 5. At this time, the size of the hole, as viewed from the top view, only needs to be sufficient to expose the left and right rectangular strips of the drain electrode 4; Figure 1 As shown in (g), the encapsulation layer 5 is covered with an electrolyte layer 6, and the size of the electrolyte layer 6 is sufficient to completely cover the square hole of the encapsulation layer 5; a gate 7 is provided on the electrolyte layer 6, and the gate 7 is in full contact with the electrolyte layer 6;

[0032] like Figure 8 In (a), the gate 7 can be an electrode sheet directly above the electrolyte layer 6; Figure 8 In (b), the gate electrode 7 may be located on the side of the semiconductor layer 3 and in the same plane as the source electrode 2;

[0033] A control signal is applied to the gate 7. Under the action of the source-drain voltage between the drain 4 and the source 2, the ions in the electrolyte layer 6 can penetrate into or precipitate out of the semiconductor layer 3, thereby generating an electrical signal simulating a synapse. The characteristics of this signal will be affected by various factors including the electrode width. Therefore, the width of the source and drain electrodes, the thickness of the semiconductor layer, and the mixing ratio of the composite semiconductor material can be controlled according to actual conditions, thereby effectively regulating the migration time of electrons and ions and achieving effective regulation of the plasticity of artificial neural synapses.

[0034] In this embodiment, the substrate is selected from one of glass, silicon wafer, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polydimethylsiloxane (PDMS), or polyurethane (PU).

[0035] In this embodiment, the electrode width of the source and drain electrodes ranges from 1 to 500 μm, and they are specifically composed of an electrochemically stable conductive material, specifically one of gold, platinum, carbon nanotubes or graphene; the gate is selected from a conductive material with or without electrochemical activity, specifically one of gold, silver, poly (3,4-ethylenedioxythiophene): polystyrene sulfonate, carbon nanotubes, graphene, and graphyne.

[0036] In this embodiment, the semiconductor layer has a thickness of 10 to 1 μm and is specifically made of a composite semiconductor material that is both ion-conducting and electron-conducting. The mass ratio of the semiconductor material to the insulating material in the composite semiconductor material is 4:1 to 1:5.

[0037] In this embodiment, the encapsulation layer is made of an electrochemically stable insulating material, specifically one of Piperin-C, cellulose, photoresist SU-8, polystyrene, polydimethylsiloxane PDMS, and polystyrene-ethylene-butylene SEBS.

[0038] In this embodiment, the electrolyte layer is a solid or liquid electrolyte that does not have electron-conducting properties but has ion-conducting properties.

[0039] In combination with the above materials, the preparation method of an artificial neural synapse based on OECT of the present invention is described in detail below, which specifically includes the following steps:

[0040] (1) Ultrasonic cleaning with isopropyl alcohol Figure 1 (b) The glass substrate shown was dried for 15 minutes and then dried in an oven at 80°C for 2 hours.

[0041] (2) On the cleaned glass substrate, 3nm chromium and 120nm gold are sequentially deposited as source electrodes with a width of 30 to 120μm. Figure 1 (c)

[0042] (3) The silicon wafer with a layer of electrode deposited thereon is subjected to UV ozone cleaning for about 10 minutes;

[0043] (4) Prepare a semiconductor layer with photocrosslinking function by spin coating: control the humidity below 20%, spin coating speed at 5000 rpm, and spin coating for 30 seconds; Photolithography: use 365nm ultraviolet light for exposure treatment to crosslink the semiconductor film in the channel to form a semiconductor layer in the channel area, such as Figure 1 (d)

[0044] (5) Prepare 120nm gold as drain electrode on the semiconductor layer, with an electrode width of 30 to 120μm, such as Figure 1 (e)

[0045] (6) Prepare a spin-coated encapsulation layer with photocrosslinking function, and use 365nm ultraviolet light for exposure to expose the patterned channel, such as Figure 1 (f)

[0046] (7) Add about 1 μL of PBS buffer solution on the exposed channel as a dielectric layer, and connect the gate through the dielectric layer, as shown in Figure 1 (g) shown.

[0047] Thus, an OECT device with synaptic properties was successfully fabricated. In this example, the source, drain, and gate electrodes were fabricated using one of the following methods: evaporation, magnetron sputtering, spray coating, inkjet printing, aerosol printing, or screen printing. The semiconductor layer, encapsulation layer, and electrolyte layer were fabricated using one of the following methods: spin coating, spray coating, screen printing, inkjet printing, 3D printing, aerosol printing, electrohydrodynamic printing, or doctor blade coating.

[0048] Next, we use the prepared artificial synapses to perform plasticity tests under the following conditions:

[0049] (1) Constant drain voltage V D =0.1V, set the gate-source voltage between 0.1V and -0.7V and scan forward and reverse, with a constant drain voltage V D = 0.5V, repeat the scan, capture the output current, obtain the transfer characteristics and plot Figure 2 The graphs shown in (a)-(g) are obtained by Figure 2 It can be seen that devices with different channel shapes have different hysteresis responses. The rule is: as the width of the top electrode decreases, the ion permeation path becomes shorter and the output current hysteresis becomes smaller; conversely, the hysteresis becomes more obvious.

[0050] (2) Constant drain voltage V D=0.5V, input continuous width of 200ms, amplitude of -0.7V, pulse interval (Δt) of 500ms, 400ms, 300ms, 200ms, 100ms, 80ms, 60ms, 40ms, 20ms, get Figure 3 (a)-(g) show the output double pulse response, through Figure 3 It can be seen that when a pair of continuous short-interval pulses are input, the corresponding second pulse response is significantly enhanced compared to the first pulse response, and its gain becomes more obvious as the pulse interval becomes shorter; then capture the two pulse response peaks, such as Figure 4 、 5 The absolute values ​​of the two pulse responses shown in FIG. 1 increase with the width of the top electrode; the quotient is then calculated to obtain the double pulse facilitation characteristic PPF, and the obtained value is fitted according to formula (1) to obtain a curve, as shown in FIG. Figure 6 As shown in Figure 2, the double-pulse facilitation changes with the pulse interval in the following manner: the shorter the pulse interval, the more obvious the double-pulse facilitation; conversely, the weaker the double-pulse facilitation. The shorter the pulse interval, the less ions seep out of the channel, so more ions remain in the channel, causing a more obvious enhancement phenomenon.

[0051]

[0052] Where C1 and C2 are the capacitance coefficients to be determined by the fitting curve, Δt is the pulse interval, and τ1 and τ2 are the time constants to be determined by the fitting curve. The double-pulse facilitation changes with the pulse interval in the following manner: the shorter the pulse interval, the more pronounced the double-pulse facilitation, and vice versa. The shorter the pulse interval, the less ions permeate the channel, resulting in more residual ions in the channel, leading to a more pronounced enhancement.

[0053] (3) Constant drain voltage V D =0.5V, input amplitude is -0.7V, pulse width is 500ms, pulse interval is 50ms, and 100 identical pulse excitations are used to obtain the leakage current I D The pulse number-dependent plasticity response curve is drawn along with the pulse variation law, such as Figure 7 As shown in (a)-(g), the number-dependent plasticity of the device with a small top electrode approximately shows a linear growth law with the number of pulses within 100 pulses, while the device with a larger top electrode shows a trend of output current saturation earlier;

[0054] In the figure above, electrode width represents the bottom electrode width × the top electrode width. Artificial synaptic devices with different electrode widths exhibit distinct hysteresis characteristics and the resulting synaptic plasticity. Devices with wider top electrodes exhibit a pronounced hysteresis loop and a more pronounced double-pulse facilitation enhancement effect in synaptic plasticity. However, devices with narrower top electrodes exhibit higher current flow and are more likely to reach leakage saturation under stimulation by multiple pulse signals. This method allows the production of artificial synaptic devices with significantly different controllability.

[0055] Although the above describes the illustrative specific embodiments of the present invention to facilitate understanding of the present invention by those skilled in the art, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those skilled in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the appended claims, these changes are obvious, and all inventions and creations using the concepts of the present invention are protected.

Claims

1. An artificial neural synapse based on OECT, characterized in that: include: Substrate, source electrode, semiconductor layer, drain electrode, encapsulation layer, electrolyte layer and gate electrode; A rectangular strip source electrode is provided in the center of the substrate, a square semiconductor layer is provided at the center of the source electrode, and the width of the semiconductor layer is greater than that of the source electrode; a rectangular strip drain electrode is provided at the center of the semiconductor layer, and the width of the drain electrode is less than that of the semiconductor layer; An encapsulation layer is provided at the center of the drain electrode, and a square hole is opened in the center of the encapsulation layer. When viewed from a top view, the size of the hole is sufficient to allow the drain electrode to expose left and right rectangular strips. An electrolyte layer is provided above the encapsulation layer, and the size of the electrolyte layer is sufficient to completely cover the square hole of the encapsulation layer. A gate is provided above the electrolyte layer, and the gate is in full contact with the electrolyte layer, or a gate is provided on the side of the porous semiconductor layer, and the gate and the source electrode are located in the same plane. A control signal is applied to the gate. Under the influence of the source-drain voltage between the drain and source electrodes, ions in the electrolyte layer can penetrate into or precipitate from the semiconductor layer, thereby generating an electrical signal that simulates a synapse. The semiconductor layer has a thickness of 10 nm to 1 μm and is specifically made of a composite semiconductor material that is both ion-conducting and electron-conducting. The mass ratio of the semiconductor material to the insulating material in the composite semiconductor material is 4:1 to 1:

5.

2. The artificial neural synapse based on OECT according to claim 1, characterized in that: The substrate is one of glass, silicon wafer, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polydimethylsiloxane (PDMS) or polyurethane (PU).

3. The artificial neural synapse based on OECT according to claim 1, characterized in that: The electrode width of the source and drain electrodes ranges from 1 to 500 μm, and they are specifically composed of electrochemically stable conductive materials, specifically one of gold, platinum, carbon nanotubes or graphene; the gate is made of a conductive material with or without electrochemical activity, specifically one of gold, silver, poly (3,4-ethylenedioxythiophene): polystyrene sulfonate, carbon nanotubes, graphene, and graphyne.

4. The artificial neural synapse based on OECT according to claim 1, characterized in that The encapsulation layer is made of an electrochemically stable insulating material, specifically one of parylene-C, cellulose, photoresist SU-8, polystyrene, polydimethylsiloxane PDMS, and polystyrene-ethylene-butylene SEBS.

5. The artificial neural synapse based on OECT according to claim 1, characterized in that: The electrolyte layer is a solid or liquid electrolyte that does not have electronic conductivity but has ion conductivity.

6. The method for preparing an artificial neural synapse based on OECT according to claim 1, characterized in that: The preparation process includes the following steps: Step 1: Prepare the substrate, clean it and dry it; Using a glass substrate as the substrate, the glass substrate was ultrasonically cleaned with isopropyl alcohol for 15 minutes and then dried in an oven at 80°C for 2 hours; Step 2: Prepare a source electrode on the substrate; 3nm chromium and 120nm gold were sequentially evaporated on the cleaned glass substrate as source electrodes with a width of 30 to 120μm; Step 3: preparing a semiconductor layer on the source electrode; A silicon wafer with an electrode layer deposited thereon was cleaned with UV ozone for 10 minutes, and then a photocrosslinkable semiconductor layer was spin-coated. The humidity was controlled below 20%, and the spin coating speed was 5000 rpm for 30 seconds. Photolithography was then performed using 365 nm UV light exposure to crosslink the semiconductor film in the channel region, forming a semiconductor layer in the channel region. Step 4: preparing a drain electrode on the semiconductor layer; A 120nm gold drain electrode is prepared on the semiconductor layer, with an electrode width of 30 to 120μm; Step 5: preparing an encapsulation layer on the substrate and exposing the semiconductor layer between the source and drain electrodes; Prepare a spin-coated encapsulation layer with photocrosslinking function and expose it with 365nm ultraviolet light to expose the patterned channels; Step 6: preparing an electrolyte layer on top of the semiconductor layer; 1 μL of PBS buffer was added dropwise on the exposed channels to serve as the electrolyte layer; Step 7: Prepare the gate electrode connected to the electrolyte layer.

7. The method for preparing an artificial neural synapse based on OECT according to claim 6, characterized in that: The source electrode, drain electrode and gate electrode are prepared by evaporation, magnetron sputtering, spraying, inkjet printing, aerosol printing and screen printing.

8. The method for preparing an artificial neural synapse based on OECT according to claim 6, characterized in that: The semiconductor layer, encapsulation layer, and electrolyte layer are prepared by spin coating, spray coating, screen printing, inkjet printing, 3D printing, aerosol printing, electrofluid printing, or scraping.

Images