Pixel circuit, driving method, display panel and display device

Abstract

The application discloses a pixel circuit, a driving method, a display panel and a display device. The pixel circuit comprises a light emitting device, a driving transistor, a data writing circuit, a threshold compensation circuit, an initialization circuit, a noise reduction circuit, a light emitting control circuit, a first storage circuit and a second storage circuit. The data writing circuit is configured to input a data voltage signal at a data signal end to a first node in response to a signal at a first control signal end. The threshold compensation circuit is configured to turn on a second electrode of the driving transistor and a gate electrode of the driving transistor in response to a signal at a second control signal end. The initialization circuit is configured to initialize the gate electrode of the driving transistor, a second node and the light emitting device. The light emitting control circuit is configured to turn on a reference voltage signal end and the first node in response to a signal at a first light emitting control signal end, and to turn on the second electrode of the driving transistor and the light emitting device in response to a signal at a second light emitting control signal end, so as to drive the light emitting device to emit light.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to pixel circuits, driving methods, display panels, and display devices. Background Technology

[0002] Organic light-emitting diode (OLED) displays are currently a hot topic in flat panel display research. Compared to liquid crystal displays (LCDs), OLED displays have advantages such as low power consumption, low production cost, self-emissiveness, wide viewing angle, and fast response speed. Generally, OLED display devices use pixel circuits to drive the light-emitting devices to emit light. Summary of the Invention

[0003] The pixel circuit provided in this embodiment of the invention includes:

[0004] Light-emitting devices;

[0005] The driving transistor is configured to generate a driving current that drives the light-emitting device to emit light based on a data voltage signal;

[0006] The data writing circuit is configured to input the data voltage signal from the data signal terminal to the first node in response to a signal from the first control signal terminal.

[0007] A threshold compensation circuit is configured to turn on the second terminal of the driving transistor and the gate of the driving transistor in response to a signal at the second control signal terminal.

[0008] An initialization circuit is configured to initialize the gate, second node, and light-emitting device of the driving transistor.

[0009] The noise reduction circuit is configured to, in response to a signal at the third control signal terminal, connect the second terminal of the driving transistor to the first node.

[0010] The light-emitting control circuit is configured to connect the reference voltage signal terminal to the first node in response to a signal at the first light-emitting control signal terminal, and to connect the second terminal of the driving transistor to the light-emitting device in response to a signal at the second light-emitting control signal terminal, thereby driving the light-emitting device to emit light.

[0011] A first storage circuit is configured to maintain a stable voltage difference between the first node and the second node;

[0012] A second storage circuit is configured to maintain a stable voltage difference between the second node and the gate of the driving transistor.

[0013] In some possible implementations, the initialization circuit is further configured to provide the signal of the first initialization signal terminal to the gate of the driving transistor in response to the signal of the first control signal terminal, to provide the signal of the first power supply terminal to the second node in response to the signal of the second control signal terminal, and to provide the signal of the first initialization signal terminal to the light-emitting device in response to the signal of the fourth control signal terminal.

[0014] In some possible implementations, the initialization circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor; the gate of the first transistor is coupled to the fourth control signal terminal, the first electrode of the first transistor is coupled to the first initialization signal terminal, and the second electrode of the first transistor is coupled to the light-emitting device; the gate of the second transistor is coupled to the first control signal terminal, the first electrode of the second transistor is coupled to the gate of the driving transistor, and the second electrode of the second transistor is coupled to the first initialization signal terminal; the gate of the third transistor is coupled to the first control signal terminal, the first electrode of the third transistor is coupled to the second node, and the second electrode of the third transistor is coupled to the first power supply terminal; the gate of the fourth transistor is coupled to the second control signal terminal, the first electrode of the fourth transistor is coupled to the second node, and the second electrode of the fourth transistor is coupled to the first power supply terminal.

[0015] In some possible implementations, the initialization circuit is further configured to provide a signal from the second initialization signal terminal to the gate of the driving transistor in response to a signal from the fifth control signal terminal, to provide a signal from the first power supply terminal to the second node in response to a signal from the first light-emitting control signal terminal, and to provide a signal from the second initialization signal terminal to the light-emitting device in response to a signal from the sixth control signal terminal.

[0016] In some possible implementations, the initialization circuit includes a fifth transistor, a sixth transistor, and a seventh transistor; the gate of the fifth transistor is coupled to the fifth control signal terminal, the first terminal of the fifth transistor is coupled to the gate of the driving transistor, and the second terminal of the fifth transistor is coupled to the second initialization signal terminal; the gate of the sixth transistor is coupled to the sixth control signal terminal, the first terminal of the sixth transistor is coupled to the light-emitting device, and the second terminal of the sixth transistor is coupled to the second initialization signal terminal; the gate of the seventh transistor is coupled to the first light-emitting control signal terminal, the first terminal of the seventh transistor is coupled to the second node, and the second terminal of the seventh transistor is coupled to the first power supply terminal.

[0017] In some possible implementations, the first light emission control signal terminal and the second light emission control signal terminal are the same signal terminal.

[0018] In some possible implementations, the initialization circuit is further configured to provide a signal from the third initialization signal terminal to the gate of the driving transistor in response to signals from the first control signal terminal and the seventh control signal terminal, to provide a signal from the first power supply terminal to the second node in response to a signal from the seventh control signal terminal, and to provide a signal from the third initialization signal terminal to the light-emitting device in response to a signal from the eighth control signal terminal.

[0019] In some possible implementations, the initialization circuit includes an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor; the gate of the eighth transistor is coupled to the eighth control signal terminal, the first terminal of the eighth transistor is coupled to the third initialization signal terminal, and the second terminal of the eighth transistor is coupled to the light-emitting device; the gate of the ninth transistor is coupled to the first control signal terminal, the first terminal of the ninth transistor is coupled to the threshold compensation circuit, and the second terminal of the ninth transistor is coupled to the third initialization signal terminal; the gate of the tenth transistor is coupled to the seventh control signal terminal, the first terminal of the tenth transistor is coupled to the gate of the driving transistor, and the second terminal of the tenth transistor is coupled to the first terminal of the ninth transistor; the gate of the eleventh transistor is coupled to the seventh control signal terminal, the first terminal of the eleventh transistor is coupled to the second node, and the second terminal of the eleventh transistor is coupled to the first power supply terminal.

[0020] In some possible implementations, the data writing circuit includes a twelfth transistor;

[0021] The gate of the twelfth transistor is coupled to the first control signal terminal, the first terminal of the twelfth transistor is coupled to the data signal terminal, and the second terminal of the twelfth transistor is coupled to the first node.

[0022] In some possible implementations, the threshold compensation circuit includes a thirteenth transistor; the gate of the thirteenth transistor is coupled to the second control signal terminal, the first terminal of the thirteenth transistor is coupled to the gate of the driving transistor, and the second terminal of the thirteenth transistor is coupled to the second terminal of the driving transistor.

[0023] In some possible implementations, the noise reduction circuit includes a fourteenth transistor; the gate of the fourteenth transistor is coupled to the third control signal terminal, the first terminal of the fourteenth transistor is coupled to the first node, and the second terminal of the fourteenth transistor is coupled to the second terminal of the driving transistor.

[0024] In some possible implementations, the light-emitting control circuit includes a fifteenth transistor and a sixteenth transistor; the gate of the fifteenth transistor is coupled to the first light-emitting control signal terminal, the first terminal of the fifteenth transistor is coupled to the reference voltage signal terminal, and the second terminal of the fifteenth transistor is coupled to the first node; the gate of the sixteenth transistor is coupled to the second light-emitting control signal terminal, the first terminal of the sixteenth transistor is coupled to the second terminal of the driving transistor, and the second terminal of the sixteenth transistor is coupled to the light-emitting device.

[0025] In some possible implementations, the first storage circuit includes a first capacitor; a first electrode of the first capacitor is coupled to the first node, and a second electrode of the first capacitor is coupled to the second node; and / or, the second storage circuit includes a second capacitor; a first electrode of the second capacitor is coupled to the second node, and a second electrode of the second capacitor is coupled to the gate of the driving transistor.

[0026] The display panel provided in this embodiment of the invention includes the pixel circuit described above.

[0027] The display device provided in this embodiment of the invention includes the display panel described above.

[0028] The driving method for the pixel circuit provided in this embodiment of the invention includes: a data writing stage, wherein the data writing circuit, in response to a signal at the first control signal terminal, inputs a data voltage signal from the data signal terminal to a first node; and an initialization circuit initializes the gate of the driving transistor, the second node, and the light-emitting device.

[0029] During the threshold voltage compensation phase, the threshold compensation circuit responds to the signal at the second control signal terminal by connecting the second terminal of the driving transistor to the gate of the driving transistor; the initialization circuit initializes the gate of the driving transistor and the second node.

[0030] During the light-emitting stage, the light-emitting control circuit responds to the signal at the first light-emitting control signal terminal by connecting the reference voltage signal terminal to the first node, and responds to the signal at the second light-emitting control signal terminal by connecting the second electrode of the driving transistor to the light-emitting device, thereby driving the light-emitting device to emit light;

[0031] During the initialization phase, the noise reduction circuit responds to the signal at the third control signal terminal and connects the second terminal of the driving transistor to the first node; the initialization circuit initializes the light-emitting device. Attached Figure Description

[0032] Figure 1Some structural schematic diagrams of pixel circuits provided in embodiments of the present invention;

[0033] Figure 2 These are some other structural schematic diagrams of the pixel circuit provided in the embodiments of the present invention;

[0034] Figure 3 These are further schematic diagrams of the pixel circuit provided in embodiments of the present invention;

[0035] Figure 4 A flowchart of a pixel circuit driving method provided in an embodiment of the present invention;

[0036] Figure 5 Some signal timing diagrams provided for embodiments of the present invention;

[0037] Figure 6 These are further schematic diagrams of the pixel circuit provided in embodiments of the present invention;

[0038] Figure 7 These are further schematic diagrams of the pixel circuit provided in embodiments of the present invention;

[0039] Figure 8 Other signal timing diagrams provided for embodiments of the present invention;

[0040] Figure 9 These are further schematic diagrams of the pixel circuit provided in embodiments of the present invention;

[0041] Figure 10 Further signal timing diagrams provided for embodiments of the present invention;

[0042] Figure 11 These are further schematic diagrams of the pixel circuit provided in embodiments of the present invention;

[0043] Figure 12 These are further schematic diagrams of the pixel circuit provided in embodiments of the present invention;

[0044] Figure 13 These are some more signal timing diagrams provided for embodiments of the present invention. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Furthermore, the embodiments and features in the embodiments of the present invention can be combined with each other without conflict. Based on the described embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0046] Unless otherwise defined, the technical or scientific terms used in this invention shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0047] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of the invention. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0048] The display device provided in this embodiment of the invention includes: a display panel, wherein the display area of ​​the display panel includes a plurality of pixel units arranged in an array, and each pixel unit includes a plurality of sub-pixels. Exemplarily, each pixel unit includes a plurality of sub-pixels. For example, a pixel unit may include red sub-pixels, green sub-pixels, and blue sub-pixels, so that red, green, and blue can be mixed to achieve color display. Alternatively, a pixel unit may also include red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels, so that red, green, blue, and white can be mixed to achieve color display. Of course, in practical applications, the emission color of the sub-pixels in a pixel unit can be designed and determined according to the actual application environment, and is not limited here.

[0049] In this embodiment of the invention, each sub-pixel includes a pixel circuit, which includes a driving transistor and a light-emitting device to control the light-emitting device to emit light, thereby enabling the display panel to display an image. Due to process technology and device aging, the threshold voltage Vth of the driving transistor that drives the light-emitting device to emit light may be non-uniform. This causes the current flowing through different light-emitting devices to vary, resulting in uneven display brightness and affecting the overall image display effect.

[0050] This invention provides a pixel circuit, such as... Figure 1 As shown, it includes a light-emitting device L, a data writing circuit 10, a threshold compensation circuit 20, an initialization circuit 30, a noise reduction circuit 40, a light-emitting control circuit 50, a first storage circuit 60, and a second storage circuit 70.

[0051] The driving transistor T0 is configured to generate a driving current for the light-emitting device L to emit light based on the data voltage signal; the data writing circuit 10 is configured to input the data voltage signal of the data signal terminal DA into the first node N1 in response to the signal of the first control signal terminal CS1; the threshold compensation circuit 20 is configured to conduct the second terminal of the driving transistor T0 to the gate of the driving transistor T0 in response to the signal of the second control signal terminal CS2; the initialization circuit 30 is configured to initialize the gate of the driving transistor T0, the second node N2, and the light-emitting device L; and the noise reduction circuit 40 is configured to respond to the signal of the third control signal terminal CS2. The CS3 signal will turn on the second terminal of the driving transistor T0 and the first node N1; the light emission control circuit 50 is configured to turn on the reference voltage signal terminal VREF and the first node N1 in response to the signal of the first light emission control signal terminal EM1, and to turn on the second terminal of the driving transistor T0 and the light emission device L in response to the signal of the second light emission control signal terminal EM2, thereby driving the light emission device L to emit light; the first storage circuit 60 is configured to keep the voltage difference between the first node N1 and the second node N2 stable; the second storage circuit 70 is configured to keep the voltage difference between the second node N2 and the gate of the driving transistor T0 stable.

[0052] In this embodiment of the invention, by cooperating with the data writing circuit, threshold compensation circuit, initialization circuit, noise reduction circuit, light emission control circuit, first storage circuit, and second storage circuit, data writing and threshold voltage compensation are separated, so that the threshold voltage compensation time is no longer limited by the data writing time. This allows for improved threshold voltage compensation when the line scanning time is very short (e.g., under high frame rate conditions in a high-resolution display panel), thereby improving the display effect.

[0053] Furthermore, since the threshold voltage compensation process in the pixel circuit is actually performed during the initialization of the driving transistor, in order to ensure the effectiveness of the pixel circuit initialization under low frame rate conditions, this invention controls the gate-source voltage Vgs of the driving transistor to be in the state of Vgs≈Vth when the pixel circuit initializes the driving transistor in the hold frame, thereby achieving low frame rate display and improving the display effect.

[0054] In some embodiments of the present invention, such as Figure 1 As shown, the driving transistor T0 can be configured as a P-type transistor, where its first terminal can be its drain and its second terminal can be its source. When the driving transistor T0 is in saturation, current flows from its drain to its source. Of course, the driving transistor T0 can also be configured as an N-type transistor; this is not a limitation.

[0055] In embodiments of the present invention, such as Figure 1As shown, the first electrode of the driving transistor T0 is coupled to the first power supply terminal VDD, and the first electrode of the light-emitting device L is coupled to the second electrode of the driving transistor T0 through the light-emitting control circuit 50. The second electrode of the light-emitting device L is coupled to the second power supply terminal VSS. Exemplarily, the first electrode of the light-emitting device L can be its anode, and the second electrode can be its cathode. For example, the light-emitting device L can include at least one of a micro light-emitting diode (MicroLED), an organic light-emitting diode (OLED), and a quantum dot light-emitting diode (QLED). Exemplarily, the light-emitting device L can include an anode, a light-emitting layer, and a cathode stacked together. Further, the light-emitting layer can also include film layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. In practical applications, the specific structure of the light-emitting device L can be designed and determined according to the actual application environment, and is not limited here.

[0056] In embodiments of the present invention, such as Figure 2 As shown, the initialization circuit 30 is further configured to provide the signal of the first initialization signal terminal Vinit1 to the gate of the driving transistor T0 in response to the signal of the first control signal terminal CS1, to provide the signal of the first power supply terminal VDD to the second node N2 in response to the signal of the second control signal terminal CS2, and to provide the signal of the first initialization signal terminal Vinit1 to the light-emitting device L in response to the signal of the fourth control signal terminal CS4.

[0057] In embodiments of the present invention, such as Figure 3 As shown, the initialization circuit 30 includes a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4. The gate of the first transistor T1 is coupled to the fourth control signal terminal CS4, the first terminal of the first transistor T1 is coupled to the first initialization signal terminal Vinit1, and the second terminal of the first transistor T1 is coupled to the light-emitting device L. The gate of the second transistor T2 is coupled to the first control signal terminal CS1, the first terminal of the second transistor T2 is coupled to the gate of the driving transistor T0, and the second terminal of the second transistor T2 is coupled to the first initialization signal terminal Vinit1. The gate of the third transistor T3 is coupled to the first control signal terminal CS1, the first terminal of the third transistor T3 is coupled to the second node N2, and the second terminal of the third transistor T3 is coupled to the first power supply terminal VDD. The gate of the fourth transistor T4 is coupled to the second control signal terminal CS2, the first terminal of the fourth transistor T4 is coupled to the second node N2, and the second terminal of the fourth transistor T4 is coupled to the first power supply terminal VDD.

[0058] For example, the first transistor T1 can be turned on under the control of the effective level of the fourth control signal transmitted at the fourth control signal terminal CS4, and can be turned off under the control of the ineffective level of the fourth control signal. For example, if the first transistor T1 is set as a P-type transistor, then the effective level of the fourth control signal is low, and the ineffective level of the fourth control signal is high. Alternatively, if the first transistor T1 is set as an N-type transistor, then the effective level of the fourth control signal is high, and the ineffective level of the fourth control signal is low.

[0059] For example, the second transistor T2 can be turned on under the control of the effective level of the first control signal transmitted at the first control signal terminal CS1, and can be turned off under the control of the ineffective level of the first control signal. For example, if the second transistor T2 is set as a P-type transistor, then the effective level of the first control signal is low and the ineffective level of the first control signal is high. Alternatively, if the second transistor T2 is set as an N-type transistor, then the effective level of the first control signal is high and the ineffective level of the first control signal is low.

[0060] For example, the third transistor T3 can be turned on under the control of the effective level of the first control signal transmitted at the first control signal terminal CS1, and can be turned off under the control of the ineffective level of the first control signal. For example, if the third transistor T3 is set as a P-type transistor, then the effective level of the first control signal is low and the ineffective level of the first control signal is high. Alternatively, if the third transistor T3 is set as an N-type transistor, then the effective level of the first control signal is high and the ineffective level of the first control signal is low.

[0061] For example, the fourth transistor T4 can be turned on under the control of the effective level of the second control signal transmitted at the second control signal terminal CS2, and can be turned off under the control of the ineffective level of the second control signal. For example, if the fourth transistor T4 is set as a P-type transistor, then the effective level of the second control signal is low, and the ineffective level of the second control signal is high. Alternatively, if the fourth transistor T4 is set as an N-type transistor, then the effective level of the second control signal is high, and the ineffective level of the second control signal is low.

[0062] In embodiments of the present invention, such as Figure 3 As shown, the data writing circuit 10 includes a twelfth transistor T12. The gate of the twelfth transistor T12 is coupled to the first control signal terminal CS1, the first terminal of the twelfth transistor T12 is coupled to the data signal terminal DA, and the second terminal of the twelfth transistor T12 is coupled to the first node N1.

[0063] For example, the twelfth transistor T12 can be turned on under the control of the effective level of the first control signal transmitted at the first control signal terminal CS1, and can be turned off under the control of the ineffective level of the first control signal. For example, if the twelfth transistor T12 is configured as a P-type transistor, then the effective level of the first control signal is low, and the ineffective level of the first control signal is high. Alternatively, if the twelfth transistor T12 is configured as an N-type transistor, then the effective level of the first control signal is high, and the ineffective level of the first control signal is low.

[0064] In embodiments of the present invention, such as Figure 3 As shown, the threshold compensation circuit 20 includes a thirteenth transistor T13. The gate of the thirteenth transistor T13 is coupled to the second control signal terminal CS2, the first terminal of the thirteenth transistor T13 is coupled to the gate of the driving transistor T0, and the second terminal of the thirteenth transistor T13 is coupled to the second terminal of the driving transistor T0.

[0065] For example, the thirteenth transistor T13 can be turned on under the control of the effective level of the second control signal transmitted at the second control signal terminal CS2, and can be turned off under the control of the ineffective level of the second control signal. For example, if the thirteenth transistor T13 is set as a P-type transistor, then the effective level of the second control signal is low, and the ineffective level of the second control signal is high. Alternatively, if the thirteenth transistor T13 is set as an N-type transistor, then the effective level of the second control signal is high, and the ineffective level of the second control signal is low.

[0066] In embodiments of the present invention, such as Figure 3 As shown, the noise reduction circuit 40 includes a fourteenth transistor T14. The gate of the fourteenth transistor T14 is coupled to the third control signal terminal CS3, the first terminal of the fourteenth transistor T14 is coupled to the first node N1, and the second terminal of the fourteenth transistor T14 is coupled to the second terminal of the driving transistor T0.

[0067] For example, the fourteenth transistor T14 can be turned on under the control of the effective level of the third control signal transmitted at the third control signal terminal CS3, and can be turned off under the control of the ineffective level of the third control signal. For example, if the fourteenth transistor T14 is set as a P-type transistor, then the effective level of the third control signal is low, and the ineffective level of the third control signal is high. Alternatively, if the fourteenth transistor T14 is set as an N-type transistor, then the effective level of the third control signal is high, and the ineffective level of the third control signal is low.

[0068] In embodiments of the present invention, such as Figure 3As shown, the light-emitting control circuit 50 includes a fifteenth transistor T15 and a sixteenth transistor T16. The gate of the fifteenth transistor T15 is coupled to the first light-emitting control signal terminal EM1, the first terminal of the fifteenth transistor T15 is coupled to the reference voltage signal terminal VREF, and the second terminal of the fifteenth transistor T15 is coupled to the first node N1. The gate of the sixteenth transistor T16 is coupled to the second light-emitting control signal terminal EM2, the first terminal of the sixteenth transistor T16 is coupled to the second terminal of the driving transistor T0, and the second terminal of the sixteenth transistor T16 is coupled to the light-emitting device L.

[0069] For example, the fifteenth transistor T15 can be turned on under the control of the effective level of the first light-emitting control signal transmitted at the first light-emitting control signal terminal EM1, and can be turned off under the control of the ineffective level of the first light-emitting control signal. For example, if the fifteenth transistor T15 is set as a P-type transistor, then the effective level of the first light-emitting control signal is low, and the ineffective level of the first light-emitting control signal is high. Alternatively, if the fifteenth transistor T15 is set as an N-type transistor, then the effective level of the first light-emitting control signal is high, and the ineffective level of the first light-emitting control signal is low.

[0070] For example, the sixteenth transistor T16 can be turned on under the control of the effective level of the second light-emitting control signal transmitted at the second light-emitting control signal terminal EM2, and can be turned off under the control of the ineffective level of the second light-emitting control signal. For example, if the sixteenth transistor T16 is set as a P-type transistor, then the effective level of the second light-emitting control signal is low, and the ineffective level of the second light-emitting control signal is high. Alternatively, if the sixteenth transistor T16 is set as an N-type transistor, then the effective level of the second light-emitting control signal is high, and the ineffective level of the second light-emitting control signal is low.

[0071] In embodiments of the present invention, such as Figure 3 As shown, the first storage circuit 60 includes a first capacitor C1. The first electrode of the first capacitor C1 is coupled to a first node N1, and the second electrode of the first capacitor C1 is coupled to a second node N2.

[0072] In embodiments of the present invention, such as Figure 3 As shown, the second storage circuit 70 includes a second capacitor C2. The first electrode of the second capacitor C2 is coupled to the second node N2, and the second electrode of the second capacitor C2 is coupled to the gate of the driving transistor T0.

[0073] For example, the first electrode of the transistor described above can be its source, and the second electrode can be its drain. Alternatively, the first electrode can be its drain, and the second electrode can be its source. No limitation is made here.

[0074] Transistors that typically use low-temperature polysilicon (LTPS) as the active layer have high mobility, can be made thinner and smaller, and consume less power. In specific implementations, the active layer of at least one of the aforementioned transistors can be made of low-temperature polysilicon. This allows the transistor to be configured as an LTPS type transistor, enabling the pixel circuit to achieve high mobility, thinner and smaller design, and lower power consumption.

[0075] Transistors that typically use metal-oxide-semiconductor (MODS) materials as their active layers generally have low leakage current. Therefore, to reduce leakage current, in some embodiments of this invention, the active layer of at least one transistor may also include a MODS material, such as IGZO (Indium Gallium Zinc Oxide). Of course, other MODS materials can also be used, and this is not limited here. This allows the transistor to be configured as an oxide thin-film transistor, thereby reducing the leakage current of the pixel circuit.

[0076] For example, all transistors can be configured as LTPS transistors. Alternatively, all transistors can be configured as oxide transistors. Alternatively, some transistors can be configured as oxide transistors, and the rest as LTPS transistors. By combining LTPS and oxide transistor fabrication processes to fabricate LTPO pixel drive circuits using low-temperature polycrystalline silicon oxide, the gate leakage current of the drive transistor T0 can be reduced, and power consumption can be lowered.

[0077] In this embodiment of the invention, the first power supply terminal VDD can be configured to load a constant first power supply voltage Vdd, and the first power supply voltage Vdd is generally positive. The second power supply terminal VSS can be loaded with a constant second power supply voltage Vss, and the second power supply voltage Vss is generally ground voltage or a negative value. The reference voltage signal terminal VREF is loaded with a constant reference voltage Vref. In practical applications, the specific values ​​of the first power supply voltage Vdd, the second power supply voltage Vss, and the reference voltage Vref can be designed and determined according to the actual application environment, and are not limited here.

[0078] In embodiments of the present invention, such as Figure 4 As shown, the present invention provides a method for driving a pixel circuit, comprising the following steps:

[0079] S100, Data writing stage: The data writing circuit responds to the signal at the first control signal terminal and inputs the data voltage signal at the data signal terminal to the first node; the initialization circuit initializes the gate of the driving transistor, the second node, and the light-emitting device.

[0080] S200, Threshold voltage compensation stage: The threshold compensation circuit responds to the signal at the second control signal terminal and connects the second terminal of the driving transistor to the gate of the driving transistor; The initialization circuit initializes the gate of the driving transistor and the second node.

[0081] S300, Light emission stage: In response to the signal at the first light emission control signal terminal, the light emission control circuit connects the reference voltage signal terminal to the first node, and in response to the signal at the second light emission control signal terminal, connects the second electrode of the driving transistor to the light emission device, thereby driving the light emission device to emit light.

[0082] S400, Initialization Phase: The noise reduction circuit responds to the signal at the third control signal terminal and connects the second terminal of the driving transistor to the first node; the initialization circuit initializes the light-emitting device.

[0083] When refreshing at a low frame rate, each display frame includes a refresh frame and at least one hold frame. The data writing phase, threshold voltage compensation phase, and light emission phase are located in the refresh frame, and the initialization phase is located in the hold frame. In the hold frame, the light emission phase follows the initialization phase.

[0084] The following is based on Figure 3 Taking the pixel circuit shown as an example, combined with Figure 5 The signal timing diagram shown describes the operation of the pixel circuit provided in the embodiment of the present invention.

[0085] In embodiments of the present invention, such as Figure 5 As shown, em1 represents the first light emission control signal of the first light emission control signal terminal EM1, em2 represents the second light emission control signal of the second light emission control signal terminal EM2, cs1 represents the first control signal of the first control signal terminal CS1, cs2 represents the second control signal of the second control signal terminal CS2, cs3 represents the third control signal of the third control signal terminal CS3, and cs4 represents the fourth control signal of the fourth control signal terminal CS4.

[0086] The operation of the pixel circuit in a display frame F1 is used as an example for explanation. The display frame F1 has a refresh frame F11 and holding frames F12 to F13. The refresh frame F11 includes a data writing stage P1, a threshold voltage compensation stage P2, and an emission stage P3. The holding frames F12 to F13 include an initialization stage P4 and an emission stage P5.

[0087] In refresh frame F11, during the data writing phase P1, the first transistor T1 is turned on under the control of the low level of the fourth control signal CS4; the second transistor T2 is turned on under the control of the low level of the first control signal CS1; the third transistor T3 is turned on under the control of the low level of the first control signal CS1; the fourth transistor T4 is turned off under the control of the high level of the second control signal CS2; the twelfth transistor T12 is turned on under the control of the low level of the first control signal CS1; the thirteenth transistor T13 is turned off under the control of the high level of the second control signal CS2; the fourteenth transistor T14 is turned off under the control of the high level of the third control signal CS3; the fifteenth transistor T15 is turned off under the control of the high level of the first light emission control signal EM1; and the sixteenth transistor T16 is turned on under the control of the low level of the second light emission control signal EM2. The turned-on first transistor T1 inputs the signal from the first initialization signal terminal Vinit1 to the light-emitting device L, initializing the light-emitting device L. The second transistor T2, which is turned on, inputs the signal from the first initialization signal terminal Vinit1 to the gate of the driving transistor T0, initializing the gate of the driving transistor T0. Therefore, VT0 = VVinit1. Here, VT0 represents the gate voltage of the driving transistor T0, and VVinit1 represents the voltage value of the signal from the first initialization signal terminal Vinit1. The third transistor T3, which is turned on, inputs the first power supply voltage Vdd from the first power supply terminal VDD to the second node N2, initializing the second node N2. Therefore, VN2 = Vdd. Here, VN2 represents the voltage value of the second node N2, and Vdd represents the first power supply voltage of the first power supply terminal VDD. The sixteenth transistor T16, which is turned on, inputs the signal from the first initialization signal terminal Vinit1 to the second terminal of the driving transistor T0, initializing the second terminal of the driving transistor T0. The twelfth transistor T12, which is turned on, inputs the data voltage signal from the data signal terminal DA to the first node N1. Therefore, VN1 = Vda. Here, VN1 represents the voltage value of the first node N1, and Vda represents the voltage value of the data voltage signal from the data signal terminal DA.

[0088] During the threshold voltage compensation stage P2, the first transistor T1 is cut off under the control of the high level of the fourth control signal CS4; the second transistor T2 is cut off under the control of the high level of the first control signal CS1; the third transistor T3 is cut off under the control of the high level of the first control signal CS1; the fourth transistor T4 is turned on under the control of the low level of the second control signal CS2; the twelfth transistor T12 is cut off under the control of the high level of the first control signal CS1; the thirteenth transistor T13 is turned on under the control of the low level of the second control signal CS2; the fourteenth transistor T14 is cut off under the control of the high level of the third control signal CS3; the fifteenth transistor T15 is cut off under the control of the high level of the first light emission control signal EM1; and the sixteenth transistor T16 is cut off under the control of the high level of the second light emission control signal EM2. The turned-on fourth transistor T4 inputs the first power supply voltage Vdd from the first power supply terminal VDD to the second node N2, therefore, VN2 = Vdd, thus maintaining the voltage stability of the first node N1 through the second node N2. The thirteenth transistor T13, when turned on, connects the gate of the driving transistor T0 to its second terminal, forming a diode connection. Therefore, VT0 changes from VVinit1 to Vdd+Vth. Here, Vth represents the threshold voltage of the driving transistor T0.

[0089] During the light-emitting phase P3, the first transistor T1 is cut off under the control of the high level of the fourth control signal CS4; the second transistor T2 is cut off under the control of the high level of the first control signal CS1; the third transistor T3 is cut off under the control of the high level of the first control signal CS1; the fourth transistor T4 is cut off under the control of the high level of the second control signal CS2; the twelfth transistor T12 is cut off under the control of the high level of the first control signal CS1; the thirteenth transistor T13 is cut off under the control of the high level of the second control signal CS2; the fourteenth transistor T14 is cut off under the control of the high level of the third control signal CS3; the fifteenth transistor T15 is turned on under the control of the low level of the first light-emitting control signal EM1; and the sixteenth transistor T16 is turned on under the control of the low level of the second light-emitting control signal EM2. The turned-on fifteenth transistor T15 inputs the reference voltage Vref from the reference voltage terminal VREF to the first node N1, therefore, VN1 = Vref. Here, Vref represents the voltage value of the reference voltage at the reference voltage terminal VREF. Due to the effects of the first capacitor C1 and the second capacitor C2, the gate voltage VT0 of the driving transistor T0 changes to Vdd + Vth + Vref - Vda. The driving transistor T0 generates a driving current Ids = K(Vref - Vda). 2Where K is a structural parameter. When the sixteenth transistor T16 is turned on, it connects the second terminal of the driving transistor T0 to the anode of the light-emitting device L, so that the driving current Ids is input to the light-emitting device L, thereby driving the light-emitting device L to emit light.

[0090] In hold frame F12, during initialization phase P4, the first transistor T1 is turned on under the control of the low level of the fourth control signal CS4; the second transistor T2 is turned off under the control of the high level of the first control signal CS1; the third transistor T3 is turned off under the control of the high level of the first control signal CS1; the fourth transistor T4 is turned off under the control of the high level of the second control signal CS2; the twelfth transistor T12 is turned off under the control of the high level of the first control signal CS1; the thirteenth transistor T13 is turned off under the control of the high level of the second control signal CS2; the fourteenth transistor T14 is turned on under the control of the low level of the third control signal CS3; the fifteenth transistor T15 is turned off under the control of the high level of the first light emission control signal EM1; and the sixteenth transistor T16 is turned off under the control of the high level of the second light emission control signal EM2. The turned-on first transistor T1 inputs the signal from the first initialization signal terminal Vinit1 to the light-emitting device L, initializing the light-emitting device L. The turned-on fourteenth transistor T14 connects the first node N1 to the second terminal of the driving transistor T0. Since the driving transistor T0 is in the on state, the voltage values ​​of VN1 and VT01 gradually increase. Simultaneously, the voltage value of VT0 is pulled up through the first capacitor C1 and the second capacitor C2, bringing Vgs of the driving transistor T0 close to Vth. This achieves the off-state reset of the driving transistor T0. Here, VT01 represents the voltage value at the second terminal of the driving transistor T0, and Vgs represents the voltage difference between the gate and source of the driving transistor T0.

[0091] During the light-emitting phase P5, the first transistor T1 is cut off under the control of the high level of the fourth control signal CS4; the second transistor T2 is cut off under the control of the high level of the first control signal CS1; the third transistor T3 is cut off under the control of the high level of the first control signal CS1; the fourth transistor T4 is cut off under the control of the high level of the second control signal CS2; the twelfth transistor T12 is cut off under the control of the high level of the first control signal CS1; the thirteenth transistor T13 is cut off under the control of the high level of the second control signal CS2; the fourteenth transistor T14 is cut off under the control of the high level of the third control signal CS3; the fifteenth transistor T15 is turned on under the control of the low level of the first light-emitting control signal EM1; and the sixteenth transistor T16 is turned on under the control of the low level of the second light-emitting control signal EM2. The turned-on fifteenth transistor T15 inputs the reference voltage Vref from the reference voltage terminal VREF to the first node N1, therefore, VN1 = Vref. Here, Vref represents the voltage value of the reference voltage at the reference voltage terminal VREF. Due to the effects of the first capacitor C1 and the second capacitor C2, the gate voltage VT0 of the driving transistor T0 changes to Vdd + Vth + Vref - Vda. The driving transistor T0 generates a driving current Ids = K(Vref - Vda). 2 Where K is a structural parameter. When the sixteenth transistor T16 is turned on, it connects the second terminal of the driving transistor T0 with the anode of the light-emitting device L, so that the driving current Ids is input to the light-emitting device, thereby driving the light-emitting device to emit light.

[0092] The holding frame F13 includes an initialization phase P4 and an emission phase P5. This process is similar to the aforementioned process, so please refer to the aforementioned process for details. The repetitions will not be repeated here.

[0093] Embodiments of the present invention provide other structural schematic diagrams of pixel circuits, such as... Figure 6 As shown, this embodiment is a variation of the implementation described in the above embodiments. The following only describes the differences between this embodiment and the above embodiments; their general similarities will not be repeated here.

[0094] In embodiments of the present invention, such as Figure 6 As shown, the initialization circuit 30 is further configured to provide the signal of the second initialization signal terminal Vinit2 to the gate of the driving transistor T0 in response to the signal of the fifth control signal terminal CS5, to provide the signal of the first power supply terminal VDD to the second node N2 in response to the signal of the first light emission control signal terminal EM1, and to provide the signal of the second initialization signal terminal Vinit2 to the light emission device L in response to the signal of the sixth control signal terminal CS6.

[0095] In embodiments of the present invention, such as Figure 7As shown, the initialization circuit 30 includes a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. The gate of the fifth transistor T5 is coupled to the fifth control signal terminal CS5, the first terminal of the fifth transistor T5 is coupled to the gate of the driving transistor T0, and the second terminal of the fifth transistor T5 is coupled to the second initialization signal terminal Vinit2. The gate of the sixth transistor T6 is coupled to the sixth control signal terminal CS6, the first terminal of the sixth transistor T6 is coupled to the light-emitting device L, and the second terminal of the sixth transistor T6 is coupled to the second initialization signal terminal Vinit2. The gate of the seventh transistor T7 is coupled to the first light-emitting control signal terminal EM1, the first terminal of the seventh transistor T7 is coupled to the second node N2, and the second terminal of the seventh transistor T7 is coupled to the first power supply terminal VDD.

[0096] For example, the fifth transistor T5 can be turned on under the control of the effective level of the fifth control signal transmitted at the fifth control signal terminal CS5, and can be turned off under the control of the ineffective level of the fifth control signal. For example, if the fifth transistor T5 is set as a P-type transistor, then the effective level of the fifth control signal is low, and the ineffective level of the fifth control signal is high. Alternatively, if the fifth transistor T5 is set as an N-type transistor, then the effective level of the fifth control signal is high, and the ineffective level of the fifth control signal is low.

[0097] For example, the sixth transistor T6 can be turned on under the control of the effective level of the sixth control signal transmitted at the sixth control signal terminal CS6, and can be turned off under the control of the ineffective level of the sixth control signal. For example, if the sixth transistor T6 is set as a P-type transistor, then the effective level of the sixth control signal is low, and the ineffective level of the sixth control signal is high. Alternatively, if the sixth transistor T6 is set as an N-type transistor, then the effective level of the sixth control signal is high, and the ineffective level of the sixth control signal is low.

[0098] For example, the seventh transistor T7 can be turned on under the control of the effective level of the first light-emitting control signal transmitted at the first light-emitting control signal terminal EM1, and can be turned off under the control of the ineffective level of the first light-emitting control signal. For example, if the seventh transistor T7 is set as a P-type transistor, then the effective level of the first light-emitting control signal is low, and the ineffective level of the first light-emitting control signal is high. Alternatively, if the seventh transistor T7 is set as an N-type transistor, then the effective level of the first light-emitting control signal is high, and the ineffective level of the first light-emitting control signal is low.

[0099] The following is based on Figure 7 Taking the pixel circuit shown as an example, combined with Figure 8 The signal timing diagram shown describes the operation of the pixel circuit provided in the embodiment of the present invention.

[0100] In embodiments of the present invention, such as Figure 8 As shown, em1 represents the first light emission control signal of the first light emission control signal terminal EM1, em2 represents the second light emission control signal of the second light emission control signal terminal EM2, cs1 represents the first control signal of the first control signal terminal CS1, cs2 represents the second control signal of the second control signal terminal CS2, cs3 represents the third control signal of the third control signal terminal CS3, cs5 represents the fifth control signal of the fifth control signal terminal CS5, and cs6 represents the sixth control signal of the fifth control signal terminal CS6.

[0101] The operation of the pixel circuit in a display frame F1 is used as an example for explanation. The display frame F1 has a refresh frame F11 and holding frames F12 to F13. The refresh frame F11 includes a data writing stage P1, a threshold voltage compensation stage P2, and an emission stage P3. The holding frames F12 to F13 include an initialization stage P4 and an emission stage P5.

[0102] In refresh frame F11, during the data writing phase P1, the fifth transistor T5 is turned on under the control of the high level of the fifth control signal CS5, the sixth transistor T6 is turned on under the control of the low level of the sixth control signal CS6, the seventh transistor T7 is turned on under the control of the high level of the first light emission control signal EM1, the twelfth transistor T12 is turned on under the control of the low level of the first control signal CS1, the thirteenth transistor T13 is turned off under the control of the low level of the second control signal CS2, the fourteenth transistor T14 is turned off under the control of the low level of the third control signal CS3, the fifteenth transistor T15 is turned off under the control of the high level of the first light emission control signal EM1, and the sixteenth transistor T16 is turned off under the control of the high level of the second light emission control signal EM2. The turned-on fifth transistor T5 inputs the signal from the second initialization signal terminal Vinit2 to the gate of the driving transistor T0, initializing the gate of the driving transistor T0. Therefore, VT0 = VVinit2, where VVinit2 represents the voltage value of the signal from the second initialization signal terminal Vinit2. The sixth transistor T6, which is turned on, inputs the signal from the second initialization signal terminal Vinit2 to the light-emitting device L, thus initializing the light-emitting device L. The seventh transistor T7, which is turned on, inputs the first power supply voltage Vdd from the first power supply terminal VDD to the second node N2, thus initializing the second node N2; therefore, VN2 = Vdd. The twelfth transistor T12, which is turned on, inputs the data voltage signal from the data signal terminal DA to the first node N1; therefore, VN1 = Vda.

[0103] During the threshold voltage compensation phase P2, the fifth transistor T5 is cut off under the control of the low level of the fifth control signal CS5, the sixth transistor T6 is cut off under the control of the high level of the sixth control signal CS6, the seventh transistor T7 is turned on under the control of the high level of the first light emission control signal EM1, the twelfth transistor T12 is cut off under the control of the high level of the first control signal CS1, the thirteenth transistor T13 is turned on under the control of the high level of the second control signal CS2, the fourteenth transistor T14 is cut off under the control of the low level of the third control signal CS3, the fifteenth transistor T15 is cut off under the control of the high level of the first light emission control signal EM1, and the sixteenth transistor T16 is cut off under the control of the high level of the second light emission control signal EM2. The seven conducting transistors T7 input the first power supply voltage Vdd from the first power supply terminal VDD to the second node N2, therefore, VN2 = Vdd, thus maintaining the voltage stability of the first node N1 through the second node N2. The thirteenth transistor T13, when turned on, connects the gate of the driving transistor T0 to its second terminal, forming a diode connection. Therefore, VT0 changes from VVinit2 to Vdd+Vth. Here, VVinit2 represents the voltage value of the signal at the second initialization signal terminal Vinit2.

[0104] During the light-emitting phase P3, the fifth transistor T5 is cut off under the control of the low level of the fifth control signal CS5, the sixth transistor T6 is cut off under the control of the high level of the sixth control signal CS6, the seventh transistor T7 is cut off under the control of the low level of the first light-emitting control signal EM1, the twelfth transistor T12 is cut off under the control of the high level of the first control signal CS1, the thirteenth transistor T13 is cut off under the control of the low level of the second control signal CS2, the fourteenth transistor T14 is cut off under the control of the low level of the third control signal CS3, the fifteenth transistor T15 is turned on under the control of the low level of the first light-emitting control signal EM1, and the sixteenth transistor T16 is turned on under the control of the low level of the second light-emitting control signal EM2. The turned-on fifteenth transistor T15 inputs the reference voltage Vref from the reference voltage terminal VREF to the first node N1, therefore, VN1 = Vref. Due to the effects of the first capacitor C1 and the second capacitor C2, the gate voltage VT0 of the driving transistor T0 changes to Vdd + Vth + Vref - Vda. The driving transistor T0 generates a driving current Ids = K(Vref - Vda). 2 Where K is a structural parameter. When the sixteenth transistor T16 is turned on, it connects the second terminal of the driving transistor T0 to the anode of the light-emitting device L, so that the driving current Ids is input to the light-emitting device L, thereby driving the light-emitting device L to emit light.

[0105] In hold frame F12, during initialization phase P4, the fifth transistor T5 is turned off under the control of the low level of the fifth control signal CS5, the sixth transistor T6 is turned on under the control of the low level of the sixth control signal CS6, the seventh transistor T7 is turned on under the control of the high level of the first light emission control signal EM1, the twelfth transistor T12 is turned off under the control of the high level of the first control signal CS1, the thirteenth transistor T13 is turned off under the control of the low level of the second control signal CS2, the fourteenth transistor T14 is turned on under the control of the high level of the third control signal CS3, the fifteenth transistor T15 is turned off under the control of the high level of the first light emission control signal EM1, and the sixteenth transistor T16 is turned off under the control of the high level of the second light emission control signal EM2. The turned-on sixth transistor T6 inputs the signal from the second initialization signal terminal Vinit2 to the light-emitting device L, initializing the light-emitting device L. The turned-on seventh transistor T7 inputs the first power supply voltage Vdd from the first power supply terminal VDD to the second node N2, initializing the second node N2. The fourteenth transistor T14, when turned on, connects the first node N1 to the second terminal of the driving transistor T0. Since the driving transistor T0 is in the on state, the voltage values ​​VN1 and VT01 gradually increase. Simultaneously, the voltage value of VT0 is pulled up through the first capacitor C1 and the second capacitor C2, making Vgs of the driving transistor T0 close to Vth. This achieves the off-state reset of the driving transistor T0.

[0106] During the light-emitting phase P3, the fifth transistor T5 is cut off under the control of the low level of the fifth control signal CS5, the sixth transistor T6 is cut off under the control of the high level of the sixth control signal CS6, the seventh transistor T7 is cut off under the control of the low level of the first light-emitting control signal EM1, the twelfth transistor T12 is cut off under the control of the high level of the first control signal CS1, the thirteenth transistor T13 is cut off under the control of the low level of the second control signal CS2, the fourteenth transistor T14 is cut off under the control of the low level of the third control signal CS3, the fifteenth transistor T15 is turned on under the control of the low level of the first light-emitting control signal EM1, and the sixteenth transistor T16 is turned on under the control of the low level of the second light-emitting control signal EM2. The turned-on fifteenth transistor T15 inputs the reference voltage Vref from the reference voltage terminal VREF to the first node N1, therefore, VN1 = Vref. Due to the effects of the first capacitor C1 and the second capacitor C2, the gate voltage VT0 of the driving transistor T0 changes to Vdd + Vth + Vref - Vda. The driving transistor T0 generates a driving current Ids = K(Vref - Vda). 2 Where K is a structural parameter. When the sixteenth transistor T16 is turned on, it connects the second terminal of the driving transistor T0 with the anode of the light-emitting device L, so that the driving current Ids is input to the light-emitting device, thereby driving the light-emitting device to emit light.

[0107] The holding frame F13 includes an initialization phase P4 and an emission phase P5. This process is similar to the aforementioned process, so please refer to the aforementioned process for details. The repetitions will not be repeated here.

[0108] This invention provides other schematic diagrams of pixel circuit structures, such as... Figure 9 As shown, this embodiment is a variation of the implementation described in the above embodiments. The following only describes the differences between this embodiment and the above embodiments; their general similarities will not be repeated here.

[0109] In this embodiment of the invention, the first light-emitting control signal terminal EM1 and the second light-emitting control signal terminal EM2 can be the same signal terminal. For example, as... Figure 9 As shown, the gate of the sixteenth transistor T16 is coupled to the first light-emitting control signal terminal EM1.

[0110] Figure 9 The signal timing diagram corresponding to the pixel circuit shown can be as follows: Figure 10 As shown. The driving process of this embodiment is similar to the driving process of the aforementioned pixel circuit. Therefore, the driving process of this embodiment can be referred to the driving process of the aforementioned pixel circuit, and the repeated parts will not be described again here.

[0111] Embodiments of the present invention provide other structural schematic diagrams of pixel circuits, such as... Figure 11 As shown, this embodiment is a variation of the implementation described in the above embodiments. The following only describes the differences between this embodiment and the above embodiments; their general similarities will not be repeated here.

[0112] In embodiments of the present invention, such as Figure 11 As shown, the initialization circuit 30 is further configured to provide the signal of the third initialization signal terminal Vinit3 to the gate of the driving transistor T0 in response to the signals of the first control signal terminal CS1 and the seventh control signal terminal CS7, provide the signal of the first power supply terminal VDD to the second node N2 in response to the signal of the seventh control signal terminal CS7, and provide the signal of the third initialization signal terminal Vinit3 to the light-emitting device L in response to the signal of the eighth control signal terminal CS8.

[0113] In embodiments of the present invention, such as Figure 12As shown, the initialization circuit 30 includes an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and an eleventh transistor T11. The gate of the eighth transistor T8 is coupled to the eighth control signal terminal CS8, the first terminal of the eighth transistor T8 is coupled to the third initialization signal terminal Vinit3, and the second terminal of the eighth transistor T8 is coupled to the light-emitting device L. The gate of the ninth transistor T9 is coupled to the first control signal terminal CS1, the first terminal of the ninth transistor T9 is coupled to the threshold compensation circuit 20, and the second terminal of the ninth transistor T9 is coupled to the third initialization signal terminal Vinit3. The gate of the tenth transistor T10 is coupled to the seventh control signal terminal CS7, the first terminal of the tenth transistor T10 is coupled to the gate of the driving transistor T0, and the second terminal of the tenth transistor T10 is coupled to the first terminal of the ninth transistor T9. The gate of the eleventh transistor T11 is coupled to the seventh control signal terminal CS7, the first terminal of the eleventh transistor T11 is coupled to the second node N2, and the second terminal of the eleventh transistor T11 is coupled to the first power supply terminal VDD.

[0114] For example, the eighth transistor T8 can be turned on under the control of the effective level of the eighth control signal transmitted at the eighth control signal terminal CS8, and can be turned off under the control of the ineffective level of the eighth control signal. For example, if the eighth transistor T8 is set as a P-type transistor, then the effective level of the eighth control signal is low, and the ineffective level of the eighth control signal is high. Alternatively, if the eighth transistor T8 is set as an N-type transistor, then the effective level of the eighth control signal is high, and the ineffective level of the eighth control signal is low.

[0115] For example, the ninth transistor T9 can be turned on under the control of the effective level of the first control signal transmitted at the first control signal terminal CS1, and can be turned off under the control of the ineffective level of the first control signal. For example, if the ninth transistor T9 is configured as a P-type transistor, then the effective level of the first control signal is low, and the ineffective level of the first control signal is high. Alternatively, if the ninth transistor T9 is configured as an N-type transistor, then the effective level of the first control signal is high, and the ineffective level of the first control signal is low.

[0116] For example, the tenth transistor T10 can be turned on under the control of the effective level of the seventh control signal transmitted at the seventh control signal terminal CS7, and can be turned off under the control of the ineffective level of the seventh control signal. For example, if the tenth transistor T10 is set as a P-type transistor, then the effective level of the seventh control signal is low, and the ineffective level of the seventh control signal is high. Alternatively, if the tenth transistor T10 is set as an N-type transistor, then the effective level of the seventh control signal is high, and the ineffective level of the seventh control signal is low.

[0117] For example, the eleventh transistor T11 can be turned on under the control of the effective level of the seventh control signal transmitted at the seventh control signal terminal CS7, and can be turned off under the control of the ineffective level of the seventh control signal. For example, if the eleventh transistor T11 is set as a P-type transistor, then the effective level of the seventh control signal is low, and the ineffective level of the seventh control signal is high. Alternatively, if the eleventh transistor T11 is set as an N-type transistor, then the effective level of the seventh control signal is high, and the ineffective level of the seventh control signal is low.

[0118] The following is based on Figure 12 Taking the pixel circuit shown as an example, combined with Figure 13 The signal timing diagram shown describes the operation of the pixel circuit provided in the embodiment of the present invention.

[0119] In embodiments of the present invention, such as Figure 13 As shown, em1 represents the first light emission control signal of the first light emission control signal terminal EM1, em2 represents the second light emission control signal of the second light emission control signal terminal EM2, cs1 represents the first control signal of the first control signal terminal CS1, cs2 represents the second control signal of the second control signal terminal CS2, cs3 represents the third control signal of the third control signal terminal CS3, cs7 represents the seventh control signal of the seventh control signal terminal CS7, and cs8 represents the eighth control signal of the eighth control signal terminal CS8.

[0120] The operation of the pixel circuit in a display frame F1 is used as an example for explanation. The display frame F1 has a refresh frame F11 and holding frames F12 to F13. The refresh frame F11 includes a data writing stage P1, a threshold voltage compensation stage P2, and an emission stage P3. The holding frames F12 to F13 include an initialization stage P4 and an emission stage P5.

[0121] In refresh frame F11, during the data writing phase P1, the eighth transistor T8 is turned on under the control of the low level of the eighth control signal CS8, the ninth transistor T9 is turned on under the control of the low level of the first control signal CS1, the tenth transistor T10 is turned off under the control of the low level of the seventh control signal CS7, the eleventh transistor T11 is turned off under the control of the low level of the seventh control signal CS7, the twelfth transistor T12 is turned on under the control of the low level of the first control signal CS1, the thirteenth transistor T13 is turned off under the control of the high level of the second control signal CS2, the fourteenth transistor T14 is turned off under the control of the low level of the third control signal CS3, the fifteenth transistor T15 is turned off under the control of the high level of the first light emission control signal EM1, and the sixteenth transistor T16 is turned on under the control of the low level of the second light emission control signal EM2. The turned-on eighth transistor T8 inputs the signal from the third initialization signal terminal Vinit3 to the light-emitting device L, initializing the light-emitting device L. The turned-on ninth transistor T9 inputs the signal from the third initialization signal terminal Vinit3 to the second terminal of the tenth transistor T10. The sixteenth transistor T16, which is turned on, inputs the signal from the third initialization signal terminal Vinit3 to the second terminal of the driving transistor T0, thus initializing the second terminal of the driving transistor T0. The twelfth transistor T12, which is turned on, inputs the data voltage signal from the data signal terminal DA to the first node N1, so VN1 = Vda.

[0122] During the threshold voltage compensation phase P2, the eighth transistor T8 is cut off under the control of the high level of the eighth control signal CS8; the ninth transistor T9 is cut off under the control of the high level of the first control signal CS1; the tenth transistor T10 is turned on under the control of the high level of the seventh control signal CS7; the eleventh transistor T11 is turned on under the control of the high level of the seventh control signal CS7; the twelfth transistor T12 is cut off under the control of the high level of the first control signal CS1; the thirteenth transistor T13 is turned on under the control of the low level of the second control signal CS2; the fourteenth transistor T14 is cut off under the control of the low level of the third control signal CS3; the fifteenth transistor T15 is cut off under the control of the high level of the first light emission control signal EM1; and the sixteenth transistor T16 is cut off under the control of the high level of the second light emission control signal EM2. The turned-on tenth transistor T10 inputs the signal from its second terminal to the gate of the driving transistor T0, initializing the gate of the driving transistor T0. The eleventh transistor T11, when turned on, inputs the first power supply voltage Vdd from the first power supply terminal VDD to the second node N2. Therefore, VN2 = Vdd, thus maintaining the voltage stability of the first node N1 through the second node N2. The thirteenth transistor T13, when turned on, connects the gate of the driving transistor T0 to its second terminal, forming a diode connection. Therefore, VT0 changes from VVinit3 to Vdd + Vth. Here, VVinit3 represents the voltage value of the signal at the third initialization signal terminal Vinit1.

[0123] During the light-emitting phase P3, the eighth transistor T8 is cut off under the control of the high level of the eighth control signal CS8; the ninth transistor T9 is cut off under the control of the high level of the first control signal CS1; the tenth transistor T10 is cut off under the control of the low level of the seventh control signal CS7; the eleventh transistor T11 is cut off under the control of the low level of the seventh control signal CS7; the twelfth transistor T12 is cut off under the control of the high level of the first control signal CS1; the thirteenth transistor T13 is cut off under the control of the high level of the second control signal CS2; the fourteenth transistor T14 is cut off under the control of the low level of the third control signal CS3; the fifteenth transistor T15 is turned on under the control of the low level of the first light-emitting control signal EM1; and the sixteenth transistor T16 is turned on under the control of the low level of the second light-emitting control signal EM2. The turned-on fifteenth transistor T15 inputs the reference voltage Vref from the reference voltage terminal VREF to the first node N1, therefore, VN1 = Vref. Due to the effects of the first capacitor C1 and the second capacitor C2, the gate voltage VT0 of the driving transistor T0 changes to Vdd + Vth + Vref - Vda. The driving transistor T0 generates a driving current Ids = K(Vref - Vda). 2Where K is a structural parameter. When the sixteenth transistor T16 is turned on, it connects the second terminal of the driving transistor T0 with the anode of the light-emitting device L, so that the driving current Ids is input into the light-emitting device L, thereby driving the light-emitting device L to emit light.

[0124] In hold frame F12, during initialization phase P4, the eighth transistor T8 is turned on under the control of the low level of the eighth control signal CS8; the ninth transistor T9 is turned off under the control of the high level of the first control signal CS1; the tenth transistor T10 is turned off under the control of the low level of the seventh control signal CS7; the eleventh transistor T11 is turned off under the control of the low level of the seventh control signal CS7; the twelfth transistor T12 is turned off under the control of the high level of the first control signal CS1; the thirteenth transistor T13 is turned off under the control of the high level of the second control signal CS2; the fourteenth transistor T14 is turned on under the control of the high level of the third control signal CS3; the fifteenth transistor T15 is turned off under the control of the high level of the first light emission control signal EM1; and the sixteenth transistor T16 is turned off under the control of the high level of the second light emission control signal EM2. The turned-on eighth transistor T8 inputs the signal from the third initialization signal terminal Vinit3 to the light-emitting device L, initializing the light-emitting device L. The turned-on fourteenth transistor T14 connects the first node N1 to the second terminal of the driving transistor T0. Since the driving transistor T0 is in the on state, the voltage values ​​of VN1 and VT01 gradually increase. At the same time, the voltage value of VT0 is pulled up through the first capacitor C1 and the second capacitor C2, so that Vgs of the driving transistor T0 is close to Vth. This achieves the off-state reset of the driving transistor T0.

[0125] During the light-emitting phase P5, the eighth transistor T8 is cut off under the control of the high level of the eighth control signal CS8; the ninth transistor T9 is cut off under the control of the high level of the first control signal CS1; the tenth transistor T10 is cut off under the control of the low level of the seventh control signal CS7; the eleventh transistor T11 is cut off under the control of the low level of the seventh control signal CS7; the twelfth transistor T12 is cut off under the control of the high level of the first control signal CS1; the thirteenth transistor T13 is cut off under the control of the high level of the second control signal CS2; the fourteenth transistor T14 is cut off under the control of the low level of the third control signal CS3; the fifteenth transistor T15 is turned on under the control of the low level of the first light-emitting control signal EM1; and the sixteenth transistor T16 is turned on under the control of the low level of the second light-emitting control signal EM2. The turned-on fifteenth transistor T15 inputs the reference voltage Vref from the reference voltage terminal VREF to the first node N1, therefore, VN1 = Vref. Due to the effects of the first capacitor C1 and the second capacitor C2, the gate voltage VT0 of the driving transistor T0 changes to Vdd + Vth + Vref - Vda. The driving transistor T0 generates a driving current Ids = K(Vref - Vda).2 Where K is a structural parameter. When the sixteenth transistor T16 is turned on, it connects the second terminal of the driving transistor T0 with the anode of the light-emitting device L, so that the driving current Ids is input into the light-emitting device L, thereby driving the light-emitting device L to emit light.

[0126] The holding frame F13 includes an initialization phase P4 and an emission phase P5. This process is similar to the aforementioned process, so please refer to the aforementioned process for details. The repetitions will not be repeated here.

[0127] This invention also provides a display panel including a plurality of sub-pixels; wherein each sub-pixel includes the aforementioned pixel circuit. The principle by which this display device solves the problem is similar to that of the aforementioned pixel circuit, therefore, the implementation of this display device can refer to the implementation of the aforementioned pixel circuit, and the repeated parts will not be described again here.

[0128] Based on the same inventive concept, embodiments of the present invention also provide a display device, including the display panel described above in the embodiments of the present invention. The principle by which this display device solves the problem is similar to that of the aforementioned display panel; therefore, the implementation of this display device can refer to the implementation of the aforementioned display panel, and the repeated parts will not be described again here.

[0129] In specific implementations, in the embodiments of the present invention, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting the present invention.

[0130] The above are merely examples illustrating the specific structures of each module in the pixel circuit provided in the embodiments of the present invention. In specific implementation, the above-mentioned specific structures are not limited to the structures provided in the embodiments of the present invention, and may also be other structures known to those skilled in the art, which are not limited here.

[0131] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0132] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations to the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include these modifications and variations.

Claims

1. A pixel circuit, characterized in that, include, Light-emitting devices; The driving transistor is configured to generate a driving current that drives the light-emitting device to emit light based on a data voltage signal; The data writing circuit is configured to input the data voltage signal from the data signal terminal to the first node in response to a signal from the first control signal terminal. A threshold compensation circuit is configured to turn on the second terminal of the driving transistor and the gate of the driving transistor in response to a signal at the second control signal terminal. An initialization circuit is configured to initialize the gate, second node, and light-emitting device of the driving transistor. The noise reduction circuit is configured to, in response to a signal at the third control signal terminal, connect the second terminal of the driving transistor to the first node. The light-emitting control circuit is configured to connect the reference voltage signal terminal to the first node in response to a signal at the first light-emitting control signal terminal, and to connect the second terminal of the driving transistor to the light-emitting device in response to a signal at the second light-emitting control signal terminal, thereby driving the light-emitting device to emit light. The first storage circuit includes a first capacitor; a first electrode of the first capacitor is coupled to the first node, and a second electrode of the first capacitor is coupled to the second node. The second storage circuit includes a second capacitor; the first electrode of the second capacitor is coupled to the second node, and the second electrode of the second capacitor is coupled to the gate of the driving transistor. The initialization circuit is further configured to provide the signal of the third initialization signal terminal to the gate of the driving transistor in response to the signals of the first control signal terminal and the seventh control signal terminal, to provide the signal of the first power supply terminal to the second node in response to the signal of the seventh control signal terminal, and to provide the signal of the third initialization signal terminal to the light-emitting device in response to the signal of the eighth control signal terminal. The initialization circuit includes an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor; The gate of the eighth transistor is coupled to the eighth control signal terminal, the first terminal of the eighth transistor is coupled to the third initialization signal terminal, and the second terminal of the eighth transistor is coupled to the light-emitting device. The gate of the ninth transistor is coupled to the first control signal terminal, the first terminal of the ninth transistor is coupled to the threshold compensation circuit, and the second terminal of the ninth transistor is coupled to the third initialization signal terminal. The gate of the tenth transistor is coupled to the seventh control signal terminal, the first terminal of the tenth transistor is coupled to the gate of the driving transistor, and the second terminal of the tenth transistor is coupled to the first terminal of the ninth transistor. The gate of the eleventh transistor is coupled to the seventh control signal terminal, the first terminal of the eleventh transistor is coupled to the second node, and the second terminal of the eleventh transistor is coupled to the first power supply terminal. The noise reduction circuit includes a fourteenth transistor, which is in a conducting state during the initialization phase; The gate of the fourteenth transistor is coupled to the third control signal terminal, the first electrode of the fourteenth transistor is coupled to the first electrode of the first capacitor, and the second electrode of the fourteenth transistor is coupled to the second electrode of the driving transistor. The light-emitting control circuit includes a fifteenth transistor, which is in the on state during the light-emitting phase; The gate of the fifteenth transistor is coupled to the first light-emitting control signal terminal, the first terminal of the fifteenth transistor is coupled to the reference voltage signal terminal, and the second terminal of the fifteenth transistor is coupled to the first node.

2. The pixel circuit as described in claim 1, characterized in that, The data writing circuit includes a twelfth transistor; The gate of the twelfth transistor is coupled to the first control signal terminal, the first terminal of the twelfth transistor is coupled to the data signal terminal, and the second terminal of the twelfth transistor is coupled to the first node.

3. The pixel circuit as described in claim 1, characterized in that, The threshold compensation circuit includes a thirteenth transistor; The gate of the thirteenth transistor is coupled to the second control signal terminal, the first terminal of the thirteenth transistor is coupled to the gate of the driving transistor, and the second terminal of the thirteenth transistor is coupled to the second terminal of the driving transistor.

4. The pixel circuit as described in claim 1, characterized in that, The light-emitting control circuit also includes a sixteenth transistor; The gate of the sixteenth transistor is coupled to the second light-emitting control signal terminal, the first terminal of the sixteenth transistor is coupled to the second terminal of the driving transistor, and the second terminal of the sixteenth transistor is coupled to the light-emitting device.

5. A display panel, characterized in that, Includes the pixel circuit as described in any one of claims 1-4.

6. A display device, characterized in that, Includes the display panel as described in claim 5.

7. A driving method for a pixel circuit as described in any one of claims 1-4, characterized in that, include: During the data writing phase, the data writing circuit responds to the signal at the first control signal terminal and inputs the data voltage signal at the data signal terminal into the first node. The initialization circuit initializes the gate of the driving transistor, the second node, and the light-emitting device. During the threshold voltage compensation phase, the threshold compensation circuit responds to the signal at the second control signal terminal by connecting the second terminal of the driving transistor to the gate of the driving transistor; the initialization circuit initializes the gate of the driving transistor and the second node. During the light-emitting stage, the light-emitting control circuit responds to the signal at the first light-emitting control signal terminal by connecting the reference voltage signal terminal to the first node, and responds to the signal at the second light-emitting control signal terminal by connecting the second electrode of the driving transistor to the light-emitting device, thereby driving the light-emitting device to emit light; During the initialization phase, the noise reduction circuit responds to the signal at the third control signal terminal and connects the second terminal of the driving transistor to the first node; the initialization circuit initializes the light-emitting device.

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