A method for preparing silicon on insulator

Abstract

The present invention provides a method for preparing silicon on insulator. An intrinsic silicon first etch stop layer, a germanium silicon alloy second etch stop layer, and a silicon device layer are formed in a stacked manner from bottom to top on a p-type doped single crystal silicon epitaxial substrate. After oxidation, bonding, reinforcement, and grinding treatments, selective etching is carried out. Through the selective etching of p+ / intrinsic silicon, the thickness deviation of the intrinsic silicon first etch stop layer located on the germanium silicon alloy second etch stop layer is controlled within 100 nm. Subsequently, through the second etching and the third etching, the thickness deviation of the finally prepared silicon on insulator thin film can be optimized to be less than 5 nm, and the surface roughness is less than, thereby realizing the planarization preparation of the silicon on insulator thin film.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductors and relates to a method for preparing silicon on insulator. Background Art

[0002] With the continuous development of integrated circuits, the feature size of electronic components has been continuously reduced. Taking this as an opportunity, the FinFET technology and the SOI technology developed are currently the two mainstream routes.

[0003] Among them, with the development of the SOI technology, the demand for SOI substrate materials has been increasing day by day. Usually, SOI consists of a support substrate, an insulating layer, and a device layer. Currently, the preparation methods mainly include the bonding and back etching technology (BESOI), the separation by implanted oxygen technology (SIMOX), and the Smartcut TM technology.

[0004] The working principle of BESOI is as follows: By the different etching selectivity ratios of the etching stop layer and the device layer to the etching solution, the uniformity of the top silicon thickness can be effectively improved. Among them, the thickness uniformity before etching and the etching selectivity ratio have a very large impact on the thickness uniformity after etching. Therefore, it is necessary to strictly control the thickness uniformity before etching. In the prior art, usually, mechanical grinding and further mechanical chemical polishing can improve the thickness deviation of the etching stop layer to about <0.2>μm, but this thickness deviation is still relatively large, and it is difficult to continue to improve, and it is still difficult to meet the demand for planarized silicon on insulator. Summary of the Invention

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a method for preparing silicon on insulator, which is used to solve the problem of the thickness uniformity of silicon on insulator in the prior art.

[0006] To achieve the above-mentioned purpose and other related purposes, the present invention provides a method for preparing silicon on insulator, including the following steps:

[0007] Provide an epitaxial substrate and a support substrate, and the epitaxial substrate is a p-type doped single crystal silicon epitaxial substrate;

[0008] On the epitaxial substrate, form a first etching stop layer, a second etching stop layer, and a device layer stacked from bottom to top by the epitaxial method. Among them, the first etching stop layer is an intrinsic silicon layer, the second etching stop layer is a germanium-silicon alloy layer, and the device layer is a silicon device layer;

[0009] Form an insulating layer, and bond the device layer to the support substrate in combination with the insulating layer;

[0010] Grind the epitaxial substrate, and reserve a certain thickness of the epitaxial substrate;

[0011] Perform the first etching using a first etching solution to remove the remaining epitaxial substrate.

[0012] Perform the second etching using a second etching solution to remove the first etch stop layer.

[0013] Perform the third etching using a third etching solution to remove the second etch stop layer, forming a silicon-on-insulator structure; perform sacrificial oxidation on the silicon-on-insulator structure to remove part of the device layer, and perform heat treatment to obtain a silicon-on-insulator thin film. Optionally, the epitaxial substrate includes a p-type heavily doped single-crystalline silicon epitaxial substrate; the support substrate includes one of a silicon support substrate, a sapphire support substrate, a quartz support substrate, and a glass support substrate; the device layer includes a doped silicon device layer. Optionally, when epitaxially forming the first etch stop layer, the epitaxial temperature ≤ 1200 °C, and the epitaxial thickness of the formed first etch stop layer ≤ 1000 nm; when epitaxially forming the second etch stop layer, the epitaxial temperature ≤ 800 °C, the epitaxial thickness of the formed second etch stop layer is 10 nm to 60 nm, and the formed second etch stop layer is Ge x Si yLayer, where the value of x ranges from 0.1 to 0.5, and the value of y ranges from 1 to x; when epitaxially forming the device layer, the epitaxial temperature < 800 °C, and the epitaxial thickness of the formed device layer ≤ 600 nm. Optionally, the insulating layer is formed on one or a combination of the surfaces of the device layer and the support substrate. Optionally, when bonding the device layer to the support substrate in combination with the insulating layer, it includes the steps of performing surface oxygen plasma treatment and reinforcement treatment. Optionally, the method of grinding the epitaxial substrate includes one or a combination of mechanical grinding and chemical mechanical grinding, the reserved thickness of the epitaxial substrate ≤ 2 μm, and the thickness deviation of the epitaxial substrate < 0.5 μm. Optionally, the first etching solution includes a mixed etching solution of HF, HNO3, and Hac; the second etching solution includes TMAH; the third etching solution includes a mixed etching solution of HF, HNO3, and Hac or a mixed etching solution of HF, H2O2, and Hac. Optionally, the step of performing the sacrificial oxidation treatment includes one or a combination of dry oxygen or wet oxygen, where the oxidation temperature is 700 °C to 1100 °C, and after the oxidation process ends, the surface oxide layer is removed using an HF solution. Optionally, when performing the heat treatment, it includes performing rapid heat treatment, long-time heat treatment, or alternating between the two, where the temperature range of the rapid heat treatment is 1150 - 1300 °C, the temperature range of the long-time heat treatment is 1050 - 1250 °C, and the atmosphere of the heat treatment includes a hydrogen-argon mixed atmosphere or a pure argon atmosphere. Optionally, after performing the sacrificial oxidation treatment and the heat treatment on the silicon-on-insulator structure, the thickness deviation of the obtained silicon-on-insulator thin film < 5 nm, and the surface roughness of the obtained silicon-on-insulator thin film Optionally, it further includes the step of performing oxidation thinning or epitaxial growth on the silicon-on-insulator thin film to adjust the thickness of the silicon-on-insulator thin film. As described above, the method for preparing silicon-on-insulator of the present invention forms an intrinsic silicon first etch stop layer, a germanium-silicon alloy second etch stop layer, and a silicon device layer stacked from bottom to top on a p-type doped single-crystalline silicon epitaxial substrate. After oxidation, bonding, reinforcement, and grinding treatments, selective etching is performed. Through the selective etching of p+ / intrinsic silicon, the thickness deviation of the intrinsic silicon first etch stop layer located on the germanium-silicon alloy second etch stop layer is controlled within 100 nm. Subsequently, through the second etching and the third etching, the thickness deviation of the finally prepared silicon-on-insulator thin film can be optimized to less than 5 nm, and the surface roughness is less than Thus, the flat preparation of the silicon-on-insulator thin film is achieved. Description of the Drawings

[0014] Figure 1 It shows a process schematic diagram for preparing silicon-on-insulator in an embodiment of the present invention.

[0015] Figure 2 It shows a schematic structural diagram of the epitaxial substrate in the embodiment of the present invention.

[0016] Figure 3 It shows a schematic structural diagram after forming a first etch stop layer, a second etch stop layer, and a device layer on the epitaxial substrate in the embodiment of the present invention.

[0017] Figure 4 It shows a schematic structural diagram after forming an insulating layer in the embodiment of the present invention.

[0018] Figure 5 It shows a schematic structural diagram after bonding the device layer to the support substrate in the embodiment of the present invention.

[0019] Figure 6 It shows a schematic structural diagram after grinding the epitaxial substrate in the embodiment of the present invention.

[0020] Figure 7 It shows a schematic structural diagram after performing the first etching to remove the epitaxial substrate in the embodiment of the present invention.

[0021] Figure 8 It shows a schematic structural diagram after performing the second etching to remove the first etch stop layer in the embodiment of the present invention.

[0022] Figure 9 It shows a schematic structural diagram after performing the third etching to remove the second etch stop layer to form a silicon-on-insulator structure in the embodiment of the present invention.

[0023] Figure 10 It shows a schematic structural diagram after performing sacrificial oxidation treatment and heat treatment on the silicon-on-insulator structure in the embodiment of the present invention.

[0024] Description of component labels

[0025] 100 Epitaxial substrate

[0026] 200 First etch stop layer

[0027] 300 Second etch stop layer

[0028] 400 Device layer

[0029] 410 Silicon-on-insulator thin film

[0030] 500 Insulating layer

[0031] 600 Support substrate Detailed implementation manners

[0032] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0033] When detailing the embodiments of the present invention, for the convenience of description, the cross-sectional views showing the device structure will be enlarged locally in a non-general proportion, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention here. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.

[0034] For the convenience of description, spatial relationship terms such as "beneath", "below", "lower than", "under", "above", "on" may be used herein to describe the relationship between an element or feature shown in the drawings and other elements or features. It will be understood that these spatial relationship terms are intended to include other directions of the device in use or operation in addition to the directions depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can be one or more intervening layers.

[0035] In the context of the present application, the structure in which the first feature is "above" the second feature described may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0036] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0037] Refer to Figure 1 , this embodiment provides a method for preparing silicon on insulator, including the following steps:

[0038] S1: Provide an epitaxial substrate and a support substrate, where the epitaxial substrate is a p-type doped single-crystal silicon epitaxial substrate;

[0039] S2: Form a first etch stop layer, a second etch stop layer, and a device layer stacked from bottom to top on the epitaxial substrate by epitaxy. Among them, the first etch stop layer is an intrinsic silicon layer, the second etch stop layer is a germanium-silicon alloy layer, and the device layer is a silicon device layer;

[0040] S3: Form an insulating layer, and bond the device layer to the support substrate in combination with the insulating layer;

[0041] S4: Grind the epitaxial substrate, and reserve a certain thickness of the epitaxial substrate;

[0042] S5: Perform a first etching using a first etching solution to remove the remaining epitaxial substrate;

[0043] S6: Perform a second etching using a second etching solution to remove the first etching stop layer;

[0044] S7: Perform a third etching using a third etching solution to remove the second etching stop layer, and form a silicon-on-insulator structure;

[0045] S8: Perform a sacrificial oxidation treatment on the silicon-on-insulator structure, remove a part of the device layer, and perform a heat treatment to obtain a silicon-on-insulator thin film.

[0046] In this embodiment, an intrinsic silicon first etching stop layer, a germanium-silicon alloy second etching stop layer, and a silicon device layer are stacked from bottom to top on a p-type doped single-crystalline silicon epitaxial substrate. After oxidation, bonding, reinforcement, and grinding treatments, selective etching is performed. Through the selective etching of p+ / intrinsic silicon, the thickness deviation of the intrinsic silicon first etching stop layer located on the germanium-silicon alloy second etching stop layer is controlled within 100 nm. Subsequently, through the second etching and the third etching, the thickness deviation of the finally prepared silicon-on-insulator thin film can be optimized to less than 5 nm, and the surface roughness is less than Thus, the planarized preparation of the silicon-on-insulator thin film is realized.

[0047] The following combines Figures 2 to 10 , and further introduces the preparation of the silicon-on-insulator.

[0048] First, refer to Figure 2 and Figure 5 , and execute step S1 to provide an epitaxial substrate 100 and a support substrate 600.

[0049] As an example, the epitaxial substrate 100 may include a p-type heavily doped (p+) single-crystalline silicon epitaxial substrate, and the support substrate 600 may include one of a silicon support substrate, a sapphire support substrate, a quartz support substrate, and a glass support substrate.

[0050] Specifically, in this embodiment, the epitaxial substrate 100 is a p-type heavily doped boron single-crystalline silicon with a resistivity less than 0.1 Ω·m, but the type of the epitaxial substrate 100 is not limited thereto; the support substrate 600 mainly plays a supporting role, and the material selection range is relatively wide, and no excessive limitation is made here. The epitaxial substrate 100 and the support substrate 600 can be flexibly selected according to needs.

[0051] Next, referring to Figure 3 , step S2 is performed to form, by epitaxy on the epitaxial substrate 100, a first etch stop layer 200, a second etch stop layer 300, and a device layer 400 stacked from bottom to top. Among them, the first etch stop layer 200 is an intrinsic silicon layer, the second etch stop layer 300 is a germanium-silicon alloy layer, and the device layer 400 is a silicon device layer.

[0052] As an example, when epitaxially forming the first etch stop layer 200, the epitaxial temperature of the formed first etch stop layer 200 is ≤1200 °C, and the epitaxial thickness is ≤1000 nm; when epitaxially forming the second etch stop layer 300, the epitaxial temperature is ≤800 °C, the epitaxial thickness of the formed second etch stop layer 300 is 10 nm - 60 nm, and the formed second etch stop layer 300 is a Ge x Si y layer, where the value of x is 0.1 - 0.5, and the value of y is 1 - x; when epitaxially forming the device layer 400, the epitaxial thickness of the formed device layer 400 is ≤600 nm, and the epitaxial temperature is <800 °C.

[0053] Specifically, since the diffusion coefficient of germanium in the germanium-silicon alloy is extremely low at high temperatures, it is not easy to damage the clear interface between the etch stop layer / device layer during heat treatment processes such as thermal oxidation, and effective stopping of selective etching can be achieved. In addition, germanium atoms do not have an obvious impact on the electrical properties of silicon. Therefore, the second etch stop layer 300 in contact with the device layer 400 is preferably made of a germanium-silicon alloy. Further, in order to prevent the thermal diffusion of impurity atoms in the etch stop layer, the thermal budget needs to be strictly controlled. When using a germanium-silicon alloy as the second etch stop layer 300, the etch selectivity is closely related to the germanium content in the germanium-silicon alloy. The greater the germanium content, the higher the etch selectivity. However, on the other hand, the greater the germanium content means that the germanium-silicon alloy is more likely to relax and is likely to introduce additional defects in the device layer 400. Therefore, a compromise balance needs to be made between these two aspects.

[0054] In this embodiment, the first etch stop layer 200 is preferably an intrinsic silicon layer with a resistivity of not less than 10 Ω·m. The epitaxial thickness of the first etch stop layer 200 is not higher than 1000 nm, and can be, for example, 500 nm, 800 nm, 1000 nm, etc. The epitaxial temperature is not higher than 1200 °C, and can be, for example, 800 °C, 1000 °C, 1200 °C, etc. The epitaxial process can be atmospheric pressure epitaxy or reduced pressure epitaxy, and the epitaxial precursor can be DCS or TCS.

[0055] The second etch stop layer 300 is a germanium-silicon alloy Ge x Si y, where the value of germanium content x can be 0.1, 0.2, 0.25, 0.4, 0.5, etc., the thickness of the second etch stop layer 300 can be 10 nm to 60 nm, such as 10 nm, 20 nm, 30 nm, 50 nm, 60 nm, etc., the epitaxial temperature is not higher than 800 °C, such as 600 °C, 700 °C, 800 °C, etc., preferably the thickness of the second etch stop layer 300 is 30 nm to 50 nm, and the germanium content x is preferably 0.2 to 0.3. The epitaxial process can be reduced-pressure epitaxy, and the epitaxial precursors of silicon and germanium can be DCS and GeH4 respectively.

[0056] The device layer 400 epitaxially formed on the second etch stop layer 300 can be a doped silicon device layer. The doping concentration of the device layer 400 depends on the specific requirements of the subsequent formed silicon-on-insulator thin film 410. To ensure the thickness uniformity of the silicon-on-insulator thin film 410, the epitaxial thickness of the device layer 400 is not higher than 600 nm, such as 400 nm, 500 nm, 600 nm, etc., the epitaxial temperature is lower than 800 °C, such as 700 °C, 600 °C, 500 °C, etc., the epitaxial process can be reduced-pressure epitaxy, and the epitaxial precursor can be DCS.

[0057] Regarding the thickness and preparation process of the formed first etch stop layer 200, second etch stop layer 300, and device layer 400, no excessive restrictions are imposed here.

[0058] Next, refer to Figure 4 and Figure 5 , perform step S3 to form the insulating layer 500, and bond the device layer 400 to the support substrate 600 in combination with the insulating layer 500.

[0059] As an example, the insulating layer 500 can be formed on one or a combination of the surfaces of the device layer 400 and the support substrate 600.

[0060] In this embodiment, the insulating layer 500 is formed on the surface of the device layer 400. By oxidizing the device layer 400, a silicon oxide insulating layer is formed on the surface of the device layer 400 to serve as the insulating layer of the finally formed silicon-on-insulator structure. Among them, in order to prevent the thermal diffusion of doped atoms, the oxidation temperature is not higher than 850 °C, preferably not higher than 800 °C, such as 800 °C, 600 °C, etc. The oxidation time can be selected according to the thickness requirement of the insulating layer 500 finally required, and no excessive restrictions are imposed here. The method of forming the insulating layer 500 is not limited to this. According to needs, the insulating layer 500 can also be formed on the surface of the support substrate 600 or on the surfaces of both the device layer 400 and the support substrate 600, and no excessive restrictions are imposed here.

[0061] As an example, when bonding the device layer 400 to the support substrate 600 in combination with the insulating layer 500, it may include the steps of performing surface oxygen plasma treatment and performing reinforcement treatment.

[0062] Specifically, the surfaces of the insulating layer 500 and the support substrate 600 to be bonded can be treated with oxygen plasma respectively to increase the room-temperature bonding strength, and then low-temperature reinforcement treatment is carried out. The temperature of the reinforcement treatment is not higher than 700 °C, such as 700 °C, 500 °C, 400 °C, etc., preferably 300 °C to 500 °C, and the time is not higher than 4 hours, such as 4 hours, 3 hours, 2 hours, etc.

[0063] Next, refer to Figure 6 , perform step S4 to grind the epitaxial substrate 100, leaving a certain thickness of the epitaxial substrate 100.

[0064] As an example, the method of grinding the epitaxial substrate 100 may include one or a combination of mechanical grinding and chemical mechanical grinding. The thickness of the reserved epitaxial substrate ≤ 2 μm, such as 2 μm, 1 μm, etc. The thickness deviation of the epitaxial substrate 100 after grinding is controlled within < 0.5 μm, such as 0.5 μm, 0.4 μm, 0.2 μm, etc.

[0065] Next, refer to Figure 7 , perform step S5 to perform the first etching with the first etching solution to remove the remaining epitaxial substrate 100.

[0066] Specifically, when removing the remaining epitaxial substrate 100, the remaining epitaxial substrate 100 is subjected to the first etching using an etching solution with an etching selectivity ratio. This first etching solution has a very high etching rate for p+ silicon materials such as boron-doped p+ silicon materials, etc., while the etching rate for intrinsic silicon material is very small. Thus, the etching reaction can stop at the p+ / first etching stop layer interface, that is, at the interface between the epitaxial substrate 100 and the first etching stop layer 200, and the thickness deviation of the first etching stop layer 200 made of intrinsic silicon material is controlled within 100 nm on the second etching stop layer 300 made of germanium-silicon alloy layer, reaching a level that cannot be achieved by mechanical chemical polishing. This is beneficial for optimizing the thickness deviation of the silicon-on-insulator thin film 410 prepared as in Figure 10 to be less than 5 nm after the second etching and the third etching, thereby realizing the planarization preparation of the silicon-on-insulator thin film 410. Among them, the first etching solution can be a mixed etching solution of HF, HNO3, and Hac. Different concentration ratios of the first etching solution correspond to different etching selectivity ratios, which can be specifically adjusted according to needs.

[0067] Next, refer toFigure 8 Step S6 is executed to perform a second etching using a second etching solution to remove the first etch stop layer 200.

[0068] Specifically, the second etching can be performed using a stress-sensitive etchant to remove the first etch stop layer 200. The second etching solution can be tetramethylammonium hydroxide (TMAH) with a concentration not higher than 25%, such as 25%, 20%, 15%, etc. The etching temperature can be 50°C to 90°C, such as 50°C, 60°C, 80°C, 90°C, etc., and is preferably 55°C to 70°C. This reaction will stop at the interface position between the intrinsic silicon / germanium-silicon alloy layer, that is, it will stop at the interface position between the first etch stop layer 200 and the second etch stop layer 300.

[0069] Next, refer to Figure 9 Step S7 is executed to perform a third etching using a third etching solution to remove the second etch stop layer 200, forming a silicon-on-insulator structure.

[0070] Specifically, an etching solution with a high etching selectivity to the second etch stop layer 300 and the device layer 400 can be selected for the third etching. For example, the third etching solution can include a mixed etching solution of HF, HNO3, and Hac or a mixed etching solution of HF, H2O2, and Hac to perform the third etching, so as to remove the second etch stop layer 300 made of a germanium-silicon alloy layer. This reaction will stop at the germanium-silicon alloy layer / device layer interface, and finally the silicon-on-insulator structure is obtained. Among them, the concentration ratio of the third etching solution is different, and the corresponding etching selectivity will also be different, which can be specifically adjusted according to needs.

[0071] Next, refer to Figure 10 Step S8 is executed to perform a sacrificial oxidation treatment on the silicon-on-insulator structure, remove part of the device layer 400, and perform a heat treatment to obtain a silicon-on-insulator thin film 410.

[0072] Specifically, after the third etching, a porous layer (Si / SiO x), in order to remove the porous layer and further strengthen the bonding interface, the silicon-on-insulator structure obtained after etching can be subjected to sacrificial oxidation treatment. For example, it can be carried out in an atmosphere of dry oxygen or wet oxygen or a combination of dry and wet oxygen, with an oxidation temperature of 700°C to 1100°C, such as 700°C, 800°C, 1100°C, etc., preferably 750°C to 1000°C, to remove a silicon layer with a thickness of 50 nm to 200 nm, such as 50 nm, 100 nm, 150 nm, 200 nm, etc. The specific oxidation time can be determined according to the target thickness and oxidation temperature, and no excessive limitation is made here. After the oxidation is completed, the oxide layer on the surface is removed in an HF solution, where the HF concentration is less than 20%, such as 15%, 10%, 5%, etc., preferably 5%.

[0073] After removing the porous layer, a final treatment method is adopted to optimize the surface roughness. This final treatment can be rapid thermal annealing (RTA) or long-term thermal annealing (batch anneal) or an alternation of both. The atmosphere for the heat treatment can be a hydrogen-argon mixed atmosphere or a pure argon atmosphere. The treatment temperature range for the rapid thermal annealing is 1150 - 1300°C, and the temperature range for the long-term thermal annealing is 1050 - 1250°C. Finally, a silicon-on-insulator thin film 410 with a thickness deviation < 5 nm, such as 4 nm, 3 nm, 2 nm, etc., and a surface roughness such as etc., with good flatness is obtained.

[0074] Furthermore, when it is necessary to adjust the thickness of the finally formed silicon-on-insulator thin film 410, an oxidation thinning process or an epitaxial process can also be included on the silicon-on-insulator thin film 410 to make the thickness of the finally formed silicon-on-insulator thin film 410 meet the specification requirements, which can be specifically adjusted according to needs.

[0075] In summary, the method for preparing silicon-on-insulator of the present invention forms an intrinsic silicon first etch stop layer, a germanium-silicon alloy second etch stop layer, and a silicon device layer stacked from bottom to top on a p-type doped single-crystalline silicon epitaxial substrate. After oxidation, bonding, strengthening, and grinding treatments, selective etching is carried out. Through the selective etching of p+ / intrinsic silicon, the thickness deviation of the intrinsic silicon first etch stop layer located on the germanium-silicon alloy second etch stop layer is controlled within 100 nm. Subsequently, through the second etching and the third etching, the thickness deviation of the finally prepared silicon-on-insulator thin film can be optimized to less than 5 nm, and the surface roughness is less than Thus, the flat preparation of the silicon-on-insulator thin film is achieved.

[0076] The above embodiments are only illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for preparing silicon on insulator, characterized in that, The method includes the following steps: Provide an epitaxial substrate and a support substrate, wherein the epitaxial substrate is a p-type doped single-crystalline silicon epitaxial substrate; Form a first etch stop layer, a second etch stop layer, and a device layer stacked from bottom to top on the epitaxial substrate by epitaxy. Among them, the first etch stop layer is an intrinsic silicon layer, the second etch stop layer is a germanium-silicon alloy layer, and the device layer is a silicon device layer; Form an insulating layer, and bond the device layer to the support substrate in combination with the insulating layer; Grind the epitaxial substrate, and reserve a certain thickness of the epitaxial substrate; Perform a first etch using a first etch solution to remove the remaining epitaxial substrate; Perform a second etch using a second etch solution to remove the first etch stop layer; Perform a third etch using a third etch solution to remove the second etch stop layer, and form a silicon-on-insulator structure; Perform a sacrificial oxidation treatment on the silicon-on-insulator structure, remove a part of the device layer, and perform a heat treatment to obtain a silicon-on-insulator thin film.

2. The method for preparing silicon on insulator according to claim 1, wherein: The epitaxial substrate includes a p-type heavily doped single-crystalline silicon epitaxial substrate; the support substrate includes one of a silicon support substrate, a sapphire support substrate, a quartz support substrate, and a glass support substrate; the device layer includes a doped silicon device layer.

3. The method for preparing silicon on insulator according to claim 1, wherein: When forming the first etch stop layer by epitaxy, the epitaxial temperature ≤ 1200 °C, and the epitaxial thickness of the formed first etch stop layer ≤ 1000 nm; when forming the second etch stop layer by epitaxy, the epitaxial temperature ≤ 800 °C, the epitaxial thickness of the formed second etch stop layer is 10 nm - 60 nm, and the formed second etch stop layer is Ge x Si y layer, the value of x is 0.1 - 0.5, and the value of y is 1 - x; when forming the device layer by epitaxy, the epitaxial temperature < 800 °C, and the epitaxial thickness of the formed device layer ≤ 600 nm.

4. The method for preparing silicon on insulator according to claim 1, wherein: The insulating layer is formed on one or a combination of the surfaces of the device layer and the support substrate.

5. The method for preparing silicon on insulator according to claim 1, wherein: When bonding the device layer to the support substrate in combination with the insulating layer, it includes the steps of performing a surface oxygen plasma treatment and a strengthening treatment.

6. The method for preparing silicon-on-insulator according to claim 1, wherein: The method of grinding the epitaxial substrate includes one or a combination of mechanical grinding and chemical mechanical grinding. The reserved thickness of the epitaxial substrate is ≤2 μm, and the thickness deviation of the epitaxial substrate is <0.5 μm.

7. The method for preparing silicon on insulator according to claim 1, characterized in that: The first etch solution includes a mixed etch solution of HF, HNO3, and Hac; the second etch solution includes TMAH; the third etch solution includes a mixed etch solution of HF, HNO3, and Hac or a mixed etch solution of HF, H2O2, and Hac.

8. The method for preparing silicon on insulator according to claim 1, wherein: The step of performing the sacrificial oxidation treatment includes one or a combination of dry oxygen and wet oxygen, wherein the oxidation temperature is 700°C to 1100°C, and after the oxidation process ends, the surface oxide layer is removed using an HF solution.

9. The method for preparing silicon on insulator according to claim 1, wherein: When performing the heat treatment, it includes performing rapid thermal processing, long-time heat treatment, or alternating between the two. Among them, the temperature range of the rapid thermal processing is 1150 to 1300°C, the temperature range of the long-time heat treatment is 1050 to 1250°C, and the atmosphere of the heat treatment includes a hydrogen-argon mixed atmosphere or a pure argon atmosphere.

10. The method for preparing silicon on insulator according to claim 1, wherein: After performing the sacrificial oxidation treatment and the heat treatment on the silicon-on-insulator structure, the thickness deviation of the obtained silicon-on-insulator thin film is < 5 nm, and the surface roughness of the obtained silicon-on-insulator thin film is < 11. The method for preparing silicon on insulator according to claim 1, wherein: It also includes the step of performing oxidation thinning or epitaxial growth on the silicon-on-insulator thin film to adjust the thickness of the silicon-on-insulator thin film.

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