Light emitting diode and method of manufacturing the same

Abstract

The application discloses a light emitting diode and a preparation method thereof. The preparation method comprises the following steps: providing a substrate, forming an epitaxial structure on the surface of the substrate, wherein the epitaxial structure comprises a first semiconductor layer, an active layer and a second semiconductor layer formed on the surface of the substrate in sequence. The second semiconductor layer and the active layer are etched in sequence from the surface of the second semiconductor layer downwards to expose the upper surface of the first semiconductor layer at the edge of the epitaxial structure; the upper surface of the first semiconductor layer exposed at the edge of the epitaxial structure is defined as a sub-mesa; and the edge area of the epitaxial structure is etched to the substrate to form a cutting path area on the surface of the substrate. The mesa structure is not formed at the edge position of the epitaxial structure, the influence of the mesa structure formed at the edge position of the epitaxial structure on the light emitting area is avoided, and the light emitting efficiency of the light emitting diode is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and more specifically to a light-emitting diode and its fabrication method. Background Technology

[0002] Light-emitting diodes (LEDs) are solid-state light-emitting devices that convert electrical energy into light energy. Due to their advantages such as long lifespan, small size, good shock resistance, energy saving, high efficiency, fast response time, low driving voltage, and environmental friendliness, they are widely used in many fields such as indication, display, decoration, and lighting.

[0003] In existing technologies, the light-emitting area of ​​an LED is a crucial factor affecting its brightness during LED fabrication. Current LED manufacturing processes typically involve sequentially forming an N-type semiconductor layer, a light-emitting layer, and a P-type semiconductor layer on a substrate surface, working on a wafer basis. The light-emitting layer is then etched away from the surface of the P-type semiconductor layer downwards to expose the N-type semiconductor layer, forming a mesa structure. Next, the substrate thickness is reduced by grinding, and finally, the mesa structure is diced for subsequent separation into individual LEDs. However, before dicing, due to the large wafer area, the substrate is thinned while the wafer area remains relatively thin. The N-type layer on the wafer is continuous and relatively thick, resulting in high stress on the substrate, which can easily cause warping and breakage during dicing.

[0004] To prevent breakage during cutting, one solution proposes a method for fabricating a light-emitting diode (LED) using the following steps: The LED formation process includes:

[0005] Step 1, refer to Figure 1a A substrate 100 is provided, and an epitaxial structure 200 is formed on the surface of the substrate 100. The epitaxial structure 200 includes a first semiconductor layer 201, an active layer 202 and a second semiconductor layer 203 sequentially formed on the surface of the substrate 100.

[0006] Step 2: Etch down along the second semiconductor layer 203 of the epitaxial structure 200 to the first semiconductor layer 201 to form a sub-mesa structure, wherein the first semiconductor layer 201 is the sub-mesa structure.

[0007] Step 3, refer to Figure 1b The sub-mesa structure formed by the edge of the epitaxial structure 200 is etched downwards to the substrate 100, exposing the upper surface of the substrate and forming the dicing area 300.

[0008] Step 4, along Figure 1b The cutting zone 3000 is cut by laser beams from the lower surface of substrate 100 to perform stealth cutting, and then separated by external force to form a single light-emitting diode, such as... Figure 1c As shown, the protrusion height of the edge region 300 is the same as the protrusion height of the upper surface of the substrate 100 below the epitaxial structure 200.

[0009] Because the width of the mesa structure at the edge of the epitaxial structure 200 used to form the dicing region is greater than the width of the formed dicing region 300, after etching the dicing region 300, a portion of the mesa structure remains at the edge of the epitaxial structure 200. This residual mesa structure has no active layer above it, but it occupies a certain amount of light-emitting area, resulting in a loss of the light-emitting area of ​​the epitaxial structure and affecting the luminous efficiency. To increase the light-emitting area of ​​the light-emitting diode, another solution is proposed, which includes the following method:

[0010] Reference Figure 2a Step 1: Provide a substrate 100, and form an epitaxial structure 200 on the surface of the substrate 100. The epitaxial structure 200 includes a first semiconductor layer 201, an active layer 202, and a second semiconductor layer 203 sequentially formed on the surface of the substrate 100. The first semiconductor layer 201 is an N-type semiconductor layer, and the second semiconductor layer 203 is a P-type semiconductor layer.

[0011] Step 2: The second semiconductor layer 203 and the active layer 202 are sequentially etched downwards from the surface of the second semiconductor layer 203 to expose the first semiconductor layer 201. The exposed first semiconductor layer 201 is formed as a sub-mesa structure (not shown in the figure), which is a sub-mesa structure formed inside the epitaxial structure 200. At this time, the sub-mesa structure formed inside the epitaxial structure 200 is used to form the N-electrode, while no mesa structure is formed at the edge of the epitaxial structure 200. This avoids the impact of forming mesa structures at the edge of the epitaxial structure 200 on the light-emitting area, thus improving the luminous efficiency of the light-emitting diode.

[0012] Step 3, refer to Figure 2b The second semiconductor layer 203, the active layer 202 and the first semiconductor layer 201 are sequentially etched downwards at the edge of the epitaxial structure 200 to form the dicing region 300.

[0013] Step 4: Along Figure 2b The cutting area 300 is cut by laser light from the lower surface of the substrate 100 to perform stealth cutting, and then separated by external force to form a single light-emitting diode, such as... Figure 2c As shown, the protrusion height of the edge region 3000 is the same as the protrusion height of the upper surface of the substrate 100 below the epitaxial structure 200.

[0014] However, during the etching process of the dicing area 300, incomplete etching of the first semiconductor layer 201 may occur, leading to leakage after the light-emitting diode (LED) is formed. This is especially true when the substrate 100 is a patterned substrate. On the one hand, semiconductor material can easily remain between the patterned structures, causing leakage. On the other hand, when an insulating layer is formed on the surface of the LED and the surface of the substrate 100 above the dicing area 300, the insulating layer may not adhere well to the patterned substrate 100, also easily causing leakage. Summary of the Invention

[0015] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a light-emitting diode and its manufacturing method, so as to increase the light-emitting area of ​​the light-emitting diode and thus improve the luminous efficiency while ensuring the yield of the light-emitting diode manufacturing process.

[0016] To achieve the above and other related objectives, the present invention provides a method for fabricating a light-emitting diode, comprising:

[0017] A substrate is provided, the upper surface of which is a patterned upper surface, and an epitaxial structure is formed on the upper surface of the substrate. The epitaxial structure includes a first semiconductor layer, an active layer, and a second semiconductor layer sequentially formed on the surface of the substrate.

[0018] The second semiconductor layer and the active layer are etched sequentially downwards from the surface of the second semiconductor layer to expose a portion of the upper surface of the first semiconductor layer at the edge of the epitaxial structure; the portion of the upper surface of the first semiconductor layer exposed at the edge of the epitaxial structure is defined as a sub-mesa.

[0019] Etching the edge region of the epitaxial structure to the substrate to form a cleavage region on the surface of the substrate, the etched edge region includes a first edge region and a second edge region, the first edge region corresponding to a sub-mesa formed on the edge region of the epitaxial structure, and the second edge region corresponding to a portion of the epitaxial structure near the sub-mesa. Optionally, etching the edge region of the epitaxial structure to the substrate further includes:

[0020] Simultaneously, sub-mesa corresponding to the first edge region and epitaxial structure corresponding to the second edge region are etched onto the substrate. The substrate corresponding to the first edge region is formed as the first dicing region, and the substrate corresponding to the second edge region is formed as the second dicing region. The thickness of the substrate corresponding to the second dicing region is greater than the thickness of the substrate corresponding to the first dicing region.

[0021] Optionally, the substrate is a patterned substrate, which includes a planar structure and protrusions formed on the surface of the planar structure and spaced apart.

[0022] Optionally, etching the edge region of the epitaxial structure to the substrate further includes:

[0023] Simultaneously, sub-mesa corresponding to the first edge region and epitaxial structure corresponding to the second edge region are etched onto the substrate; wherein, a flat region is formed on the surface of the substrate corresponding to the first edge region, and the flat region is formed as the first dicing region; a second protrusion structure is formed on the surface of the substrate corresponding to the second edge region, and the substrate region corresponding to the second protrusion structure is formed as the second dicing region.

[0024] Optionally, etching the edge region of the epitaxial structure to the substrate further includes:

[0025] Simultaneously, sub-mesa corresponding to the first edge region and epitaxial structure corresponding to the second edge region are etched onto the substrate; wherein, a first protrusion structure is formed on the surface of the substrate corresponding to the first edge region, and the substrate region corresponding to the first protrusion structure is formed as a first dicing region; a second protrusion structure is formed on the surface of the substrate corresponding to the second edge region, and the substrate region corresponding to the second protrusion structure is formed as a second dicing region, and the height of the first protrusion structure is lower than the height of the second protrusion structure.

[0026] The present invention also provides a light-emitting diode, comprising:

[0027] Substrate,

[0028] An epitaxial structure is formed on the upper surface of a substrate, and the epitaxial structure includes a first semiconductor layer, an active layer, and a second semiconductor layer sequentially formed on the surface of the substrate.

[0029] An edge region surrounds the epitaxial structure and exposes the substrate; the edge region includes a first edge region and a second edge region, the second edge region being closer to the epitaxial structure than the first edge region;

[0030] The upper surface of the substrate corresponding to the first edge region is a first protrusion structure, and the upper surface of the substrate corresponding to the second edge region has a second protrusion structure, the height of the second protrusion structure being higher than the height of the first protrusion structure; or the upper surface of the substrate corresponding to the first edge region is a flat region, and the upper surface of the substrate corresponding to the second edge region has a second protrusion structure, the substrate surface of the flat region being flat.

[0031] Optionally, the height of the first protrusion structure on the substrate is 1~2μm or less than 1μm.

[0032] Optionally, the height of the second protrusion structure on the substrate is 1~2μm or less than 1μm.

[0033] Optionally, at least a portion of the sidewalls of the epitaxial structure extend continuously from the second semiconductor layer to the edge region along the circumferential direction, and at least a portion of the sidewalls have no steps.

[0034] Optionally, all sidewalls of the epitaxial structure extend continuously from the second semiconductor layer to the edge region along the circumferential direction, and there are no steps on any of the sidewalls.

[0035] Optionally, a portion of the sidewalls of the epitaxial structure extends continuously from the second semiconductor layer to the edge region along the circumferential direction. Some of the sidewalls have no steps, while the remaining sidewalls, except for the portion of the sidewalls, have steps for setting electrodes.

[0036] Optionally, it also includes an insulating layer covering the edge region, wherein the first and second protrusion structures of the substrate are conical, and the sidewalls of the first or second protrusion structure are arc-shaped.

[0037] Optionally, the width of the edge region of the substrate is 4~12μm.

[0038] Optionally, the thickness of the substrate corresponding to the first edge region is less than the thickness of the substrate corresponding to the second edge region.

[0039] The present invention also provides a light-emitting diode, comprising:

[0040] Substrate,

[0041] An epitaxial structure is formed on the upper surface of a substrate, and the epitaxial structure includes a first semiconductor layer, an active layer, and a second semiconductor layer sequentially formed on the surface of the substrate.

[0042] An edge region surrounds the edge of the epitaxial structure and exposes the substrate; the edge region includes a first edge region and a second edge region, the second edge region being closer to the epitaxial structure than the first edge region;

[0043] The thickness of the substrate corresponding to the first edge region is less than the thickness of the substrate corresponding to the second edge region.

[0044] Optionally, the upper surface of the substrate corresponding to the first edge region has a first protrusion structure, and the upper surface of the substrate corresponding to the second edge region has a second protrusion structure, wherein the height of the second protrusion structure is higher than that of the first protrusion structure.

[0045] Optionally, the upper surface of the substrate corresponding to the first edge region is a flat region, and the upper surface of the substrate corresponding to the second edge region has a second protrusion structure, and the substrate surface of the flat region is flat.

[0046] Optionally, it also includes an insulating layer that covers the edge area.

[0047] Optionally, the width of the first edge region is greater than the width of the second edge region.

[0048] Compared with the prior art, the light-emitting diode and its fabrication method described in this invention have at least the following beneficial effects:

[0049] In this invention, the upper surface of the first semiconductor layer exposed at the edge of the epitaxial structure is defined as a sub-mesa. Etching is performed from the edge region of the upper surface of the second semiconductor layer and the sub-mesa to the surface of the substrate to form a dicing region on the substrate surface. Because this invention does not form a mesa structure at the edge of the epitaxial structure, it avoids the impact of forming a mesa structure at the edge of the epitaxial structure on the light-emitting area, thus improving the luminous efficiency of the light-emitting diode. Furthermore, forming the dicing region based on the sub-mesa also saves etching time for forming the dicing region.

[0050] Furthermore, when the width of the dicing zone is greater than the width of the sub-mesa, a first dicing zone and a second dicing zone are formed within the dicing zone. Since the surface of the substrate corresponding to the first dicing zone is flatter than the surface of the substrate corresponding to the second dicing zone, the insulating layer formed in the second dicing zone adheres more tightly to the substrate, thereby improving the production yield of the light-emitting diode. Moreover, due to the height difference between the first and second dicing zones, the first semiconductor layer is removed more thoroughly in the first dicing zone, thus preventing leakage current caused by incomplete etching of the first semiconductor layer material in the first dicing zone and improving the luminous efficiency of the light-emitting diode.

[0051] The light-emitting diode of the present invention is formed by the above-described method for preparing a light-emitting diode and also possesses the aforementioned technical effects. Attached Figure Description

[0052] Figure 1a This is a schematic diagram of the mesa structure formed by etching during the formation of a light-emitting diode in the prior art.

[0053] Figure 1b In the existing technology Figure 1a A schematic diagram of the structure in which the cutting channel area is formed by etching on the basis of the material;

[0054] Figure 1c In the existing technology Figure 1b A schematic diagram of the structure of a light-emitting diode formed after cutting;

[0055] Figure 2a This is a schematic diagram of an existing technology for forming an epitaxial structure on the surface of a substrate.

[0056] Figure 2b A schematic diagram of a cutting channel region formed at the edge position of an etched epitaxial structure in the prior art;

[0057] Figure 2c For the existing technology Figure 2b A schematic diagram of the light-emitting diode structure after it has been cut from the original structure;

[0058] Figure 3aThis is a schematic diagram of the structure after forming an epitaxial structure on the surface of the substrate in the first embodiment of the present invention;

[0059] Figure 3b This is a schematic diagram of the structure formed by etching the epitaxial structure to create a mesa structure in the first embodiment of the present invention;

[0060] Figure 3c This is a schematic diagram of the etched epitaxial structure and mesa structure forming the cutting channel area in the first embodiment of the present invention;

[0061] Figure 3d This is a schematic diagram of the etched epitaxial structure and mesa structure forming the cutting channel area in the first embodiment of the present invention;

[0062] Figure 4a This is a cross-sectional view of the light-emitting diode described in a specific embodiment of the second embodiment of the present invention;

[0063] Figure 4b This is a cross-sectional schematic diagram of the light-emitting diode described in another specific embodiment of the second embodiment of the present invention;

[0064] Figure 5a This is a cross-sectional schematic diagram of the light-emitting diode described in a further specific embodiment of the second embodiment of the present invention;

[0065] Figure 5b for Figure 5a A top view of the structure of the light-emitting diode described herein.

[0066] List of reference numerals in the attached diagram:

[0067] 100 substrate 101 planar structure 102 Initial protrusion structure 103 First protrusion structure 104 Second protrusion structure 105 flat area 200、12 Epitaxial structure 201、123 First semiconductor layer 202、124 Active layer 203、125 Second semiconductor layer 300 Cutting lane area 301 First Cutting Road Area 302 Second Cutting Road Area

[0068] 3000 Edge area 3010 First Edge Zone 3020 Second edge zone Detailed Implementation

[0069] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0070] It should be understood that the illustrations provided in the embodiments of this invention are merely schematic representations of the basic concept of the invention. Although the illustrations only show components relevant to the invention and are not drawn according to the actual number, shape, and size of components in implementation, the shape, quantity, and proportion of each component can be arbitrarily changed in actual implementation, and the component layout may also be more complex. The structures, proportions, sizes, etc., shown in the accompanying drawings are only used to complement the content disclosed in the specification for those skilled in the art to understand and read, and are not intended to limit the conditions under which this application can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationships, or adjustments to the size, without affecting the effects and objectives that the invention can produce, should still fall within the scope of the technical content disclosed in this application.

[0071] It should be noted that, in this invention, the thickness of the substrate corresponding to any region with a raised structure on the substrate surface is the thickness between the top of the raised structure in the corresponding region on the upper surface of the substrate; the thickness of the substrate corresponding to a flat region on the substrate surface is the thickness between the lower surface of the substrate and the flat region on the upper surface of the substrate.

[0072] To address the problems existing in the background art, this embodiment provides a method for fabricating a light-emitting diode (LED) and an LED, thereby improving the luminous efficiency and chip fabrication yield of the LED, and saving fabrication time and cost.

[0073] Example 1

[0074] This embodiment provides a method for fabricating a light-emitting diode, including:

[0075] S101: A substrate is provided, and an epitaxial structure is formed on the surface of the substrate. The epitaxial structure includes a first semiconductor layer, an active layer, and a second semiconductor layer sequentially formed on the surface of the substrate.

[0076] Reference Figure 3a A substrate 100 is provided, which may be made of sapphire. The substrate 100 may be a patterned substrate. The substrate 100 has an upper surface and a lower surface, and the upper surface of the substrate 100 has a pattern made of aluminum oxide. The pattern height of the substrate is 1.5~3μm, and the pattern width of the substrate is 2~4μm.

[0077] An epitaxial structure 200 is formed by sequentially depositing a first semiconductor layer 201, an active layer 202, and a second semiconductor layer 203 on the surface of a substrate 100. Optionally, the first semiconductor layer 201 is an n-type semiconductor layer, the active layer 202 is a quantum well layer, and the second semiconductor layer 203 is a p-type semiconductor layer. Optionally, the n-type semiconductor layer, the quantum well layer, and the p-type semiconductor layer are all GaN-based materials. Furthermore, the epitaxial structure 200 can be deposited using chemical vapor deposition.

[0078] Optionally, after forming the epitaxial structure 200 on the surface of the substrate 100, a conductive layer (not shown in the figure) may be formed on the surface of the p-type semiconductor layer, and the conductive layer may be etched to expose the edge region to be etched. For example, the conductive layer may be indium tin oxide, nickel gold, etc.

[0079] S102: The second semiconductor layer and the active layer are etched sequentially from the surface of the second semiconductor layer downwards to expose the first semiconductor layer; the exposed first semiconductor layer is formed as a sub-mesa structure, the mesa structure including a sub-mesa formed in the edge region of the epitaxial structure; the sub-mesa formed in the edge region of the epitaxial structure is an annular mesa surrounding the active layer and flush with or lower than the lower surface of the active layer.

[0080] Reference Figure 3b After etching the conductive layer, the second semiconductor layer 203 and the active layer 202 are sequentially etched in the exposed edge region to be etched, so as to expose the first semiconductor layer 201. The exposed first semiconductor layer 201 is formed as a mesa structure. The mesa structure includes sub-mesa formed in the edge region of the epitaxial structure 200 and / or sub-mesa formed inside the epitaxial structure 200. At this time, the local area of ​​the sub-mesa formed at the edge of the epitaxial structure 200 can also be used to form N electrodes. For example, one or more N electrodes are formed on a part of the sub-mesa structure at the edge. Alternatively, an N electrode epitaxial structure can be formed on the sub-mesa inside the epitaxial structure 200. The sub-mesa formed at the edge of the epitaxial structure 200 does not need to form N electrodes.

[0081] In this embodiment, the sub-mesa formed inside the epitaxial structure 200 is used to form the N electrode. The sub-mesa structure formed inside the epitaxial structure 200 can be one or more, and can be circular, elliptical or elongated. The sub-mesa formed at the edge of the epitaxial structure 200 does not need to form the N electrode.

[0082] S103: Etch the edge region of the epitaxial structure to form a cleavage region on the surface of the substrate, wherein the width of the cleavage region is greater than the width of the sub-mesa.

[0083] The edge region of the epitaxial structure 200 is etched to form a dicing region 300 on the surface of the substrate 100. In this embodiment, inductively coupled plasma (ICP) etching is used. More preferably, the ICP etching gas is capable of etching the epitaxial structure. As an example, the ICP etching gas is at least two combinations of gases such as CF4, oxygen, chlorine, or boron chloride. By adjusting the gas ratio, the epitaxial structure and the sapphire substrate can be etched simultaneously.

[0084] In one embodiment, reference is made to Figure 3c Alternatively, in 3d, the width of the sub-mesa is less than the width of the dicing region 300. In this case, the dicing region 300 of the epitaxial structure 200 includes a first dicing region 301 and a second dicing region 302. The first dicing region 301 corresponds to the region of the epitaxial structure 200 below the sub-mesa. The second dicing region 302 corresponds to the epitaxial structure region near the edge of the upper surface of the second semiconductor layer of the sub-mesa, and this epitaxial structure region includes a second semiconductor layer, an active layer, and a first semiconductor layer. At this time, the edge region of the etched epitaxial structure 200 also includes: in the same etching process, simultaneously etching the sub-mesa corresponding to the first dicing region 301 and the epitaxial structure 200 corresponding to the second dicing region 302 to the substrate 100, so that the thickness d1 of the substrate 100 corresponding to the first dicing region 301 (since there is a protrusion on the upper surface of the substrate in this region, the thickness corresponds to the vertical distance between the top of the pattern on the upper surface of the substrate and the lower surface of the substrate) is less than the thickness d2 of the substrate 100 corresponding to the second dicing region 302 (since there is a protrusion on the upper surface of the substrate in this region, the thickness corresponds to the vertical distance between the top of the pattern on the upper surface of the substrate and the lower surface of the substrate); since the thickness of the epitaxial structure corresponding to the sub-mesa is lower than the thickness of the epitaxial structure 200 in the second dicing region 302, after the epitaxial structure 200 below the sub-mesa is etched, the gas of ICP etching further etches the substrate until the epitaxial structure 200 in the second dicing region 302 is etched clean and stops on the upper surface of the substrate.

[0085] In an optional embodiment, refer to Figure 3a Alternatively, in option 3b, the substrate 100 may be a patterned substrate, comprising a planar structure 101 and initial protrusions 102 formed at intervals on the planar structure 101, wherein the epitaxial structure 200 is formed on the surface of the patterned substrate having the initial protrusions 102. (Refer to...) Figure 3cCorresponding to the etching of the sub-mesa to the substrate 100 in the first edge region, a first protrusion structure 103 is formed on the upper surface of the substrate 100. The first protrusion structure 103 is formed based on the etching of the initial protrusion structure 102, and the region corresponding to the first protrusion structure 103 is formed as the first dicing region 301. Corresponding to the etching of the epitaxial structure 200 to the substrate 100 in the second edge region, a second protrusion structure 104 is formed on the surface of the substrate 100. The second protrusion structure 104 is formed based on the etching of the initial protrusion structure 102, and the region corresponding to the second protrusion structure 104 is formed as the second dicing region 302. Since the etching starting point of the first dicing region 301 is the sub-mesa, and the etching starting point of the second dicing region 302 is the second semiconductor layer 203 of the epitaxial structure 200, both are etched in the same etching process. Therefore, the height of the first protrusion structure 103 formed in the first dicing region 301 is less than the height of the second protrusion structure 104. Optionally, the height of the second protrusion structure 104 may be further lower than the height of the initial protrusion structure 102 below the epitaxial layer.

[0086] Optionally, referring to 3d, the edge region of the etched epitaxial structure 200 further includes: in the same etching process, etching the sub-mesa to the substrate 100 corresponding to the first edge region, and forming a flat region 105 on the surface of the substrate 100. This flat region 105 can be the surface of the planar structure 101 of the patterned substrate, or it can be the surface of the substrate 100 after etching downwards from the surface of the planar structure 101 to a certain thickness. The substrate 100 region corresponding to the flat region 105 is formed as the first dicing region 301. Corresponding to the second edge region, the epitaxial structure 200 is etched to the substrate 100 to form a second protrusion structure 104 on the surface of the substrate 100. This second protrusion structure 104 can have the same height as the initial protrusion structure 102 below the epitaxial structure. The second protrusion structure 104 can also be a structure formed by further etching based on the initial protrusion structure 102, with the height of the second protrusion structure 104 being lower than the height of the initial protrusion structure 102 below the epitaxial structure. The corresponding substrate 100 region is formed as the second dicing region 302.

[0087] Optionally, the width of the sub-platform is between 2μm and 38μm.

[0088] Optionally, the width of the cutting channel is between 4μm and 40μm.

[0089] Optionally, the width of the first cutting channel region 301 is between 2μm and 38μm, and the width of the second cutting channel region 302 is between 2μm and 38μm.

[0090] The width of the first cutting channel area 301 may be less than the width of the second cutting channel area 302, or the width of the first cutting channel area 301 may be equal to or greater than the width of the second cutting channel area 302.

[0091] Optionally, the height of the first protrusion structure is less than 2 μm; further, the height can be 1~2 μm or less than 1 μm.

[0092] Optionally, the height of the second protrusion is less than 2 μm, and further, the height can be 1~2 μm or less than 1 μm.

[0093] The surface of the substrate 100 corresponding to the first dicing region 301 is flatter than the surface of the substrate 100 corresponding to the second dicing region 302, and the surface of the substrate 100 corresponding to the second dicing region 302 is also flatter than the surface of the substrate below the epitaxial structure 200. Subsequently, when forming the insulating layer in the second dicing region 302, the insulating layer adheres more tightly to the edge of the substrate 100, thereby improving the production yield of the light-emitting diode. Furthermore, due to the difference in etching thickness between the first dicing region 301 and the second dicing region 302, the first semiconductor layer 201 material in the first dicing region 301 can be fully etched, preventing leakage current caused by incomplete etching of the first semiconductor layer 201 material in the dicing region, and improving the luminous efficiency of the light-emitting diode.

[0094] S104: Laser ablation is performed on the substrate inside the cutting area corresponding to the second surface of the substrate using laser hidden cutting, forming modified particles inside the substrate. External force is applied along the cutting path to separate the substrate and obtain a single light-emitting diode.

[0095] Example 2

[0096] This embodiment provides a light-emitting diode, which is formed by the method of light-emitting diode in Embodiment 1.

[0097] like Figure 4a , 4b As shown in Figure 5a, the system includes a substrate 100 and an epitaxial structure 12 on the substrate 100. An edge region 3000 is disposed around the edge of the epitaxial structure 12 and exposes the upper surface of the substrate 100; the edge region 3000 includes a first edge region 3010 and a second edge region 3020, wherein the second edge region is closer to the epitaxial structure than the first edge region.

[0098] like Figure 4aAs shown, the upper surface of the substrate 100 corresponding to the first edge region 3010 has a first protrusion structure 103, and the upper surface of the substrate 100 corresponding to the second edge region 3020 has a second protrusion structure 104. The height of the second protrusion structure 104 is greater than the height of the first protrusion structure 103. That is, the thickness d1 of the substrate corresponding to the first edge region 3010 is less than the thickness d2 of the substrate corresponding to the second edge region 3020.

[0099] Optionally, the height of the first protrusion structure 103 is less than 2 μm; further, the height can be 1~2 μm or less than 1 μm.

[0100] Optionally, the height of the second protrusion structure 104 is less than 2 μm, and further, the height can be 1~2 μm or less than 1 μm.

[0101] Or such as Figure 4b As shown, the upper surface of the substrate 100 corresponding to the first edge region 3010 is a flat region 105, and the surface of the substrate corresponding to the second edge region 3020 has a second protrusion structure 104. The substrate surface of the flat region 105 is flat, that is, the surface of the flat region 105 has no protrusion structure.

[0102] Relative to the lower surface of the substrate 100, the corresponding thickness d2 between the top of the pattern of the first protrusion structure 103 and the lower surface of the substrate is greater than the thickness d1 between the upper surface of the flat region 105 of the substrate and the lower surface of the substrate.

[0103] Optionally, the height of the first protrusion structure 103 is less than 2 μm; further, the height can be 1~2 μm or less than 1 μm.

[0104] Optionally, the height of the second protrusion structure 104 is less than 2 μm, and further, the height can be 1~2 μm or less than 1 μm.

[0105] Optionally, the first protrusion structure 103 or the second protrusion structure 104 is conical, and the sidewall of the conical structure is arc-shaped, which can be an inwardly concave arc-shaped structure or an outwardly concave arc-shaped structure.

[0106] The epitaxial structure 12 connects the second semiconductor layer 125 and the surface of the substrate 100. At least a portion of the sidewalls extend continuously from the second semiconductor layer 125 to the edge region 3000 of the surface of the substrate 100, and there are no steps on the at least a portion of the sidewalls.

[0107] Alternatively, the epitaxial structure 12 may have all its sidewalls connecting the second semiconductor layer 125 and the surface of the substrate 100 extending continuously from the second semiconductor layer 125 to the edge region 3000, and all of the sidewalls may have no steps.

[0108] Alternatively, the epitaxial structure 12 may have a portion of its sidewalls connecting the second semiconductor layer 125 and the surface of the substrate 100 extending continuously from the second semiconductor layer 125 to the edge region 3000 of the surface of the substrate 100. This portion of the sidewalls may not have steps, while the remaining sidewalls may have steps for setting electrodes.

[0109] Optionally, the width of the edge region 3000 is between 2μm and 20μm, for example 6 to 15μm, or for example 8 to 12μm.

[0110] Optionally, the width of the first edge region 3010 is between 1μm and 19μm, for example, 3~10μm, 4~8μm, or 6μm, and the width of the second edge region 3020 is between 1μm and 19μm, for example, 3~10μm, 4~8μm, or 6μm.

[0111] The width of the first edge region 3010 may be less than the width of the second edge region 3020, or the width of the first edge region 3010 may be equal to or greater than the width of the second edge region 3020.

[0112] Optionally, the first edge region 3010 can have a large area, for example, the width of the first edge region 3010 is greater than the width of the second edge region 3020, so that the height of the edge region 3000 is relatively lower, which is beneficial to the coverage of the insulating layer. Figure 4a , 4b 5a and Figure 5b The epitaxial structure 12 marked in the figure refers to the same structure as the epitaxial structure 200 in Example 1. The epitaxial structure 12 includes a first semiconductor layer 123, an active layer 124, and a second semiconductor layer 125.

[0113] Specifically, Figure 5a and Figure 5b The diagram shows a flip-chip light-emitting diode (LED) comprising an epitaxial structure 12 having opposing lower and upper surfaces 121. The epitaxial structure 12, from the lower surface 122 to the upper surface 121, includes a first semiconductor layer 123, an active layer 124, and a second semiconductor layer 125. That is, the active layer 124 is located between the first semiconductor layer 123 and the second semiconductor layer 125.

[0114] like Figure 5a As shown in Figure 5b, a portion of the upper surface of the first semiconductor layer 123 is not covered by the active layer 124; the uncovered portion is formed as a sub-mesa, and a plurality of vias are formed within the epitaxial structure 12 on the sub-mesa. The region surrounding the edge of the epitaxial structure 12 is formed as an edge region. The edge region can be referenced... Figure 4aThe edge region 3000 exposes the upper surface of the substrate 100. The edge region 3000 includes a first edge region 3010 and a second edge region 3020, where the thickness of the substrate 100 corresponding to the first edge region 3010 is less than the thickness of the substrate 100 corresponding to the second edge region 3020. Furthermore, when an insulating layer is subsequently formed on the surface of the light-emitting diode, the insulating layer covers the first edge region 3010 and the second edge region 3020, which can prevent leakage current caused by incomplete etching of the first semiconductor layer 201 material corresponding to the second edge region 3020, thereby improving the fabrication yield of the light-emitting diode.

[0115] All sidewalls of the epitaxial structure 12 extend continuously from the second semiconductor layer 125 to the edge region 3000, and none of the sidewalls have steps. The first edge region 3010 surrounds the second edge region 3020.

[0116] In this embodiment, by not forming mesa structures at the edges of the epitaxial structure, the impact of such mesa structures on the light-emitting area is avoided, thus improving the luminous efficiency of the LED. Furthermore, the increased light-emitting area, combined with the addition of a metal reflective layer, significantly enhances the luminous brightness.

[0117] The first semiconductor layer 123 can be an N-type semiconductor layer, which can provide electrons to the active layer 124 under the action of a power source. In some embodiments, the first semiconductor layer 123 includes an N-type doped nitride layer.

[0118] The first metal electrode 21 is located above the upper surface 121 of the epitaxial structure 12, that is, above the upper surface of the first semiconductor layer 123, and is electrically connected to the first semiconductor layer 123. The first metal electrode 21 can be a single-layer, double-layer, or multi-layer structure, such as a stacked structure of metal layers such as Cr, Al, Ti, Pt, Au, and Ni. In some embodiments, the first metal electrode 21 can be directly formed on the mesa of the epitaxial structure 12, and the first semiconductor layer 123 forms a good ohmic contact with each other.

[0119] The second metal electrode 22 is located above the upper surface 121 of the epitaxial structure 12, that is, above the upper surface of the second semiconductor layer 125, and is electrically connected to the second semiconductor layer 125. The second metal electrode 22 may be made of the same material as the first metal electrode 22. The top view of the light-emitting diode 1 can be as follows: Figure 5b As shown, the first metal electrode 21 is circular or elliptical and there are multiple of them, and the second metal electrode 22 is circular or elliptical and there are multiple of them. The width of each first metal electrode 21 and second metal electrode 22 can be between 5 and 50 μm, for example, 10 μm, 20 μm, 30 μm, etc.

[0120] An insulating stack 32 covers a portion of the epitaxial structure 12, a portion of the first metal electrode 21, and a portion of the second metal electrode 22. The insulating stack 32 includes a first insulating layer 321 and a second insulating layer 322. The second insulating layer 322 is located above the first insulating layer 321. In other words, the second insulating layer 322 is located above the first insulating layer 321. The insulating stack 32 has a first opening 61 and a second opening 62. The first opening 61 is located above the first metal electrode 21, so that the first connecting electrode 41 can be electrically connected to the first metal electrode 21 through the first opening 61. The second opening 62 is located above the second metal electrode 22, so that the second connecting electrode 42 can be electrically connected to the second metal electrode 22 through the second opening 62. Both the first opening 61 and the second opening 62 penetrate the first insulating layer 321 and the second insulating layer 322. The insulating stack 32 has different functions depending on its location. For example, when the insulating stack 32 covers the sidewall of the epitaxial structure 12, it can be used to prevent electrical connection between the first semiconductor layer 123 and the second semiconductor layer 125 due to leakage of conductive material, thereby reducing short-circuit abnormalities of the light-emitting diode 1. However, the embodiments disclosed herein are not limited thereto. The material of the insulating stack 32 includes a non-conductive material. The non-conductive material is preferably a dielectric material, which includes electrically insulating materials such as aluminum oxide, silicon nitride, silicon oxide, titanium oxide, or magnesium fluoride. For example, the insulating stack 32 can be silicon dioxide, silicon nitride, titanium oxide, tantalum oxide, niobium oxide, barium titanate, or a combination thereof. Such a combination can be, for example, a Bragg mirror (DBR) formed by repeatedly stacking two materials with different refractive indices.

[0121] In some embodiments, the first insulating layer 321 is an insulating reflective layer formed by repeatedly stacking two insulating materials. As one embodiment, the optical thickness of each sublayer of the DBR layer (first insulating layer 321) is approximately 137.5 nm. The thickness of the DBR layer is 2–6 μm, and the number of pairs is 10–30. More preferably, to ensure the reflectivity of the DBR layer, the number of pairs in the DBR layer is 20–30, and the thickness is 4–6 μm; for example, the DBR layer has 22 pairs and a thickness of 5 μm.

[0122] A partial or complete insulating layer covers the entire edge region 3000 of the upper surface of the substrate 100.

[0123] A metal reflective layer 26 is sandwiched between the first insulating layer 321 and the second insulating layer 322 of the insulating stack 32. The metal reflective layer 26 is used to reflect light so that more light is emitted from the light-emitting surface. In some embodiments, the metal reflective layer 26 includes Ag or Al. For example, the metal reflective layer 26 can be an Ag metal reflective layer, or an Al metal reflective layer, etc. In some embodiments, the metal reflective layer 26 and the first insulating layer 321 constitute a reflective structure layer. This reflective structure layer can be a total reflection layer. For example, the metal reflective layer 26 is an Ag or Al metal reflective layer, and the first insulating layer 321 is an insulating reflective layer (DBR layer) formed by repeated stacking of silicon dioxide and titanium dioxide. Since the DBR layer does not have high reflectivity in all wavelength ranges within the white light range, especially in the long wavelength range where the reflectivity is relatively low, the Ag or Al metal reflective layer 26 has high reflectivity in the long wavelength range. Therefore, the metal reflective layer and the insulating reflective layer together form a total reflection layer, which can reflect almost all the light back, improving the light emission performance of the light-emitting diode 1.

[0124] The first connecting electrode 41 is located above the insulating stack 32 and is connected to the first metal electrode 21. The first connecting electrode 41 serves to spread current, protect the underlying first metal electrode 21, and provide support and elevation. The material of the first connecting electrode 41 can be selected from one or more of Cr, Pt, Au, Ni, Ti, and Al. Preferably, the bottom metal of the first connecting electrode 41 is a Ti metal layer or a Cr metal layer, so that a stable adhesion relationship is formed between the first connecting electrode 41 and the insulating stack. Preferably, the surface metal of the first connecting electrode 41 is a Ti metal layer or a Cr metal layer, so that a stable adhesion relationship is formed between the first connecting electrode 41 and adjacent structural layers. The second connecting electrode 42 is located above the insulating stack 32 and is connected to the second metal electrode 22. The second connecting electrode 42 serves to spread current. The material of the second connecting electrode 42 can be selected from one or more of Cr, Pt, Au, Ni, Ti, and Al. Preferably, the surface metal of the second connecting electrode 42 is a Ti metal layer or a Cr metal layer, so that a stable adhesion relationship is formed between the second connecting electrode 42 and the adjacent structural layer.

[0125] In some embodiments, the insulating stack 32 has a first opening 61 and a second opening 62, both having a bottom width dimension and a top width dimension, with the bottom width dimension being smaller than the top width dimension. This facilitates the subsequent filling and continuous compaction of the first connecting electrode 41 and the second connecting electrode 42 within the first opening 61 and the second opening 62. Preferably, the top width dimension of the first opening 61 exceeds the width of the upper surface of the first metal electrode 21, and the top width dimension of the second opening 62 exceeds the width of the upper surface of the second metal electrode 22.

[0126] The first connecting electrode 41 can be one or more strips, or the first connecting electrode 41 can be comb-shaped, and the second connecting electrode 42 can be block-shaped. Figure 5b The first connecting electrode 41 and the second connecting electrode 42 are schematically shown with different filling patterns. Figure 5b The metallic reflective layer 26 is also illustrated with a dotted pattern. For example... Figure 5b As shown, the area of ​​the vertical projection of the first connecting electrode 41 is smaller than the area of ​​the vertical projection of the second connecting electrode 42. The second connecting electrode 42 is arranged around the first connecting electrode 41.

[0127] The vertical projections of the first metal electrode 21 and / or the second metal electrode 22 onto the horizontal plane do not overlap with the vertical projection of the metal reflective layer 26 onto the horizontal plane. That is, when viewed from above the LED 1 towards the epitaxial structure 12, the first metal electrode 21 and / or the second metal electrode 22 will not intersect or overlap with the metal reflective layer 26, and there will be no vertical projections of the first metal electrode 21 and the second metal electrode 22 within the vertical projection area of ​​the metal reflective layer 26. This is achieved by ensuring that the vertical projections of the first metal electrode 21 and / or the second metal electrode 22 onto the horizontal plane do not overlap with the vertical projection of the metal reflective layer 26 onto the horizontal plane. If the vertical projection of the first metal electrode 21 and / or the second metal electrode 22 onto the horizontal plane overlaps with the vertical projection of the metal reflective layer 26 onto the horizontal plane, it means that the first opening 61 and / or the second opening 62 at the insulating stack 32 will be very small. In other words, the metal reflective layer 26 covers the first metal electrode 21 and the second metal electrode 22. Since the insulating stack 32 below the metal reflective layer 26 covers the first metal electrode 21 and the second metal electrode 22, a step is formed. The brittleness of the insulating stack 32 makes it easy for cracks to appear at the step. Moisture is easy to erode along the cracks, which makes the metal reflective layer 26 easy to migrate, affecting the reflective stability of the metal reflective layer 26 and the possibility of metal contact between the metal reflective layer 26 and the contact electrode below, resulting in some mixing, which affects its stability and is easy to damage the metal reflective layer 26 in subsequent etching and other processes.

[0128] Preferably, the vertical projection of the lower surface of the first metal electrode 21 and / or the lower surface of the second metal electrode 22 onto the horizontal plane does not overlap with the vertical projection of the lower surface of the metal reflective layer 26 onto the horizontal plane. In some embodiments, the horizontal plane can be understood as... Figure 5a The surface where the lower surface 122 of the epitaxial structure 12 shown is located.

[0129] In some embodiments, considering the reflective effect of the metal reflective layer 26, the thickness of the metal reflective layer 26 ranges from 200 to 1000 nm, for example 300 to 600 nm, for example 400 nm, for example 500 nm. The thickness of the second insulating layer 322 ranges from 200 to 1000 nm, for example 200 to 400 nm, for example 400 to 600 nm.

[0130] In some embodiments, the metal reflective layer 26 is located above the upper surface 121 of the epitaxial structure 12, and is not disposed above the substrate 10 not covered by the epitaxial structure 12, so as to ensure that the metal reflective layer 26 is as flat as possible. Preferably, the metal reflective layer 26 is located only directly above the upper surface of the second semiconductor layer 125, so that the formed metal reflective layer 26 is as flat as possible, and no step height difference is formed on itself and below it during the process of attaching the metal reflective layer 26 to the lower square shape, thereby avoiding problems such as water vapor erosion or metal migration, and ensuring the stability of the metal reflective layer 26.

[0131] To ensure the reflection effect, in some embodiments, the vertical projection area of ​​the metal reflective layer 26 on the upper surface of the second semiconductor layer 125 overlaps with the vertical projection areas of the first connecting electrode 41 and the second connecting electrode 42 on the upper surface of the second semiconductor layer 125. That is, the vertical projection of the metal reflective layer 26 on the horizontal plane overlaps with the vertical projections of the first connecting electrode 41 and the second connecting electrode 42 on the horizontal plane.

[0132] In some embodiments, the vertically projected area of ​​the metal reflective layer 26 on the upper surface of the second semiconductor layer 125 occupies at least 80% of the area of ​​the upper surface of the second semiconductor layer 125. The vertically projected area of ​​the plurality of second metal electrodes 22 on the upper surface of the second semiconductor layer 125 occupies less than 20% of the total area of ​​the upper surface of the second semiconductor layer 125. Alternatively, the vertically projected area of ​​the current blocking layer 64 below the second metal electrodes 22 on the upper surface of the second semiconductor layer 125 occupies less than 20% of the total area of ​​the upper surface of the second semiconductor layer 125.

[0133] In some embodiments, the second insulating layer 322 covers the upper surface and sidewalls of the metal reflective layer 26, and the first insulating layer 321 surrounding the metal reflective layer 26 is in direct contact with the second insulating layer 322, so that the first insulating layer 321 and the second insulating layer 322 tightly clamp the metal reflective layer 26, improving the overall structural stability. That is, the first insulating layer 321 around the metal reflective layer 26 is in direct contact with the upper surface of the second insulating layer 322 to completely cover the metal reflective layer 26.

[0134] In some embodiments, such as Figure 5a As shown, the minimum horizontal spacing L1 of the metal reflective layer 26 at the second opening 62 is greater than the maximum horizontal spacing L2 of the first insulating layer 321 at the second opening 62. This ensures that the formed metal reflective layer 26 is as flat as possible, preventing step differences in the topography of the underlying layers from causing step differences in the metal reflective layer 26 and the first insulating layer 321 below it, which could lead to moisture erosion or metal migration. In other words, the metal reflective layer 26 has a third opening 63 around the second opening 62, and the bottom dimension (i.e., L1) of the third opening 63 is greater than the dimension (i.e., L2) of the second opening 62 at the contact point between the first insulating layer 321 and the second insulating layer 322.

[0135] Preferably, the minimum horizontal spacing L3 of the metal reflective layer 26 at the first opening 61 is greater than the maximum horizontal spacing L4 of the first insulating layer 321 at the first opening 61. That is, the metal reflective layer 26 has a fourth opening 64 around the first opening 61, and the bottom dimension of the fourth opening 64 (i.e., L3) is greater than the dimension of the first opening 61 at the contact point between the first insulating layer 321 and the second insulating layer 322 (i.e., L4).

[0136] Preferably, the minimum horizontal spacing L1 of the metal reflective layer 26 at the second opening 62 is greater than the maximum horizontal spacing L5 of the second insulating layer 322 at the second opening 62, that is, the bottom dimension (i.e., L1) of the third opening 63 is greater than the top dimension (i.e., L5) of the second opening 62, so as to ensure that the metal reflective layer 26 can be protected and prevent the metal layer 26 from being exposed or etched. Preferably, the difference between L1 and L5 is at least 6 μm.

[0137] The dimensions of the openings mentioned above may include the opening diameter or the opening width.

[0138] In some embodiments, such as Figure 5a As shown, the top of the first opening 61 is higher than the upper surface of the first metal electrode 21, and the top of the second opening 62 is higher than the upper surface of the second metal electrode 22. The height is calculated using the lower surface 122 of the extension structure 12 as the reference plane.

[0139] As one embodiment, based on the design of the metal reflective layer 26 being flatly attached to the first insulating layer 321, the edge of the metal reflective layer 26 further has inclined sidewalls, with the upper and lower ends of the inclined sidewalls connecting to the upper and lower surfaces of the metal reflective layer 26, respectively. Preferably, the thickness of the second insulating layer 322 is 200~1000nm, and the inclination angle of the inclined sidewalls of the metal reflective layer 26 does not exceed 40°, for example, not exceeding 30° or not exceeding 20°. This prevents the edge of the metal reflective layer 26 from being pulled up onto the first insulating layer 321 during the photoresist peeling process after the negative resist coating is completed due to the relatively soft Al and Ag materials, thus enhancing its edge adhesion. Additionally, it also facilitates good continuity of the second insulating layer 322 laid above the inclined sidewalls of the metal reflective layer 26, avoiding crack formation and thus preventing moisture erosion, unstable reflectivity, or leakage channels, thereby preventing the metal reflective layer 26 from participating in conductivity.

[0140] In some embodiments, such as Figure 5a As shown, the light-emitting diode 1 may further include an insulating structure 34, a first pad electrode 51, and a second pad electrode 52. The insulating structure 34 covers a portion of the insulating layer 32, a portion of the first connecting electrode 41, and a portion of the second connecting electrode 42, primarily serving an insulating and protective function. The first pad electrode 51 is located on the insulating structure 34 and is connected to the first connecting electrode 41. The second pad electrode 52 is located on the insulating structure 34 and is connected to the second connecting electrode 42. The first pad electrode 51 and the second pad electrode 52 can be metal pads and can be formed together using the same material in the same process, thus having the same layer structure.

[0141] The light-emitting diode 1 may further include a current-blocking layer 64 and a transparent current-spreading layer 66. The current-blocking layer 64 is disposed between the second semiconductor layer 125 and the second metal electrode 22, and serves to block current. The transparent current-spreading layer 66 is disposed between the current-blocking layer 64 and the second metal electrode 22, and the transparent current-spreading layer 66 covers the current-blocking layer 64, serving to spread current and further improve the electrical characteristics of the light-emitting diode 1. Preferably, the vertical projection of the metal reflective layer 26 onto the horizontal plane does not overlap with the vertical projection of the current-blocking layer 64 onto the horizontal plane. The thickness of the current-blocking layer 64 is between 100 and 400 nm, and the material of the current-blocking layer 64 can be silicon oxide or silicon nitride. The width of the current-blocking layer 64 is larger than the width of the second metal electrode 22; typically, the bottom width of the current-blocking layer 64 is larger than the bottom width of the metal reflective layer 26, and by 2 to 6 μm. Preferably, in order to allow the metal reflective layer 26 to avoid the current blocking layer 64, the difference between L1 and L5 is at least 15 μm.

[0142] The transparent current spreading layer 66 is made of a transparent conductive material, which may include indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium-doped zinc oxide (GZO), tungsten-doped indium oxide (IWO), or zinc oxide (ZnO), but the embodiments disclosed herein are not limited thereto.

[0143] More preferably, the vertical projection of the metal reflective layer 26 onto the horizontal plane falls only within the vertical projection range of the second semiconductor layer 125 onto the horizontal plane. That is, the metal reflective layer 26 is disposed only directly above the second semiconductor layer 125, so that the formed metal reflective layer 26 is as flat as possible, and will not suffer from poor density due to the step height difference formed by the first insulating layer 321 below it and the second insulating layer 322 covering it above it when it is attached to the first insulating layer 321, which would cause problems such as water vapor erosion or metal migration in the metal reflective layer 26.

[0144] In some embodiments, the upper surface 121 of the epitaxial structure 12 located directly below the metal reflective layer 26 is continuously flat, so that the formed metal reflective layer 26 is as flat as possible.

[0145] In some embodiments, an additional metal adhesion layer, which is Ti or Cr, may be disposed between the metal reflective layer 26 and the second insulating layer 322. The thickness of the metal adhesion layer is 0.1~20nm, for example 0.5~5nm.

[0146] In one embodiment, reference is made to Figure 4aThe upper surface of the substrate 100 corresponding to the first edge region 3010 has a first protrusion structure 103, and the surface of the substrate 100 corresponding to the second edge region 3020 has a second protrusion structure 104. The height of the first protrusion structure 103 is smaller than that of the second protrusion structure 104. Similarly, since the upper surface of the substrate 100 corresponding to the first edge region 3010 is flatter than the surface of the substrate 100 corresponding to the second edge region 3020, it is beneficial to make the insulating layer and the substrate 100 adhere more tightly, thereby improving the luminous efficiency of the light-emitting diode. This, in turn, can improve the production yield of the light-emitting diode. At the same time, the etching of the first semiconductor layer material in the first edge region is relatively more thorough, which can also prevent leakage caused by incomplete etching of the first semiconductor layer material in the second edge region.

[0147] The height of the second protrusion structure 104 is equal to the height of the protrusion structure 102 on the upper surface of the substrate below the epitaxial structure 12, and is located at 2~2.5μm; the height of the first protrusion structure 103 is 1~2μm.

[0148] The light-emitting diode formed using the method described in Example 1 Figure 4a LEDs in Figure 1c The light-emitting diodes formed in the process were subjected to performance tests, and the test data is shown in Table 1.

[0149] Table 1

[0150] plan Voltage brightness band Figure 1c 3.279 1145.7 454.9 Figure 4a 3.252 1173.0 454.6

[0151] As shown in Table 1 above, compared with existing technologies... Figure 1c The light-emitting diode in this embodiment 1 Figure 4a The voltage and brightness of the LEDs shown are significantly improved. Therefore, this invention is beneficial for improving the electrical yield and luminous efficiency of LEDs.

[0152] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method of fabricating a light emitting diode, characterized by, The method comprises: providing a substrate, an upper surface of the substrate being a patterned upper surface, forming an epitaxial structure on the upper surface of the substrate, the epitaxial structure comprising a first semiconductor layer, an active layer and a second semiconductor layer formed in sequence on the surface of the substrate; etching the second semiconductor layer and the active layer in sequence from the surface of the second semiconductor layer downwards to expose an upper surface of a part of the first semiconductor layer at the edge of the epitaxial structure; defining the upper surface of the part of the first semiconductor layer exposed at the edge of the epitaxial structure as a sub-mesa; simultaneously etching the sub-mesa and a part of the epitaxial structure close to the sub-mesa to the substrate in the same etching process to form a cutting path region on the surface of the substrate, wherein the sub-mesa formed at the edge region of the epitaxial structure corresponds to a first cutting path region, and the part of the epitaxial structure close to the sub-mesa corresponds to a second cutting path region, the thickness of the substrate corresponding to the first cutting path region being smaller than the thickness of the substrate corresponding to the second cutting path region.

2. The method of claim 1, wherein the substrate is a sapphire substrate. The substrate is a patterned substrate, the patterned substrate comprising a planar structure and a plurality of protruding structures formed on the surface of the planar structure and arranged at intervals.

3. The method of claim 2, wherein the substrate is a sapphire substrate. The method of etching the edge region of the epitaxial structure to the substrate further comprises: simultaneously etching the sub-mesa corresponding to the first edge region and the epitaxial structure corresponding to the second edge region to the substrate; wherein the surface of the substrate corresponding to the first edge region forms a flat region, and the flat region forms the first cutting path region, and the surface of the substrate corresponding to the second edge region forms a second protruding structure, and the substrate region corresponding to the second protruding structure forms the second cutting path region.

4. The method of claim 2, wherein the substrate is a sapphire substrate. The method of etching the edge region of the epitaxial structure to the substrate further comprises: simultaneously etching the sub-mesa corresponding to the first edge region and the epitaxial structure corresponding to the second edge region to the substrate; wherein the surface of the substrate corresponding to the first edge region forms a first protruding structure, and the substrate region corresponding to the first protruding structure forms the first cutting path region; the surface of the substrate corresponding to the second edge region forms a second protruding structure, and the substrate region corresponding to the second protruding structure forms the second cutting path region, the height of the first protruding structure being lower than the height of the second protruding structure.

5. A light emitting diode, characterized by The method comprises: a substrate, an epitaxial structure formed on the upper surface of the substrate, the epitaxial structure comprising a first semiconductor layer, an active layer and a second semiconductor layer formed in sequence on the surface of the substrate; an upper surface of a part of the first semiconductor layer exposed at the edge of the epitaxial structure is defined as a sub-mesa; an edge region surrounding the epitaxial structure and exposing the substrate, the edge region comprising a first edge region and a second edge region, the second edge region being closer to the epitaxial structure than the first edge region; etching the first edge region and the second edge region to form a first cutting path region and a second cutting path region on the substrate, the first cutting path region and the second cutting path region being formed by simultaneously etching the sub-mesa and a part of the epitaxial structure close to the sub-mesa to the substrate in the same etching process; The upper surface of the substrate corresponding to the first edge region is a first convex structure, the upper surface of the substrate corresponding to the second edge region has a second convex structure, and the height of the second convex structure is higher than the height of the first convex structure; or the upper surface of the substrate corresponding to the first edge region is a flat region, the upper surface of the substrate corresponding to the second edge region has a second convex structure, and the substrate surface of the flat region is flat.

6. The light emitting diode of claim 5, wherein: The height of the first convex structure of the substrate is 1-2 μm or less than 1 μm.

7. The light emitting diode of claim 5, wherein: The height of the second convex structure of the substrate is 1-2 μm or less than 1 μm.

8. The light emitting diode of claim 5, wherein: At least a part of the sidewall of the epitaxial structure in the circumferential direction continuously extends from the second semiconductor layer to the edge region, and there is no step on the at least a part of the sidewall.

9. The light emitting diode of claim 5, wherein: All of the sidewall of the epitaxial structure in the circumferential direction continuously extends from the second semiconductor layer to the edge region, and there is no step on the all of the sidewall, the second edge region surrounds the epitaxial structure, and the first edge region surrounds the second edge region.

10. The light emitting diode of claim 5, wherein: Part of the sidewall of the epitaxial structure in the circumferential direction continuously extends from the second semiconductor layer to the edge region, and there is no step on the part of the sidewall, and a step is arranged on the remaining sidewall other than the part of the sidewall, and the step is used to arrange an electrode.

11. The light emitting diode of claim 5, wherein: Further comprising an insulating layer, the insulating layer covers the edge region, the first convex structure and the second convex structure of the substrate are conical, and the sidewall of the first convex structure or the second convex structure is arc-shaped.

12. The light emitting diode of claim 5, wherein: The width of the edge region of the substrate is 4-20 μm.

13. The light emitting diode of claim 5, wherein: The width of the first edge region is greater than the width of the second edge region.

14. A light emitting diode, comprising: Comprise: a substrate, an epitaxial structure formed on the upper surface of the substrate, the epitaxial structure comprising a first semiconductor layer, an active layer and a second semiconductor layer formed on the surface of the substrate in sequence; the upper surface of the part of the first semiconductor layer exposed by the edge of the epitaxial structure is defined as a sub-mesa; an edge region surrounding the epitaxial structure and exposing the substrate; the edge region comprises a first edge region and a second edge region, and the second edge region is closer to the epitaxial structure than the first edge region; etching the first edge region and the second edge region to form a first cutting track region and a second cutting track region on the substrate, the first cutting track region and the second cutting track region are simultaneously etched in the same etching process to form the sub-mesa and the part of the epitaxial structure close to the sub-mesa to the substrate; the thickness of the substrate corresponding to the first edge region is less than the thickness of the substrate corresponding to the second edge region.

15. The light emitting diode of claim 14, wherein: The upper surface of the substrate corresponding to the first edge region has a first convex structure, and the upper surface of the substrate corresponding to the second edge region has a second convex structure, and the height of the second convex structure is higher than the height of the first convex structure.

16. The light emitting diode of claim 14, wherein: The upper surface of the substrate corresponding to the first edge region is a flat region, and the upper surface of the substrate corresponding to the second edge region has a second convex structure, and the substrate surface of the flat region is flat.

17. The light emitting diode of claim 14, wherein: Further comprising an insulating layer, the insulating layer covers the edge region.

18. The light emitting diode of claim 14, wherein: The width of the first edge region is greater than the width of the second edge region.

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