Opcode storage for on-die microprocessor

Abstract

This application is directed to opcode storage for on-die microprocessors. A microprocessor can be formed on a die with a memory array. Opcodes for the microprocessor can be stored in the memory array, possibly along with other data (e.g., trace or statistical data) for use by or generated by the on-die microprocessor. A wear leveling algorithm can cause a number of rows within the memory array to not be used to store user data at any given time, and these rows can be used to store the opcodes and possibly other data for the on-die microprocessor. The on-die microprocessor can be initiated and run based on the opcodes stored in the memory array.

Description

[0001] Cross-references

[0002] This patent application is the national phase of International Patent Application No. PCT / US2021 / 030812, filed May 5, 2021, entitled "Operational Code Storage for an On-Die Microprocessor," filed by Manning et al., which claims priority to U.S. Patent Application No. 16 / 878,226, filed May 19, 2020, entitled "Operational Code Storage for an On-Die Microprocessor," both of which are assigned to this assignee and are expressly incorporated herein by reference in their entirety. Technical Field

[0003] The technical field relates to opcode storage for on-die microprocessors. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to support one of two states, often represented by logic 1 or logic 0. In some instances, a single memory cell can support more than two states, any of which can be stored. To access the stored information, components of the device can read or sense at least one stored state in the memory device. To store information, components of the device can write to or program the states in the memory device.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, and phase-change memory (PCM). Memory devices can be volatile or non-volatile. Non-volatile memory, such as FeRAM, can maintain its stored logic state for a long time, even without external power. For example, volatile memory devices like DRAM may lose their stored state when disconnected from external power. FeRAM can achieve densities similar to volatile memory but can have non-volatile characteristics because it uses ferroelectric capacitors as storage devices. Summary of the Invention

[0006] Describe an apparatus. The apparatus may include a semiconductor die comprising: a microprocessor; a memory array coupled to the microprocessor; and a bus operable to receive data from a source external to the semiconductor die, wherein: the memory array is configured to store data received via the bus in a first subset of memory cells of the memory array; and the memory array is configured to store instructions executable by the microprocessor in a second subset of memory cells of the memory array. The apparatus may also include one or more pins, solder balls, or bonding pads coupled to the bus, wherein the one or more pins, solder balls, or bonding pads are coupled to the source external to the semiconductor die.

[0007] Describe a method. The method may include: storing instructions for a microprocessor contained on the same die as the memory array within the memory array; executing the instructions via the microprocessor; after executing the instructions via the microprocessor, receiving a command from a source outside the die to write data to the memory array; and writing the data to the memory array at least in part based on the command.

[0008] Describe a device. The device may include: a microprocessor contained on a die; and a memory array contained on the die, wherein the memory array includes: a first number of memory cell rows for storing instructions executable by the microprocessor; and a second number of the memory cell rows for storing data associated with access commands received by the device. Attached Figure Description

[0009] Figure 1 This document describes an example of a system that supports opcode storage for on-chip microprocessors, based on the examples disclosed herein.

[0010] Figure 2 This document describes an example of a memory die that supports opcode storage for a microprocessor on a die, based on the examples disclosed herein.

[0011] Figure 3 This document describes an example of a memory die architecture that supports opcode storage for on-die microprocessors, based on the examples disclosed herein.

[0012] Figure 4 This document describes an example of an instruction storage scheme that supports opcode storage for on-chip microprocessors, based on the examples disclosed herein.

[0013] Figure 5A block diagram is shown of a memory die supporting opcode storage for a microprocessor on a die, according to aspects of this disclosure.

[0014] Figure 6 and 7 The flowchart illustrates one or more methods for supporting opcode storage for on-chip microprocessors, based on the examples disclosed herein. Detailed Implementation

[0015] In some cases, a system-on-a-die (SoC) can contain a microprocessor. If the SoC is entirely self-contained, then the opcodes used by the microprocessor can also be stored on the die.

[0016] In some systems, opcodes for the microprocessor can be stored in read-only memory (ROM). However, systems that store opcodes in ROM may not have the ability to modify the opcodes during runtime, or due to the read-only nature of ROM, they may not have the ability to use ROM to store other data generated by the microprocessor or otherwise associated with operating the microprocessor.

[0017] As described herein, a system-on-a-die (SoC) may include a non-volatile memory array (e.g., a ferroelectric random access memory (FeRAM) array) supporting both read and write operations, and a microprocessor on the same semiconductor die, with opcodes for the microprocessor stored in the non-volatile memory array. The array may also be used to store user data, with opcodes stored in memory cells of the array not used for storing user data, which may refer to data written and read by a host device of the SoC and exchanged via a data (DQ) bus of the SoC. For example, the memory array may provide memory-level memory for the host device. Other data associated with the microprocessor (e.g., trace or statistics that the microprocessor may generate or otherwise use, such as data related to the operation and management of the array) may be stored similarly as opcodes for the microprocessor. For example, storing opcodes and other data associated with the microprocessor in the same writable array used to store user data can save die space (e.g., by eliminating the need for a dedicated ROM for the microprocessor), thereby increasing the flexibility of microprocessor use (e.g., monitoring and managing array performance), and other benefits that can be understood by those skilled in the art.

[0018] In some cases, on-die systems can employ wear leveling algorithms for the array, whereby data within the memory array can be relocated or otherwise rotated between different physical addresses within the array to evenly distribute the wear associated with different memory cells within the array. To support wear leveling, a certain number of memory cell rows (or possibly other groups) may not be used to store user data at any given time during array operation. These rows may be referred to as "gap" or "skip" rows. Opcodes (or other data) for the on-die microprocessor can be stored in a certain number of skip rows within the array, and these opcodes can be used to start and run the on-die microprocessor. Other rows within the array can be used to store user data.

[0019] Initially, in reference Figure 1-2 The features of this disclosure are described in the context of the memory system and the die. (See references...) Figure 3-4 The features of this disclosure are described in the context of the memory die architecture and instruction storage scheme described herein. (See references to...) Figure 5-7 The device diagrams and flowcharts for storing opcodes for a microprocessor on a die further illustrate and describe these and other features of this disclosure, and are further described with reference to the device diagrams and flowcharts.

[0020] Figure 1 This document describes an example of a system 100 supporting opcode storage for an on-die microprocessor, based on the examples disclosed herein. System 100 may include a host device 105, a memory device 110, and multiple channels 115 coupling the host device 105 to the memory device 110. System 100 may include one or more memory devices 110, but aspects of said one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110). As described herein, memory device 110 may include a microprocessor 175 on the same die 160 as memory array 170.

[0021] System 100 may include portions of electronic devices such as computing devices, mobile computing devices, wireless devices, graphics processing devices, vehicles, or other systems. For example, system 100 may describe aspects of computers, laptop computers, tablet computers, smartphones, cellular phones, wearable devices, networked devices, vehicle controllers, etc. Memory device 110 may be a component of the system used to store data for one or more other components of system 100.

[0022] At least a portion of system 100 may be an example of host device 105. Host device 105 may be an example of a processor or other circuitry within a device that uses memory to execute processes, such as in a computing device, mobile computing device, wireless device, graphics processing device, computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, vehicle controller, or other fixed or portable electronic device, and other examples. In some examples, host device 105 may refer to the hardware, firmware, software, or a combination thereof that implements the functions of external memory controller 120. In some examples, external memory controller 120 may be referred to as a host or host device 105.

[0023] Memory device 110 may be a separate device or component operable to provide physical memory address / space that can be used or referenced by system 100. In some instances, memory device 110 may be configurable to work with one or more different types of host devices. Signaling between host device 105 and memory device 110 may be operable to support one or more of the following: modulation schemes for modulating signals, various pin configurations for transmitting signals, various physical package dimensions for host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing conventions, or other factors.

[0024] Memory device 110 may be operable to store data for components of host device 105. In some instances, memory device 110 may act as a slave device to host device 105 (e.g., responding to and executing commands provided by host device 105 via external memory controller 120). Such commands may include one or more of write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands.

[0025] The host device 105 may include an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or one or more other components such as one or more peripheral components or one or more input / output controllers. The components of the host device may be coupled to each other using bus 135.

[0026] Processor 125 may be operable to provide control or other functionality for at least a portion of system 100 or host device 105. Processor 125 may be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof. In such instances, processor 125 may be an instance of a central processing unit (CPU), graphics processing unit (GPU), general-purpose GPU (GPGPU), or system-on-a-chip (SoC), as well as other instances. In some instances, external memory controller 120 may be implemented by processor 125 or be part of said processor.

[0027] BIOS component 130 may be a software component containing a BIOS operating as firmware, which can initialize and run various hardware components of system 100 or host device 105. BIOS component 130 may also manage data flow between processor 125 and various components of system 100 or host device 105. BIOS component 130 may contain programs or software stored in one or more read-only memory (ROM), flash memory, or other non-volatile memory.

[0028] Memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-N). Memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more groups, one or more tiles, one or more segments), wherein each memory cell can be used to store at least one bit of data. Memory device 110 containing two or more memory dies may be referred to as a multi-die memory or multi-die package, or a multi-chip memory or multi-chip package.

[0029] The device memory controller 155 may include circuitry, logic, or components for controlling the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions that enable the memory device 110 to perform various operations, and may be used to receive, transmit, or execute commands, data, or control information related to components of the memory device 110. The device memory controller 155 may be used to communicate with one or more of the external memory controller 120, the one or more memory dies 160, or the processor 125. In some instances, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with a local memory controller 165 of the memory die 160.

[0030] In some instances, memory device 110 may receive data or commands, or both, from host device 105. For example, memory device 110 may receive a write command instructing memory device 110 to store data (which may be referred to as user data) for host device 105, or a read command instructing memory device 110 to provide data stored in memory die 160 to host device 105.

[0031] A local memory controller 165 (e.g., local to memory die 160) may be operable to control the operation of memory die 160. In some instances, the local memory controller 165 may be operable to communicate with device memory controller 155 (e.g., to receive or transmit data or commands, or both). In some instances, memory device 110 may not include device memory controller 155, and either the local memory controller 165 or the external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 may be operable to communicate with device memory controller 155, with other local memory controllers 165, or directly with external memory controller 120 or processor 125, or combinations thereof. Examples of components that may be included in the device memory controller 155 or the local memory controller 165, or both, may include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for transmitting signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating the received signals, an encoder for encoding or modulating the signals to be transmitted, or various other circuitry or controllers operable to support the operation of the described device memory controller 155 or the local memory controller 165, or both.

[0032] In some cases, the memory die 160 may contain one or more microprocessors 175. For example, the memory die 160 may contain one microprocessor 175, a group of microprocessors 175 per memory array 170, or some other configuration. Opcodes for the on-die microprocessors 175 may be stored on the die. For example, the opcodes may be stored in the memory array 170 of the memory die 160 (e.g., a non-volatile memory array, such as, as an example, a FeRAM memory array).

[0033] The microprocessor 175 can be started and run using code stored in memory array 170. For example, the boot address and complete operating procedure for the microprocessor 175 may be stored in memory array 170. In some cases, the opcode for the microprocessor 175 stored in memory array 170 may be or contain BIOS code (e.g., firmware) for the microprocessor 175, i.e., BIOS code that is separate and isolated from any BIOS code for host device 105, and therefore separate and isolated from any BIOS code provided by BIOS component 130. In some cases, additional data associated with the microprocessor 175 may also be stored in memory array 170, such as data related to monitoring and managing the performance and operation of memory array 170, and which is not accessible to host device 105 (e.g., outside the address space addressable by host device 105 via command and address (CA) channel 186 (which may be alternatively referred to as the CA bus)). In some cases, some or all of the structures or functions of the local memory controller 165, the device memory controller 155, or other controllers described herein as possibly included in the memory device 110 may alternatively be included in or executed by the microprocessor 175, and thus the memory device 110 may or may not include any separate controller.

[0034] External memory controller 120 may be operable to enable the transfer of one or more of information, data, or commands between components of system 100 or host device 105 (e.g., processor 125) and memory device 110. External memory controller 120 may translate or interpret communications exchanged between components of host device 105 and memory device 110. In some instances, external memory controller 120 or other components of system 100 or host device 105, or the functionality described herein, may be implemented by processor 125. For example, external memory controller 120 may be hardware, firmware, or software, or a combination thereof, implemented by processor 125 or other components of system 100 or host device 105. Although external memory controller 120 is depicted as external to memory device 110, in some instances, external memory controller 120 or the functionality described herein may be implemented by one or more components of memory device 110 (e.g., device memory controller 155, local memory controller 165), or vice versa.

[0035] Components of host device 105 may exchange information with memory device 110 using one or more channels 115. Channels 115 may be operable to support communication between external memory controller 120 and memory device 110. Each channel 115 may be an example of a transmission medium carrying information between host device 105 and memory device. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. Signal paths may be examples of conductive paths operable to carry signals. For example, channel 115 may include a first terminal comprising one or more pins or pads at host device 105 and one or more pins or pads at memory device 110. Pins may be examples of conductive input or output points of devices of system 100, and pins may be operable to act as part of a channel.

[0036] Channel 115 (and associated signal paths and terminals) may be dedicated to transmitting one or more types of information. For example, channel 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or combinations thereof. In some instances, signaling may be transmitted on channel 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of the signal may be registered for each clock cycle (e.g., on the rising or falling edge of the clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of the signal may be registered for each clock cycle (e.g., on both the rising and falling edges of the clock signal).

[0037] Figure 2 This document describes an example of a memory die 200 supporting opcode storage for an on-die microprocessor, based on the examples disclosed herein. The memory die 200 may be a reference. Figure 1 Examples of memory die 160 described herein. In some instances, memory die 200 may be referred to as a memory chip, memory device, or electronic memory device. Memory die 200 may include one or more memory cells 205, each of which may be programmable to store different logical states (e.g., one programmed state from a set of two or more possible states). For example, memory cell 205 may be operable to store one bit of information at a time (e.g., logic 0 or logic 1). In some instances, memory cell 205 (e.g., a multi-level memory cell) may be operable to store more than one bit of information at a time (e.g., logic 00, logic 01, logic 10, logic 11). In some instances, memory cells 205 may be arranged in an array, as described in the reference. Figure 1 The memory array 170 is described. The memory die 200 may contain a microprocessor 270, which may be referenced. Figure 1 An example of the microprocessor 175 described.

[0038] Certain examples described herein are presented in the context of FeRAM memory arrays; however, it should be understood that the teachings herein are applicable to the context of any class of memory arrays, where FeRAM may be merely an illustrative example. In the case where memory cell 205 is a ferroelectric memory cell, memory cell 205 may store states representing programmable states (e.g., polarization states or dielectric charges) in a capacitor. For example, memory cell 205 may include a capacitor 240 having a ferroelectric material to store charges and / or polarizations representing programmable states. Memory cell 205 may include logic storage components, such as capacitor 240 and switching component 245. Capacitor 240 may be an example of a ferroelectric capacitor. A first node of capacitor 240 may be coupled to switching component 245, and a second node of capacitor 240 may be coupled to plate line 220. Switching component 245 may be an example of a transistor or any other type of switching device that selectively establishes or de-establishes electronic communication between two components.

[0039] The memory die 200 may include access lines (e.g., word lines 210, digital lines 215, and board lines 220) arranged in a pattern such as a grid. Access lines may be wires coupled to memory cells 205 and may be used to perform access operations on memory cells 205. In some instances, word lines 210 may be referred to as row lines. In some instances, digital lines 215 may be referred to as column lines or bit lines. References to access lines, row lines, column lines, word lines, digital lines, bit lines, or board lines, or the like, are interchangeable without loss of understanding or operation. Memory cells 205 may be located at the intersections of word lines 210, digital lines 215, and / or board lines 220.

[0040] Operations such as reading and writing can be performed on memory cells 205 by activating or selecting access lines such as word line 210, digital line 215, and / or board line 220. A single memory cell 205 can be accessed at its intersection by biasing the word line 210, digital line 215, and board line 220 (e.g., applying a voltage to the word line 210, digital line 215, or board line 220). Activating or selecting a word line 210, digital line 215, or board line 220 may involve applying a voltage to the corresponding line.

[0041] Access to memory cell 205 can be controlled via row decoder 225, column decoder 230, and board driver 235. For example, row decoder 225 receives a row address from local memory controller 265 and activates word line 210 based on the received row address. Column decoder 230 receives a column address from local memory controller 265 and activates digital line 215 based on the received column address. Board driver 235 receives a board address from local memory controller 265 and activates board line 220 based on the received board address.

[0042] Selecting or deselecting memory cell 205 can be achieved by activating or deactivating switch assembly 245. Capacitor 240 can be electrically connected to digital line 215 using switch assembly 245. For example, when switch assembly 245 is deactivated, capacitor 240 can be isolated from digital line 215, and when switch assembly 245 is activated, capacitor 240 can be coupled to digital line 215.

[0043] Word line 210 may be a conductive line for electronic communication with memory cell 205 to perform access operations on memory cell 205. In some architectures, word line 210 may be in electronic communication with the gate of switching component 245 of memory cell 205, and may be operable to control the switching component 245 of memory cell 205. In some architectures, word line 210 may be in electronic communication with the node of capacitor of memory cell 205, and memory cell 205 may not include a switching component.

[0044] Digital line 215 may be a wire connecting memory cell 205 to sensing component 250. In some architectures, memory cell 205 may be selectively coupled to digital line 215 during portions of an access operation. For example, word line 210 and switching component 245 of memory cell 205 may be operable to selectively couple and / or isolate memory cell 205 and digital line 215. In some architectures, memory cell 205 may be in electronic communication (e.g., constant) with digital line 215.

[0045] Board line 220 may be a wire for electronic communication with memory cell 205, used to perform access operations on memory cell 205. Board line 220 may be in electronic communication with a node (e.g., bottom of cell) of capacitor 240. Board line 220 is configured to cooperate with digital line 215 to bias capacitor 240 during access operations of memory cell 205.

[0046] Sensing component 250 can determine the state (e.g., polarization state or charge) stored on capacitor 240 of memory cell 205 and determine the logic state of memory cell 205 based on the detected state. Sensing component 250 may include one or more sensing amplifiers to amplify the signal output from memory cell 205. Sensing component 250 can compare the signal received from memory cell 205 across digital line 215 with reference 255 (e.g., reference voltage). The detected logic state of memory cell 205 may be provided as an output of sensing component 250 (e.g., provided to input / output 260) and may indicate the detected logic state to another component of memory device 110 including memory die 200.

[0047] The local memory controller 265 can control the operation of the memory cell 205 through various components (e.g., row decoder 225, column decoder 230, board driver 235, and sensing component 250). The local memory controller 265 can be a reference. Figure 1Examples of the described local memory controller 165. In some instances, one or more of the row decoder 225, column decoder 230, board driver 235, and sensing components 250 may be located in the same location as the local memory controller 265. The local memory controller 265 may be operable to receive one or more commands or data from one or more different memory controllers (e.g., an external memory controller 120 associated with host device 105, another controller associated with memory die 200), translate the commands or data (or both) into information usable by memory die 200, perform one or more operations on memory die 200, and transfer data from memory die 200 to host device 105 based on the performance of one or more operations. The local memory controller 265 may generate row signals and column address signals to activate target word line 210, target digital line 215, and target board line 220. The local memory controller 265 may also generate and control various voltages or currents used during operation of memory die 200. Generally, the magnitude, shape, or duration of the applied voltage or current discussed herein may vary and may differ for the various operations discussed when operating the memory die 200.

[0048] The local memory controller 265 may be operable to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations may include write operations, read operations, refresh operations, precharge operations, or activation operations, etc. In some instances, access operations may be performed or otherwise coordinated by the local memory controller 265 in response to various access commands (e.g., from the host device 105). The local memory controller 265 may be operable to perform other access operations not listed herein or other operations related to the operation of the memory die 200 that are not directly related to accessing the memory cells 205.

[0049] The local memory controller 265 is operable to perform write operations (e.g., programming operations) on one or more memory cells 205 of the memory die 200. During a write operation, the memory cells 205 of the memory die 200 can be programmed to store a desired logical state. The local memory controller 265 can identify the target memory cell 205 on which the write operation will be performed. The local memory controller 265 can identify target word lines 210, target digital lines 215, and target board lines 220 coupled to the target memory cell 205. The local memory controller 265 can activate the target word lines 210, target digital lines 215, and target board lines 220 (e.g., apply a voltage to word lines 210, digital lines 215, or board lines 220) to access the target memory cell 205. The local memory controller 265 can apply a specific signal (e.g., a write pulse) to the digital line 215 during a write operation to store a specific state (e.g., charge) in the capacitor 240 of the memory cell 205. The pulse used for the write operation may contain one or more voltage levels over a duration.

[0050] Local memory controller 265 is operable to perform read operations (e.g., sensing operations) on one or more memory cells 205 of memory die 200. During a read operation, a logical state stored on the memory cells 205 of memory die 200 can be determined. Local memory controller 265 can identify the target memory cell 205 on which the read operation will be performed. Local memory controller 265 can identify target word lines 210, target digital lines 215, and target board lines 220 coupled to the target memory cell 205. Local memory controller 265 can activate the target word lines 210, target digital lines 215, and target board lines 220 (e.g., by applying a voltage to word lines 210, digital lines 215, or board lines 220) to access the target memory cell 205. The target memory cell 205 can transmit a signal to sensing component 250 in response to applying a bias voltage to the access lines. Sensing component 250 can amplify the signal. The local memory controller 265 can activate the sensing component 250 (e.g., a latching sensing component) and then compare the signal received from the memory cell 205 with a reference 255. Based on the comparison, the sensing component 250 can determine the logic state stored in the memory cell 205.

[0051] The memory die 200 may also include one or more microprocessors 270, which in some cases may be coupled to a local memory controller 265. Alternatively, the microprocessor may be coupled to any other aspect of the memory die 200 (e.g., row decoder 225, column decoder 230, board driver 235, input / output 260). And in some cases, some or all of the structures or functions belonging to the local memory controller 265 herein may alternatively be included in or executed by the microprocessor 270 (e.g., in some embodiments, the local memory controller 265 may not exist).

[0052] For example, according to the instances described herein, a microprocessor may monitor and potentially manage one or more aspects of the performance or operation of the memory cell array 205. A subset of the memory cells 205 in the array may be used to store opcodes or other data for the microprocessor 270 (e.g., performance statistics, performance log data, or other data related to the performance or operation of the array). For example, the microprocessor 270 may be used to store opcodes and / or other data in one or more rows of memory cells 205 (each row coupled to a corresponding word line 210). In some cases, the rows of memory cells 205 used to store opcodes and / or other data for the microprocessor 270 may be skipped rows and may be used for such uses, at least in part due to wear leveling procedures for the array. During operation of the array and memory die 200, wear leveling procedures may (e.g., periodically or on a otherwise scheduled or commanded basis) rotate the storage orientation of data within the array to equalize (normalize, balance, distribute, homogenize) the amount of wear associated with different memory cells 205 within the array. Therefore, in some cases, according to the wear leveling procedure, the physical orientation of the opcodes and / or other data used by the microprocessor 270 can change (rotate, change) over time when operating the array.

[0053] Figure 3 This document describes an example of a memory die architecture 300 that supports opcode storage for a microprocessor on a die, based on the examples disclosed herein. The memory die architecture 300 may include a memory die 305, which may be as described in the references... Figure 1 The memory die 160 described or as referenced Figure 2 Examples of aspects of the described memory die 200. In some instances, the memory die 305 may be an example of a semiconductor memory die or a silicon memory device.

[0054] Memory die 305 may include memory array 310, which may be as referenced. Figure 1 The memory array 170 described or as referenced Figure 2Examples of aspects of the described array. Memory array 310 may be a collection of memory cells (e.g., one or more grids, one or more groups, one or more tiles, one or more segments), wherein each memory cell is operable to store at least one bit of data. Where the memory array comprises one or more groups, each of the one or more groups may comprise one or more subarrays.

[0055] The memory die 305 may also include a controller 315 coupled to the memory array 310. The controller 315 may be as described in the reference. Figure 1 The described device memory controller 155 or local memory controller 165 or as referenced Figure 2 Examples of aspects of the described local memory controller 265 are described. Controller 315 may be operable to control the operation of memory array 310. For example, in the case where memory array 310 comprises one or more groups, controller 315 may be operable to access one of the one or more groups in parallel with accessing another of the one or more groups. Additionally, when accessing a group, controller 315 may access one subarray within the group at a time. Thus, when accessing multiple groups in parallel, controller 315 may be operable to access a first subarray within a first group, a second subarray within a second group, and so on. Controller 315 may also include or be coupled to a decoding circuitry system, such as those described in reference [reference needed]. Figure 2 The described one or more row decoders 225, column decoders 230, or board drivers 235, or command decoders for decoding commands received from a source outside the memory die 305 (e.g., host device 105).

[0056] Controller 315 may be coupled to bus 340, through which controller 315 may receive user data from and transmit user data to a source outside memory die 305 (e.g., host device 105). Therefore, bus 340 may also carry commands (e.g., access commands) and address information associated with the user data. Controller 315 may be operable to store data received via bus 340 in a subset of memory array 310 (e.g., a subset of memory cells within memory array 310). Bus 340 may be coupled to one or more pads 335 contained in memory die 305. Pads 335 may be coupled to, as referenced... Figure 1 Any number of channels 115 described (including DQ channel 190 and CA channel 186 and other instances) are coupled (e.g. via pins, solder balls, bonding pads, bonding wires or any other type of interconnect, or any combination thereof).

[0057] A subset of the memory array 310 used for storing user data may be associated with a logical address space, wherein commands associated with user data received via bus 340 may be identified by referring to logical addresses within the logical address space or otherwise associated with corresponding user data. For example, a read or write command may contain a logical address or be otherwise associated with a logical address (e.g., received in parallel with or at a certain defined timing relative to a logical address), and the controller 315 may identify the location within the memory array 310 for reading or writing user data according to the logical address. Physical storage locations within the memory array 310 (e.g., groups, subarrays, rows, columns, memory cells) may each have a corresponding physical address within the physical address space, and the controller 315 may maintain and utilize the logical-to-physical address mapping to associate logical addresses with physical addresses within the memory array. In some cases, logical addresses may be alternatively referred to as virtual addresses, and the logical address space may be alternatively referred to as a virtual address space.

[0058] In some cases, the physical address space associated with memory array 310 may be larger than the logical address space associated with commands and user data exchanged via bus 340 (e.g., the logical address space used by host device 105). A first subset of the physical locations of memory array 310 may have physical addresses corresponding to logical addresses present in the logical address space, and memory cells within the first subset of the physical locations of memory array 310 may be accessible to devices outside memory die 305 (e.g., host device 105) and usable for storing user data. A second subset of the physical locations of memory array 310 may have physical addresses corresponding to logical addresses not present in the logical address space, and this second subset of the physical locations of memory array 310 may be inaccessible or unusable for storing user data to devices outside memory die 305 (e.g., host device 105).

[0059] The memory die 305 may also include a microprocessor 320. In some instances, the microprocessor 320 may include or be an instance of a central processing unit (CPU). The microprocessor 320 may be configured to execute instructions. Executable instructions for the microprocessor 320 may be referred to as opcodes for the microprocessor 320. The microprocessor 320 may execute such instructions, for example, to monitor and manage (control) various operational aspects of the memory array 310 or other aspects of the memory die 305. In some cases, the microprocessor may be coupled to a pad 335 and configured to exchange signals with a device external to the memory die 305 (e.g., host device 105) via the pad 335. Alternatively or concurrently, the microprocessor may be coupled to a device such as... Figure 3The controller 315 is coupled as shown in the example. And in some cases, the microprocessor 320 may be directly coupled to the memory array 310. For example, one or more structures or functions belonging to the controller 315 herein may alternatively be contained in or executed by the microprocessor 320, and in some cases, the memory die 305 may not have a controller 315. Although in Figure 3 The example shows a microprocessor 320, but it should be understood that in some cases, the memory die 305 may contain multiple microprocessors 320 (e.g., one on-die microprocessor 320 per group of memory array 310, or one on-die microprocessor 320 per memory array 310, wherein the memory die 305 contains multiple memory arrays 310).

[0060] As will be appreciated by those skilled in the art, the inclusion of a microprocessor 320 in the memory die 305 can support a variety of functions. For example, the microprocessor 320 can be configured to prevent or repair errors related to row hammering in the memory array 310. Row hammering can refer to the frequent and repeated activation of one or more identical word lines (and therefore rows of memory cells). For some types of memory (e.g., FeRAM), if rows are repeatedly accessed within a certain time interval (e.g., rows are hammered), leakage, parasitic current, or charge pumping caused by repeated access to one or more rows can lead to data corruption in one or more affected (activated, accessed) rows and one or more physically adjacent (e.g., adjacent) rows that are not accessed. The on-die microprocessor 320 can be configured to detect row hammering events (e.g., the number of times the same row is accessed above a threshold number of times within a threshold duration) and mitigate or prevent the effects of row hammering events (e.g., by physically relocating the data associated with the hammered row, adjusting the logical-to-physical address mapping associated with the hammered row or user data stored at the hammered row, blocking access to the hammered row or memory array 310 via bus 340 for at least a certain duration, or any combination thereof).

[0061] Alternatively, the microprocessor 320 may be configured to manage or otherwise support the execution of a wear leveling procedure for the memory array 310. Wear leveling may include, for example, transferring data from one physical location within the memory array 310 (or across memory arrays 310 or between memory arrays 310, such as in the case where the memory die 305 contains multiple memory arrays 310) to another physical location and adjusting the logical-to-physical address mapping associated with the relocated data (e.g., so that the associated logical address is associated with a new physical address corresponding to the new physical location to which the data is relocated). Wear leveling prevents memory cells within the memory array 310 from being written to or read more (e.g., significantly more) than other memory cells within the memory array 310, and thus reduces the difference between a first wear level of the first set of memory cells and a second wear level of the second set of memory cells. Excessive access reduces the lifespan of overused memory cells compared to those that are not accessed so frequently, and thus wear leveling protects the memory device from overuse of individual memory cells, which can lead to premature memory cell failure.

[0062] Alternatively, the microprocessor 320 may be configured to perform field device fine-tuning optimization. Fine-tuning parameters may refer to parameters (e.g., timing, voltage, current, or other parameters) used to operate the configurable memory array 310 after the memory die 305 has been manufactured. In some cases, fine-tuning parameters may be set based on the melting of a single-programmable memory element (e.g., a fuse or antifuse) after the memory die 305 has been manufactured, such as during post-manufacturing testing or before the memory die 305 is used (deployed). However, the on-die microprocessor 320 may be configured to monitor one or more metrics (characteristics) of array operation (e.g., data error rate or other field failure conditions, operating temperature, operating voltage, etc.) and, based on the monitored metrics, adjust (modify, change) one or more fine-tuning parameters, including during the operation of the memory die 305 and memory array 310 or after the memory die 305 and memory array 310 have been deployed. For example, if the temperature associated with memory die 305 changes, microprocessor 320 can modify the values ​​of parameters (e.g., voltage or timing parameters) used to operate memory array 310 based on the temperature. As another example, microprocessor 320 can be configured to detect and counteract (e.g., by fine-tuning parameters) magnetic field aging, affine, imprinting, wear, or other conditions detrimental to the performance (operation) of memory array 310. Microprocessor 320 can initiate and manage evaluations (test programs) related to detecting such conditions. In some cases, the microprocessor can adjust the fine-tuning parameters by adjusting the values ​​stored in the mode register or other reprogrammable memory orientations on memory die 305 (in some cases, including the orientation for memory array 310). Alternatively or concurrently, the microprocessor can be used to execute a built-in self-test (BIST) program during manufacturing to similarly identify and correct (e.g., rectify) any number of problems.

[0063] Opcodes for microprocessor 320 may be stored in memory array 310 along with user data (received from a device outside memory die 305 and associated with commands from said device, such as data received via bus 340). Opcodes may contain BIOS instructions, boot addresses, complete boot sequences, or any other type of instruction executable by microprocessor 320. Microprocessor 320 may retrieve (e.g., read) operation instructions (e.g., as part of a boot program for microprocessor 320) from memory array 310 and execute the opcodes to perform any of the functions belonging to microprocessor 320 herein. Opcodes may be stored within memory array 310 in a physical location outside the logical address space for user data (e.g., associated with bus 340), at least below the current operational logic-to-physical address mapping. For example, opcodes for microprocessor 320 may be stored within one or more skip lines associated with a wear leveling program for memory array 310.

[0064] In some cases, multiple copies of the opcodes used for the microprocessor 320, or multiple copies of one or more subsets of opcodes, may be stored in the memory array 310. Alternatively, multiple copies of the opcodes used for the microprocessor 320, or multiple copies of one or more subsets of opcodes, may be stored in different corresponding memory arrays 310 on the memory die 305. Storing multiple copies of some or all of the opcodes used for the microprocessor 320 may provide redundancy or other reliability benefits as may be understood by those skilled in the art.

[0065] In some cases, error correction or detection codes (broadly referred to as error correction codes (ECCs)) can be used to protect opcodes used with microprocessor 320. For example, opcodes may be stored in memory array 310 in association with cyclic redundancy check (CRC) or other types of ECC, which can be used to verify the opcode when it is retrieved from memory array 310. Such techniques can provide redundancy or other reliability benefits as may be understood by those skilled in the art.

[0066] In some cases, memory die 305 may also store other data associated with microprocessor 320 (e.g., read, written, generated, or used by microprocessor 320) in memory array 310. For example, memory die 305 may store data collected or computed by microprocessor 320 (e.g., performance statistics, parameter values, runtime data) in memory array 310. For example, such data may be used by microprocessor 320 for performance tracking, parameter tuning (optimization), or any other function of microprocessor 320 herein. Other data may also be stored in memory array 310 in a manner similar to opcodes used by microprocessor 320.

[0067] Storing opcodes and / or other data for the microprocessor 320 in the memory array 310 can have one or more advantages. For example, the memory die 305 does not need to contain any ROM supporting the microprocessor 320 (e.g., for storing opcodes), which allows the memory die 305 to contain the on-die microprocessor 320 while saving die size or space compared to an embodiment with a separate ROM. Additionally, since the memory array 310 can have a larger amount of memory compared to a ROM, a relatively larger program (a larger number of instructions) can be stored within the memory array 310 compared to an embodiment with a separate ROM. Furthermore, unlike a ROM, the microprocessor 320 can be updated and written with new data to the memory array 310. Additional benefits will be apparent to those skilled in the art.

[0068] Because both the memory array 310 and the microprocessor 320 are fabricated to be contained within the same memory die 305, one or more fabrication processes (e.g., steps) or structures can be common to both the memory array 310 and the microprocessor 320, which can provide fabrication efficiency, performance benefits, or any combination thereof. For example, one or more metal layers can be fabricated and processed (e.g., patterned) in parallel to perform electrodes within both the memory array 310 and the microprocessor 320 at the same layer of the memory die 305.

[0069] Figure 4 This document describes an example of an instruction storage scheme 400 that supports opcode storage for on-chip microprocessors, based on the examples disclosed herein.

[0070] The instruction storage scheme 400 can be implemented at least partially using subarray set 405, which may be as referenced. Figure 3 The memory array 310 described herein or a subarray of another memory array as described herein. Figure 4The subarrays 405 illustrated in the examples may each be contained within the same group of memory arrays 310, but it should be understood that the teachings herein may be implemented using any number of subarrays 405 within any number of groups (e.g., one or more), and any number of memory arrays 310 within memory dies 305. Each subarray 405 may contain a set of rows (e.g., a set of word lines, each corresponding to a row of memory cells), wherein each row comprises a set of memory cells.

[0071] Within each subarray 405, a first number of rows can be used to store user data (e.g., at any given time). The memory cells within the first number of rows may be contained in a first subset of memory cells within subarray 405 (or alternatively, a first subset of memory cells within memory array 310). The rows (or memory cells) in the first subset may have physical addresses corresponding to the logical addresses present in the logical address space of memory array 310 and thus may be accessed based on commands received via bus 340 (e.g., commands received from host device 105).

[0072] Within each subarray 405, a second number of rows may not be available for storing user data (e.g., at any given time). The memory cells within this second number of rows may be included in a second subset of memory cells within subarray 405 (or, alternatively, a first subset of memory cells within memory array 310). Rows (or memory cells) in this second subset may have physical addresses corresponding to which the logical addresses do not exist within the logical address space for memory array 310 and may therefore be inaccessible based on commands received via bus 340 (e.g., commands received from host device 105). Therefore, the physical address space for memory array 310 may be larger than the logical address space for memory array 310. However, the rows in the second subset may be accessible to microprocessor 320, controller 315, or other on-die entities because such on-die entities may be able to directly access memory cells within memory array 310 based on their physical addresses or may otherwise access the entire physical address space for memory array 310.

[0073] In some cases, at least some of the rows within the second subset can be used for wear leveling within memory array 310. These rows may be referred to as gap rows or skip rows. When user data stored in the first row of the first set is relocated as part of the wear leveling process, the user data can be transferred to the skip rows, and the logical address associated with the user data can be remapped from the physical address of the first row to the physical address of the skip rows. In some cases, any information stored in the skip rows can be transferred to the first row, thus replacing previously stored user data in the first row, or transferred to another row within the memory array to free up space for the user data. Depending on the wear leveling algorithm, the user data can later be relocated and transferred further away from the skip rows, back to the first row, or to another row within memory array 310.

[0074] The physical orientation of information (user data, opcodes for microprocessor 320, or other data for microprocessor 320) stored in memory array 310 can be rotated (cyclically) through memory array 310 or otherwise varied over time according to a wear leveling algorithm, such that information accessed more frequently (and therefore the logical addresses accessed more frequently) is not always stored in the same physical row. Wear leveling can be performed on a scheduled (e.g., periodic) or other basis (e.g., in response to access counts associated with one or more rows reaching a threshold). As the physical storage orientation of information rotates, the logical-to-physical address mapping can be updated so that the logical addresses used for user data similarly rotate (e.g., cyclically) through the corresponding subset of physical address space.

[0075] Therefore, the physical location (and thus the physical address) of skipped rows within memory array 310 can be dynamic (changing over time during the operation of memory array 310), but is at least partly due to wear leveling procedures (e.g., due to user data being relocated further away from the physical row, or due to physical rows being reserved for potential later relocation of user data to the physical row). Any physical row not currently used to store user data can be considered a skipped row. Thus, within memory array 310, the physical location of opcodes and other data for microprocessor 320 can change over time because this information is relocated according to the wear leveling algorithm and circulates (rotates) through memory array 310 and because of the execution of associated wear leveling procedures.

[0076] exist Figure 4In an example, each subarray 405 may contain at least one corresponding skip line 410. For example, subarray 405-a may contain skip line 410-a; subarray 405-b may contain skip line 410-b; subarray 405-c may contain skip line 410-c; and subarray 405-d may contain skip line 410-d. For example, skip line 410-a may store a first portion of an opcode, skip line 410-b may store a second portion of an opcode, and skip line 410-c may store a third portion of an opcode. The opcode stored in the skip line 410 may be any instance of an opcode for a microprocessor as described elsewhere herein (e.g., BIOS code or other executable instructions for a microprocessor), and in some cases, other data associated with the microprocessor (e.g., generated, manipulated, or otherwise made available to the microprocessor) may similarly be stored in the skip line 410. In some instances, it is not necessary to use all skip lines 410 of all subarrays 405 to store opcodes or other data associated with the microprocessor, and therefore one or more skip lines 410 (e.g., skip line 410-d) may be empty at least when the memory die 305 first begins operation.

[0077] In some instances, the skipped row 410 within subarray 405 may initially be located at the end of subarray 405 and therefore may have a physical address preceding or following the physical address of one or more redundant rows. Redundant rows may alternatively be referred to as repair elements and may also be included at least initially in a second subset of rows outside the logical address space. One or more redundant rows may then be located at one or more corresponding physical memory addresses following or preceding one or more dummy rows, which may be included at the very end of subarray 405 to avoid associated manufacturing defects being linked to the rows used to store information.

[0078] Because the opcodes and / or other data for the microprocessor 320 are stored in the skip line 410, these opcodes and / or data may not be accessible via external commands (e.g., they may be hidden from the host device 105). For example, the skip line may not be accessible to entities outside the die (e.g., the host device 105), at least in part because the skip line may have a physical address but the data stored therein may not have a corresponding logical address. However, the microprocessor 320 or controller 315 may be operable to retrieve opcodes and / or other data from the skip line 410 and modify the opcodes and / or other data. Thus, the microprocessor 320 may be fully bootable from the opcodes stored in the memory array 310 and may also have available storage space within the memory array 310 to read and write runtime data that may be inaccessible to an external user (e.g., the host device 105).

[0079] While some aspects of the teachings herein are explained with reference to rows of memory cells, it should be understood that the teachings herein can be applied to any grouping of memory cells and are not limited to memory cells physically arranged in rows.

[0080] Figure 5 A block diagram 500 illustrates a memory die 505 supporting opcode storage for an on-die microprocessor, according to an embodiment of this disclosure. The memory die 505 may be as described in reference... Figures 1 to 4 Examples of aspects of the described memory die. Memory die 505 may include memory array 510, microprocessor 515, command component 520, write component 525, wear leveling component 530, mapping component 535, address identification component 540, boot component 545, array management component 550, and array operation component 555. Each of these modules may communicate directly or indirectly with each other (e.g., via one or more buses or other signal paths).

[0081] Memory array 510 may store instructions for a microprocessor contained on the same die as memory array 510. Microprocessor 515 may execute the instructions. In some cases, boot component 545 may boot the microprocessor based on the execution of the instructions. In some cases, the instructions contain BIOS code for the microprocessor.

[0082] Command component 520 may receive a command to write data to memory array 510 from a source outside the die after (e.g., via microprocessor 515) at least some of the instructions. Write component 525 may write data to memory array 510 based on the command.

[0083] Wear leveling component 530 can transfer data from a first set of memory cells within memory array 510 to a second set of memory cells within memory array 510 after data has been written to memory array 510. In some instances, memory array 510 can use the first set of memory cells to store the instructions after transferring data from the first set of memory cells. In some cases, the data is transferred based on a program configured to reduce the difference between a first wear level of the first set of memory cells and a second wear level of the second set of memory cells. In some cases, the first subset of memory cells within memory array 510 is used to store data in response to an external command. In some cases, the second subset of memory cells within memory array 510 supports the program in which the instructions are stored. In some instances, wear leveling component 530 may be included in microprocessor 515 or in a separate controller on memory die 505.

[0084] In some instances, memory array 510 may contain rows of memory cells associated with corresponding physical addresses. In some such cases, mapping component 535 may map the corresponding physical addresses to corresponding logical addresses in a logical address set for a first subset of the rows, wherein the instructions are stored in one or more rows of memory cells contained in a second subset of the rows, the second subset not overlapping with the first subset.

[0085] Address identification component 540 can identify logical addresses in the logical address set based on the command. In some instances, address identification component 540 can identify physical addresses based on the logical addresses and the mapping, wherein at least a portion of the data is written to a row of memory cells contained in the first subset and associated with the physical address.

[0086] Array management component 550 can determine statistics associated with the operational memory array 510. Array management component 550 can be a component of a microprocessor. Therefore, the determination can be performed by a microprocessor. In some instances, write component 525 can write indications of statistics associated with the operational memory array to the memory array 510.

[0087] In some instances, array management component 550 may determine the values ​​of parameters used to operate memory array 510. In some instances, write component 525 may write an indication of the values ​​of the parameters used to operate the memory array to the memory array. Array operation component 555 may operate the memory array based on the values ​​of the parameters determined by array management component 550. In some instances, array operation component 555 may be contained in microprocessor 515 or in a separate controller contained on memory die 505.

[0088] Figure 6 The diagram illustrates one or more methods 600 for storing opcodes for a microprocessor on a die, according to aspects of this disclosure. Operation of method 600 may be implemented by a memory die or its components as described herein. For example, operation of method 600 may be performed as described in reference... Figure 5 The described memory die performs the function. In some instances, the memory die can execute a set of instructions to control the functional elements of the memory die to perform the described function. Alternatively, the memory die may use dedicated hardware to perform aspects of the described function.

[0089] At 605, the memory die can store instructions for a microprocessor contained on the same die as the memory array within the memory array. The operation of 605 can be performed according to the method described herein. In some instances, it can be performed by, as referenced... Figure 5 The described memory array performs the operation of 605.

[0090] At 610, the memory die can execute instructions via a microprocessor. Operations at 610 can be performed according to the methods described herein. In some instances, this can be achieved by, as referenced... Figure 5 The described aspects of the microprocessor performing the operations of 610.

[0091] At 615, the memory die can receive a command to write data to the memory array from an external source after instructions have been executed by the microprocessor. The operation at 615 can be performed according to the method described herein. In some instances, it can be performed by, as referenced... Figure 5 The described command component performs the operation of 615.

[0092] At 620, the memory die can write data to the memory array based on the command. The operation at 620 can be performed according to the method described herein. In some instances, it can be performed by, as referenced... Figure 5 The described aspect of the write component performing the 620 operation.

[0093] In some instances, the device as described herein may perform one or more methods, such as method 600. The device may include features, means, or instructions (e.g., processor-executable instructions stored on a non-transitory computer-readable medium) for: storing instructions for a microprocessor contained on the same die as the memory array within the memory array; executing the instructions via the microprocessor; receiving, after executing the instructions via the microprocessor, a command to write data to the memory array from a source outside the die; and writing data to the memory array based on the command.

[0094] Some examples of the method 600 and apparatus described herein may additionally include operations, features, means, or instructions for: transferring the data from a first set of memory cells within the memory array to a second set of memory cells within the memory array after the data has been written to the memory array; and storing the instructions using the first set of memory cells after the data can be transferred.

[0095] In some instances of the method 600 and apparatus described herein, the data may be transmitted based on a program configured to reduce the difference between a first degree of wear and tear on the first set of memory cells and a second degree of wear and tear on the second set of memory cells.

[0096] In some instances of the method 600 and apparatus described herein, a first subset of memory cells within the memory array may be used to store data in response to an external command, and a second subset of memory cells within the memory array may support the program, wherein the instructions may be stored using the second subset of memory cells.

[0097] In some instances of the method 600 and apparatus described herein, the memory array may comprise rows of memory cells associated with corresponding physical addresses. Additionally, the memory array may include operations, features, means, or instructions for mapping the corresponding physical addresses to corresponding logical addresses in a logical address set for a first subset of the rows, wherein the instructions may be stored in one or more rows of memory cells that may be contained in a second subset of the rows, the second subset not overlapping with the first subset.

[0098] Some examples of the method 600 and device described herein may additionally include operations, features, means, or instructions for: identifying logical addresses in the set based on the command; and identifying physical addresses based on the logical addresses and the mapping, wherein at least a portion of the data may be written to a row of memory cells contained in the first subset and associated with the physical address.

[0099] Some examples of the method 600 and device described herein may additionally include operations, features, means, or instructions for starting a microprocessor based on executing the instructions.

[0100] In some instances of the method 600 and device described herein, the instructions contain BIOS code for a microprocessor.

[0101] Some examples of the method 600 and apparatus described herein may additionally include operations, features, means, or instructions for: determining statistics associated with operating the memory array via the microprocessor; and writing an indication of the statistics into the memory array.

[0102] Some examples of the method 600 and apparatus described herein may additionally include operations, features, means, or instructions for: determining, by the microprocessor, values ​​of parameters for operating the memory array; writing an indication of the values ​​of the parameters into the memory array; and operating the memory array according to the values ​​of the parameters.

[0103] Figure 7 The diagram illustrates one or more methods 700 for storing opcodes for a microprocessor on a die, according to aspects of this disclosure. Operation of method 700 may be implemented by a memory die or its components as described herein. For example, operation of method 700 may be performed as described in reference... Figure 5 The described memory die performs the function. In some instances, the memory die can execute a set of instructions to control the functional elements of the memory die to perform the described function. Alternatively, the memory die may use dedicated hardware to perform aspects of the described function.

[0104] At 705, the memory die can store instructions for a microprocessor contained on the same die as the memory array within the memory array. The operation of 705 can be performed according to the method described herein. In some instances, it can be achieved by, as referenced... Figure 5 The described memory array performs the operations of 705.

[0105] At 710, the memory die can execute instructions via a microprocessor. Operations at 710 can be performed according to the methods described herein. In some instances, this can be achieved by, as referenced... Figure 5 The described aspects of the microprocessor performing the operations of the 710.

[0106] At 715, the memory die can receive a command to write data to the memory array from an external source after instructions have been executed by the microprocessor. The operation at 715 can be performed according to the method described herein. In some instances, it can be performed by, as referenced... Figure 5 The described command component performs the operations of 715.

[0107] At 720, the memory die can write data to the memory array based on the command. The operation at 720 can be performed according to the method described herein. In some instances, it can be performed by, as referenced... Figure 5 The described aspect of the write component performing the 720 operation.

[0108] At 725, after the data is written to the memory array, the memory die can transfer the data from the first memory cell set within the memory array to the second memory cell set within the memory array based on a procedure configured to reduce the difference between a first wear level of the first memory cell set and a second wear level of the second memory cell set. The operation at 725 can be performed according to the method described herein. In some instances, it can be performed by, as referenced... Figure 5 The described loss balancing component performs 725 operations.

[0109] At 730, the memory die can store the instructions using the first set of memory cells after the data has been transferred. The operation of 730 can be performed according to the method described herein. In some instances, it can be performed by, as referenced... Figure 5 The described memory array performs the operations of 730.

[0110] It should be noted that the methods described herein are possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods described may be combined.

[0111] Describe an apparatus. The apparatus may include a semiconductor die, and the die may include a microprocessor, a memory array coupled to the microprocessor, and a bus operable to receive data from a source external to the semiconductor die. The apparatus may additionally include one or more pins, solder balls, or bonding pads coupled to the bus, and the one or more pins, solder balls, or bonding pads may be coupled to the source external to the semiconductor die. The memory array may be configured to store data received via the bus in a first subset of memory cells of the memory array, and the memory array may be configured to store instructions executable by the microprocessor in a second subset of memory cells of the memory array.

[0112] In some instances, the second subset of memory cells may be configured to support procedures for balancing the wear and tear of the memory cells in the memory array.

[0113] In some instances, the microprocessor or controller contained on the semiconductor die may be configured to relocate data and instructions received via the bus into the memory array based on the program.

[0114] In some instances, the memory array may be associated with a logical address space for data received via the bus, and the second subset of memory cells may be located outside the logical address space.

[0115] In some instances, the memory array comprises multiple rows of memory cells, each of which is associated with a corresponding physical address within a physical address space that is larger than the logical address space for data received via the bus, and the microprocessor or controller contained on the semiconductor die is configured to map a subset of the physical address space to the logical address space for data received via the bus, the subset of the physical address space corresponding to the first subset of memory cells.

[0116] In some instances, the microprocessor may be configured to retrieve the instructions from the second subset of memory cells; and execute a startup program based on the instructions.

[0117] In some instances, the instructions contain BIOS code for the microprocessor.

[0118] In some instances, the microprocessor may be configured to calculate one or more performance statistics of the memory array; and to store data associated with the one or more performance statistics within the second subset of memory cells.

[0119] In some instances, the microprocessor may be configured to determine the values ​​of parameters used to operate the memory array; and to write indications of the parameters into the second subset of memory cells.

[0120] In some instances, the memory array comprises subarray sets, each of which contains at least one row of memory cells within the second memory cell subset.

[0121] Describe an apparatus. The apparatus may include: a microprocessor contained on a die; and a memory array contained on the die, wherein the memory array includes a first number of memory cell rows for storing instructions executable by the microprocessor; and a second number of the memory cell rows for storing data associated with access commands received by the apparatus.

[0122] Some instances of the device may include a wear leveling component configured to relocate the data and instructions within the memory array.

[0123] In some instances, the wear leveling component may be configured to rotate the addresses associated with the first number of rows to switch the row set from being included in the first number to being included in the second number.

[0124] In some instances, the first number of rows are also used to store data associated with the microprocessor.

[0125] In some instances, the microprocessor can be configured to be started based on the instructions.

[0126] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate signaling as a single signal; however, those skilled in the art will understand that a signal can represent a bus of signals, where the bus can have various bit widths.

[0127] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports the flow of electrons between them. Components are considered to be in electronic communication with each other (or in conductive contact, connected, or coupled) if any conductive path exists between them that can support the flow of signals at any given time. At any given time, the conductive path between components that are electronically connected (or in conductive contact, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, can be used to interrupt the signal flow between connected components for a period of time.

[0128] The term "coupling" refers to the condition that shifts from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via a conductive path; in a closed-circuit relationship, signals can travel between components via a conductive path. When a component, such as a controller, couples other components together, it initiates a change that allows signals to flow between other components via conductive paths that were previously not permitted.

[0129] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. When a controller isolates two components from each other, it prevents signals from flowing between the components using previously permitted conductive paths.

[0130] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In others, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0131] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, a drain, and a gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or a channel. If the channel is n-type (i.e., the majority carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be called a p-type FET. The channel may be end-capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0132] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior" to other instances. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0133] In the accompanying drawings, similar components or features may have the same reference numerals. Additionally, various components of the same type can be distinguished by a dash following the reference numeral and a second numeral used to differentiate them among similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0134] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof.

[0135] The various illustrative blocks and modules described herein can be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0136] The functionality described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented as software executed by a processor, the functionality may be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functionality described above may be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functionality may also be physically located in various locations, including distributed implementations such that portions of the functionality are implemented in different physical locations. And, as used herein, the word “or” used in the list of items included in the claims (e.g., a list of items beginning with phrases such as “at least one of…” or “one or more of…”) indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase “based on” should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as “based on condition A” may be based on both condition A and condition B. In other words, as used herein, the phrase “based on” should also be interpreted as the phrase “at least partially based on”.

[0137] The description provided herein enables those skilled in the art to make or use this disclosure. Those skilled in the art will appreciate the various modifications that can be made to this disclosure, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An electronic device comprising: Semiconductor dies, comprising: microprocessor; A memory array coupled to the microprocessor; and A bus operable to receive data from a source outside the semiconductor die, wherein: The memory array is configured to store data received via the bus in a first subset of memory cells within the memory array; and The memory array is configured to store instructions executable by the microprocessor in a second subset of memory cells, wherein the memory array is associated with a logical address space for data received via the bus, and the second subset of memory cells is located outside the logical address space; and One or more pins, solder balls, or bonding pads coupled to the bus, wherein the one or more pins, solder balls, or bonding pads may be coupled to the source outside the semiconductor die.

2. The electronic device of claim 1, wherein the second subset of memory cells is configured to support a procedure for balancing the wear and tear of the memory cells of the memory array.

3. The electronic device of claim 2, wherein the microprocessor or controller on the semiconductor die is configured to: Based at least in part on the program, the data received via the bus and the instructions are relocated within the memory array.

4. The electronic device according to claim 1, wherein: The memory array includes multiple rows of memory cells, each of which is associated with a corresponding physical address in a physical address space that is larger than the logical address space used for data received via the bus. and The microprocessor or controller contained on the semiconductor die is configured to map a subset of the physical address space to the logical address space for data received via the bus, the subset of the physical address space corresponding to the first subset of memory cells.

5. The electronic device of claim 1, wherein the microprocessor is configured to: Retrieve the instructions from the second subset of memory cells; and The startup procedure is executed at least in part based on the instructions.

6. The electronic device of claim 1, wherein the instructions include Basic Input / Output System (BIOS) code for the microprocessor.

7. The electronic device of claim 1, wherein the microprocessor is configured to: Calculate one or more performance statistics of the memory array; and The data associated with the one or more performance statistics is stored in the second subset of memory cells.

8. The electronic device of claim 1, wherein the microprocessor is configured to: Determine the values ​​of the parameters used to operate the memory array; and The indication of the parameters is written into the second subset of memory cells.

9. The electronic device of claim 1, wherein the memory array comprises a plurality of subarrays, each of the plurality of subarrays comprising at least one row of memory cells within the second subset of memory cells.

10. A method for an electronic device, the method comprising: Instructions for a microprocessor contained on the same die as the memory array are stored within the memory array, wherein the memory array comprises rows of memory cells associated with corresponding physical addresses; For a first subset of the rows, the corresponding physical addresses are mapped to corresponding logical addresses in a logical address set, wherein the instructions are stored in one or more memory cell rows contained in a second subset of the rows, the second subset not overlapping with the first subset; The instructions are executed by the microprocessor; After the instructions are executed by the microprocessor, a command to write data to the memory array is received from a source outside the die; and The data is written to the memory array, at least in part, based on the command.

11. The method of claim 10, further comprising: After the data is written to the memory array, the data is transferred from the first set of memory cells in the memory array to the second set of memory cells in the memory array. and After the data is transmitted, the instructions are stored using the first set of memory cells.

12. The method of claim 11, wherein the data is transmitted based at least in part on a procedure configured to reduce the difference between a first wear level of the first memory cell set and a second wear level of the second memory cell set.

13. The method according to claim 12, wherein: The first subset of memory cells within the memory array is used to store data in response to external commands; and The program is supported by a second subset of memory cells within the memory array, wherein the instructions are stored using the second subset of memory cells.

14. The method of claim 10, further comprising: Logical addresses in the set of logical addresses are identified, at least in part, based on the command. and The physical address is identified at least in part based on the logical address and the mapping, wherein at least a portion of the data is written to a row of memory cells contained in the first subset and associated with the physical address.

15. The method of claim 10, further comprising: The microprocessor is started at least in part based on the execution of the instructions.

16. The method of claim 10, wherein the instructions include Basic Input / Output System (BIOS) code for the microprocessor.

17. The method of claim 10, further comprising: The microprocessor determines statistics associated with operating the memory array; and The statistical indication is written into the memory array.

18. The method of claim 10, further comprising: The microprocessor determines the values ​​of the parameters used to operate the memory array; Write the indication of the value of the parameter into the memory array; and The memory array is operated according to the value of the parameter.

19. An electronic device comprising: Microprocessors contained on a bare die; and A memory array contained on the die, wherein the memory array comprises: A first number of rows of memory cells are used to store instructions that can be executed by the microprocessor; and The second number of memory cell rows for storing data associated with access commands received by the device, wherein rows in the first number of rows and the second number of rows are associated with corresponding physical addresses, and wherein the electronic device is configured to map the corresponding physical addresses for the second number of rows to corresponding logical addresses in a set of logical addresses, and wherein the first number of rows for storing the instructions do not overlap with the second number of rows for storing the data.

20. The electronic device of claim 19, further comprising: A wear leveling component is configured to relocate the data and instructions within the memory array.

21. The electronic device of claim 20, wherein the loss balancing component is configured to rotate the address associated with the first number of rows to switch the row set from being included in the first number to being included in the second number.

22. The electronic device of claim 20, wherein the first number of rows are also used to store data associated with the microprocessor.

23. The electronic device of claim 19, wherein the microprocessor is configured to be activated at least in part based on the instructions.

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